Remote memory access using memory mapped addressing among multiple compute nodes

Abstract

An example method for facilitating remote memory access with memory mapped addressing among multiple compute nodes is executed at an input / output (IO) adapter in communication with the compute nodes over a Peripheral Component Interconnect Express (PCIE) bus, the method including: receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node; generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a base address register (BAR) of the second compute node; and configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node.

Description

TECHNICAL FIELD[0001]This disclosure relates in general to the field of communications and, more particularly, to remote memory access with memory mapped addressing among multiple compute nodes.BACKGROUND[0002]Compute nodes such as microservers and hypervisor-based virtual machines executing in a single chassis can provide scaled out workloads in hyper-scale data centers. Microservers are an emerging trend of servers for processing lightweight workloads with large numbers (e.g., tens or even hundreds) of relatively lightweight server nodes bundled together in a shared chassis infrastructure, for example, sharing power, cooling fans, and input / output components, eliminating space and power consumption demands of duplicate infrastructure components. The microserver topology facilitates density, lower power per node, reduced costs, and increased operational efficiency. Microservers are generally based on small form-factor, system-on-a-chip (SoC) boards, which pack processing capability...

AI Technical Summary

Benefits of technology

The patent text describes a communication system that allows multiple compute nodes to access remote memory with memory mapped addressing. The system includes a chassis with multiple compute nodes and a shared input / output (I / O) adapter. The I / O adapter presents network and storage devices on a PCIE bus to the compute nodes, which appear as a PCIE device to other compute nodes in the chassis. The system allows for efficient communication among the compute nodes and provides a scalable and cost-effective solution for hyper-scale data centers.

Problems solved by technology

Yet, sharing data across the compute nodes with more effective and efficient inter-process communication has always been a challenge.

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