325 results about "Memory type" patented technology

A method for analyzing advertisements and advertising campaigns. Important images are selected from one or more advertisements and then ranked. The most important images are then assigned to a category which preferably corresponds to a memory type, such as knowledge, emotion, or action. The relative numbers of images in each type determine the focus of the advertisement(s), and may be used to tailor the memory type(s) of subsequent advertisements.

One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.

A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.

A memory profiling system profiles memory objects in various memory devices and identifies memory objects as candidates to be moved to a more efficient memory device. Memory object profiles include historical read frequency, write frequency, and execution frequency. The memory object profile is compared to parameters describing read and write performance of memory types to determine candidate memory types for relocating memory objects. Memory objects with high execution frequency may be given preference when relocating to higher performance memory devices.

A method and a motherboard for automatically determining the memory type. By applying the characteristics of different operational voltages for various dynamic random access memory modules, a software program is used to drive a control signal and to automatically adjust the control voltage of the dynamic random access memory. An automatic detection of the types of the dynamic random access memory is obtained. The objectives of protecting the dynamic random access memory and to allow the dynamic random access memory to operate normally can thus be achieved. The invention not only provides the detection mechanism for accessing the dynamic random access memory during the initial activation of the computer system, but also determines the voltages required by the memory module for the computer system to enter various power saving modes.

A computing system and methods for memory management are presented. A memory or an I/O controller receives a write request where the data two be written is associated with an address. Hint information may be associated with the address and may relate to memory characteristics such as an historical, O/S direction, data priority, job priority, job importance, job category, memory type, I/O sender ID, latency, power, write cost, or read cost components. The memory controller may interrogate the hint information to determine where (e.g., what memory type or class) to store the associated data. Data is therefore efficiently stored within the system. The hint information may also be used to track post-write information and may be interrogated to determine if a data migration should occur and to which new memory type or class the data should be moved.

Computer technology supports multiple byte order formats, separately or simultaneously. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. The PAT has a plurality of entries. Each entry indicates a memory type and a byte order format for a physical address, wherein a plurality of attribute bits and a virtual address are associated with the physical address. A portion of the attribute bits are utilized to select one of the entries. In another embodiment, a memory type range register (MTRR), which is programmable, is utilized to indicate byte order format. The MTRR is configured to indicate a memory type and a byte order format for a range of physical addresses, wherein the memory type and range register (MTRR) receives a physical address and provides a corresponding memory type and a corresponding byte order format.

The present system enables receiving a request from an I/O device to translate a virtual address to a physical address to access the page in system memory. One or more memory attributes of the page defining a cacheability characteristic of the page is identified. A response including the physical address and the cacheability characteristic of the page is sent to the I/O device.

A system and method are provided for bypassing cache memory when reading data from system memory particularly when the primary memory could include memory types where the read operation mixes non-data with data. A system and method are provided for bypassing and invalidating cache memory when writing data to system memory particularly when the primary memory could include memory types where the write operation mixes non-data with data.

A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.

A system is capable of receiving Fast Page mode, Extended Data Out mode, Burst Extended Data Out mode, or a combination of these memory devices. A method of determining the type of memory present allows the system to adjust internal memory access signals in accordance with the type of memory installed. The system may be shipped with a first type of memory, and then upgraded to a second type of memory by the user to improve overall system performance. A first bank of memory may be of a first type, and a second bank may be of another type. The user may make cost versus performance decisions when upgrading memory types or capacities.

The invention belongs to the technical field of the permanent-magnet brushless machine manufacture, particularly to a stator permanent-magnet machine adaptable to the application fields of wide speed regulation and high efficiency, such as the mixing dynamic car and the electric automobiles, composed of a stator, a rotor, an armature winding and an NdFeB permanent magnet, characterized in that, the original NdFeB permanent magnet is saved, an ALNiCo permanent magnet and a magnetizing winding for adjusting the magnetic field strength and the magnetic flux density of the ALNiCo permanent magnet are arranged on the stator. The invention has the advantage that, the ALNiCo permanent magnet and the magnetizing winding are first inducted in the stator permanent-magnet, to cause that the flux memory type stator permanent-magnet machine inherits the advantages of large power intensity and good fault tolerant performance of the stator permanent-magnet machine, meanwhile solves the defect that it is difficult to realize the weak magnetic control, the range of the constant power speed control is small and the operating efficiency of the constant power operation is low.

A common DRAM controller is provided for supporting a plurality of memory types such as double data rate or quad data rate mode or types. The controller is adapted to use a number of clock signals to process data. The controller can further delay the data for a predetermined time period and capture the same.

Circuits and methods that use third dimension memory as a different memory technology are described. The third dimension memory can be used for application specific data storage and/or to emulate conventional memory types such as DRAM, FLASH, SRAM, and ROM or new memory types as they become available. A processor-memory system implements a memory operable as different memory technologies. The processor-memory system includes a logic subsystem and a memory subsystem, which includes third dimension memory cells. The logic subsystem implements memory technology-specific signals to interact with the third dimension memory cells as memory cells of a different memory technology. As such, the memory subsystem can emulate different memory technologies. The logic subsystem can be fabricated FEOL on a substrate and the memory subsystem can be fabricated BEOL directly on top of the substrate. An interlayer interconnect structure can electrically couple the logic subsystem with the memory subsystem.

A steerable structure (21, 27) of the catheter or endoscope type, the structure comprising an elastically or deformable longitudinal body (22, 28) including at least one actuator (16, 38) of material of the shape memory type incorporated longitudinally with the body (22, 28) together with Joule-effect heater means enabling the actuator (16, 38) to be contracted longitudinally in order to cause the longitudinal body (22, 28) to bend, wherein the actuator (16, 38) extends over at least one portion of the body (22, 28) that presents varying stiffness.

The invention discloses a heterogeneous memory management method and device. The method includes: when a process is created and a memory request is received, determining an applied memory type according to an identifier carried in the memory request; allocating a corresponding memory according to the determined memory type. By the method and device, a system-level process is ensured to be allocated to a fast DRAM (dynamic random access memory) for data processing, and a process for big data processing is reasonably put in an NVM (non-volatile memory) to run. By the method and device, the different types of memories perform data processing of specific types, so that influence on data processing due to access speed difference of the DRAM and the NVM is reduced greatly. On the other hand, when the allocated NVM is recycled, a recycling delay mechanism is adopted, and waiting time for big data processing process access is prolonged, so that the problem of deadlocking possibly caused by access to the DRAM and the NVM is avoided.