171 results about "JFET" patented technology

The invention relates to an audio decoding output stage circuit and audio equipment, the audio decoding output stage circuit comprises an I / V conversion module and a low-pass filtering module, and the I / V conversion module comprises a conversion circuit, a crossed diamond amplification circuit, an overcurrent protection circuit and a Roche network circuit; the conversion circuit comprises a JFET (Junction Field Effect Transistor) audio operational amplifier chip and an I / V (Input / Output) conversion resistor and is used for converting an input current into an analog voltage signal; the crossed diamond amplifying circuit can reduce the input offset voltage; the over-current protection circuit can carry out over-current protection; the rowbell network circuit can prevent high-frequency self-oscillation of the power output stage; and the low-pass filtering module comprises a filtering circuit and an ultrahigh frequency filtering circuit arranged at the output end of the audio decoding output stage circuit. The scheme can bring high-performance sound performance, and has the advantages of lower distortion, higher conversion rate, low output impedance and large pushing current.

A field-effect transistor with a buried gate, and a method of making the same. A volume of semiconductor material includes first and second ends and left and right sides. A source is located at the first end, a drain is provided, a left first gate structure is located at the left side, and a right first gate structure is located at the right side. A second, buried gate is located between and spaced apart from the source and the drain and the left and right first gate structures so as to be surrounded in first and second dimensions by the semiconductor material. The second gate divides a channel into multiple paths for current to flow between the source and the drain. The second gate includes a projection extending in a third dimension and presenting an exposed surface operable to receive a voltage.

A common-source cascode switching system and its operation method, as well as a half-bridge circuit, are disclosed. The common-source cascode switching system includes a JFET and a MOSFET coupled in series between the drain and source terminals, and a driving circuit. The driving circuit includes: a JFET driver that receives an input signal and outputs a JFET drive signal to a capacitor coupled in series with the gate of the JFET; a switch coupled between the gate and source terminals of the JFET and configured to respond to the input signal; and a comparator for comparing the JFET gate voltage with a threshold. The driving circuit also includes a MOSFET driver circuit to drive the MOSFET in a MOSFET on state during an input signal on state, and to drive the MOSFET in either a MOSFET off state or a MOSFET on state during an input signal off state in response to a comparison signal from the comparator.

A kind of anti-radiation reinforced SiC super-junction JFET structure and preparation method, from bottom to top are in order: drain metallization layer, N+ substrate layer, N buffer layer, P column region, N column region, P-base region, current expansion region, N+ source region, P+ gate region, isolation dielectric layer, gate metallization layer, source metallization layer.P column region and N column region are arranged alternately on the upper surface of N buffer layer, P column region is symmetrically arranged, and N column region is arranged between two P column regions.P column region and P-base region form a P-type doped region as a whole, and are connected with source metallization layer.Electrically conductive channel structure is formed between P+ gate region and P-base region, and the opening and closing of channel are realized by controlling the voltage on P+ gate region.The application effectively solves the problem of electric field concentration caused by high-energy charged particle bombardment in the device, reduces local high temperature, and greatly improves the anti-single-particle radiation capability of SiC JFET.

The invention firstly comprises a junction field effect transistor (JFET), namely a SiC JFET, which is completely made of SiC. The transistor is preferably manufactured by adopting a top-down method, and the manufacturing process is suitable for large-scale production. The electrical properties of the proposed SiC JFET have been evaluated under dry conditions and in a liquid medium. The concept feasibility of the SiC JFET as a biosensor 0 is verified through pH value measurement. The sensitivity of the SiC JFET provided by the invention is up to 495 mV / ph, that is, the sensitivity is nearly 100 times higher than the theoretical Nernst limit. Therefore, the device is suitable for various in-vitro and in-vivo biochemical detection applications because the device meets performance indexes generally required in the field, such as sensitivity and chemical stability, especially long-term stability.

A method of manufacturing a silicon carbide power device includes performing a first ion implantation process to form a JFET region in an epitaxial layer over a substrate. A patterned mask layer is formed on the epitaxial layer above the JFET region. A second ion implantation process is performed to form well regions at both sides of the JFET region. A first spacer is formed on sidewalls of the patterned mask layer. A third ion implantation process is performed to form a self-aligned heavily doped region in the well regions. A second spacer is formed on a side of the first spacer to shield a portion of the heavily doped region. A fourth ion implantation process is performed to form another self-aligned heavily doped region in the heavily doped region. A gate structure is formed after removing the patterned mask layer, the first spacer, and the second spacer.

The application relates to the technical field of semiconductors, in particular to a planar SiC MOSFET device structure and a manufacturing method thereof. The device structure comprises a substrate, an epitaxial layer located on the substrate, a doped region and a JFET region located on the epitaxial layer, wherein the substrate is a silicon carbide (SiC) substrate, and the epitaxial layer is a SiC epitaxial layer; the JFET region is located between the doped regions and is in contact with the doped regions; the upper surface of the JFET region, the upper surface of the doped region and the upper surface of the epitaxial layer are located on the same set surface, and the set surface is a concave surface; the concave part of the concave surface covers the specified region of the JFET region and the doped region, and the specified region is a region containing at least a channel of the doped region. Through the device structure, the on-resistance of the device is effectively reduced under the premise of guaranteeing the performance of the device except the on-resistance.

A field-effect transistor with a shielded source, and a method of making the same. A volume of semiconductor material includes first and second vertically spaced ends and first and second laterally spaced sides. First and second laterally spaced gates are provided in the volume of semiconductor material. A source is located at the first end between the first and second gates, a drain is provided, and a channel extends therebetween. The first gate includes a lower first gate portion spaced below and extending beneath the source so as to create a turn in the channel around the lower first gate portion.

The embodiment of the invention provides a metal oxide semiconductor cellular structure, a power chip and a preparation method of the metal oxide semiconductor cellular structure. Comprising a first conductive type substrate, a first conductive type epitaxial layer located on the substrate, a second conductive type active region formed in the epitaxial layer, and a first conductive type source layer formed in the active region; the cellular structure further comprises a second conduction type ohmic contact layer, and the second conduction type ohmic contact layer is at least partially located in the second conduction type active region. Wherein a junction field effect transistor (JFET) region of the cellular structure comprises a region provided with a second conduction type ohmic contact layer and other regions located in the junction field effect transistor (JFET) region, and the other regions are constructed as channel regions; the second conductivity type ohmic contact layer is connected to a junction field effect transistor (JFET) region. According to the invention, the transverse size of the unit cell is reduced so as to reduce the forward on-resistance, and the output performance of the device is improved.

The invention relates to the technical field of semiconductor devices, in particular to a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: providing a substrate with an epitaxial layer; sequentially forming a JFET layer and a first type doping layer on the epitaxial layer, wherein a cellular region and a bus region are defined on the surface of the first type doping layer; a second type doped column is formed by extending from the surface of the first type doped layer, the second type doped column penetrates through the first type doped layer and the JFET layer, and the bottom of the second type doped column is located in the epitaxial layer; a groove is formed in the second type doping column through etching, a second type doping area is reserved between the inner wall of the groove and the outer wall of the second type doping column, and the groove comprises a cellular groove formed in the cellular area and a bus groove formed in the bus area. The method has the advantages that the technological process is simple, and the uniform second-type doped region can be formed without accurately controlling the injection angle like a traditional method.

The invention discloses a vertical JFET (Junction Field Effect Transistor) power device for enhancing gate end driving capability by ohmic contact and a manufacturing method thereof, and belongs to the technical field of semiconductor power devices. In order to solve the problem of poor switching performance caused by high electrical resistivity of a grid active region and serious attenuation of a driving signal in the existing vertical JFET, the invention provides a metal ohmic contact layer (such as nickel) formed on the surface of the grid active region. And the low-resistance metal layer is connected in parallel with the grid electrode P region, and an efficient current path from the grid electrode contact end to each grid junction in the chip is constructed, so that the grid electrode resistance is greatly reduced, and the grid end driving capability is enhanced. According to the manufacturing method, an ohmic contact preparation step in the prior art is utilized, introduction of non-compatible materials such as polycrystalline silicon and complex procedures is not needed, and gate source short circuit is reliably prevented through the design of selectively reserving an insulating layer above a gate region. According to the invention, the switching speed and reliability of the device are improved, and excellent process compatibility and cost advantages are maintained.

The invention discloses a circuit for simplifying electroencephalogram signal detection, amplification and transmission, and relates to the technical field of electroencephalogram signal acquisition. Comprising a distributed JFET signal amplification module, a differential amplification and common-mode recovery module and a differential-to-single-ended module. The distributed JFET signal amplification module directly amplifies weak electroencephalogram signals at an electroencephalogram signal acquisition point, and noise is reduced and measurement errors caused by Vos are eliminated through cooperation of a JFET tube and an operational amplifier in combination with a reference current source and a zero setting circuit; the differential amplification and common-mode recovery module further amplifies the amplified differential signal and recovers a common-mode signal, so that the influence of the input current on a pre-stage circuit is reduced; the differential-to-single-ended module converts the differential signal into a single-ended signal and couples the single-ended signal to a specified common-mode voltage, so that ADC acquisition is facilitated. Interference in the electroencephalogram signal transmission process is effectively reduced, the authenticity and accuracy of signal collection are improved, complex digital bus control is not needed, the number of connecting lines is reduced, and connection between point locations is simplified.

A vertical junction field effect (JFET) semiconductor device according to some embodiments includes a drift layer, a channel layer on the drift layer, and a plurality of alternating trenches and mesas in the channel layer, wherein a first plurality of the trenches includes gate contact regions. A source metallization is on the mesas. The device includes a second different than the first plurality of trenches, wherein the source metallization is electrically connected to the drift layer at a bottom of the second trench.

A power metal oxide semiconductor field-effect transistor is radiation-hardened against a single-event gate rupture effect, and a method of making such a transistor is disclosed. A volume of semiconductor material includes first and second sides and a centrally located junction field effect transistor neck region. The metal oxide semiconductor field-effect transistor includes a source, a well located between the source and the JFET neck region, and a dielectric material. The well includes a first well portion and a second well portion. The second well portion is located between the first well portion and the JFET neck region and has a lower dopant concentration than the first well portion. The dielectric material overlies the first well portion, at least part of the second well portion, and at least part of the source. The dielectric material presents a thicker dielectric portion located over the second well portion.

This application belongs to the field of power device technology and provides a silicon carbide power device with improved BV and Ron, as well as its fabrication method and chip. By setting a first P-type well region in the top epitaxial region, a heavily doped P-type region is formed on the first P-type well region, and adjacent second P-type well regions are isolated by the top epitaxial region. At least the second P-type well regions are symmetrically arranged with heavily doped P-type regions, and the depth of the second P-type well region is less than the depth of the first P-type well region. This allows the JFET region inside the device to have a higher doping concentration of donor doping. While ensuring the ideal BVDSS of the device, the on-resistance can be effectively reduced and the current density of the device can be increased.

The invention discloses a method and a structure for integrating a double-gate JFET (junction field effect transistor) device in a bipolar junction transistor process, and the method comprises the steps: providing a substrate, and forming a buried layer structure, an epitaxial layer and an isolation structure of the bipolar junction transistor and the JFET device on the substrate; carrying out penetration doping and well region doping in the epitaxial layer; forming a collector crystalline region, a base crystalline region, a bottom gate crystalline region, a top gate crystalline region, a source crystalline layer and a drain crystalline region above the epitaxial layer; depositing a dielectric layer on the epitaxial layer, etching to form a base region window, and forming a heavily doped collector region, a heavily doped outer base region, a heavily doped bottom gate, a heavily doped top gate, a source region and a drain region through the base region window; s500, forming an emitter region window, and forming an emitter crystalline region in the emitter region window; and forming electrodes of the bipolar junction transistor and the JFET device on the dielectric layer. According to the invention, the high-speed bipolar junction transistor and the JFET device can be integrated in a single manufacturing process under the condition that a large amount of process complexity is not increased.

The present application relates to the field of geophysical exploration equipment, and relates to a multi-discrete current source low-noise JFET differential parallel amplifier, which comprises a JFET primary amplifier circuit and an IOA secondary amplifier circuit; the JFET primary amplifier circuit comprises a common-source amplifier circuit composed of two groups of JFET pairs in parallel, the drain of each group of JFET pairs is connected to the positive pole of a lithium battery, the source of the JFET pair is connected to the negative pole of the lithium battery through an NPN-type BJT, the gate of the JFET pair is connected to the output signal of one side of a differential coil, and the drain of the JFET pair serves as an output; the IOA secondary amplifier circuit adopts a subtractor structure and is connected to the two outputs of the JFET primary amplifier circuit through two input ends. Discrete current sources are used to supply power to two pairs of parallel JFETs, the parameter difference between JFET pairs is reduced, parallel method is used to reduce the background noise of JFET devices, and the advantages of low-noise amplification of JFET devices are exerted.

The application discloses a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle. The manufacturing method comprises the following steps: providing a semiconductor body; comprising a first surface; forming a barrier portion on the side of the first surface away from the semiconductor body; performing a preset number of operations of forming a side wall structure and a JFET region on the semiconductor body; wherein the side wall structure is located on both sides of the barrier portion; the JFET region is of a first conductivity type; removing the barrier portion and forming a central JFET region in the semiconductor body; wherein the central JFET region is coincident with the orthogonal projection of the barrier portion on the first surface; the ion concentration of the central JFET region is less than that of the JFET region; forming an insulating layer on the first surface; forming a gate electrode on the side of the insulating layer away from the first surface. The embodiment of the application can improve the voltage resistance of the gate oxide layer and reduce the resistance of the JFET region.

A multilayer semiconductor device includes: a substrate comprising silicon carbide (SiC); and an epitaxial transition layer on the substrate, the epitaxial transition layer comprising a first epitaxial oxide material or SiC. One or more epitaxial active regions comprising one or more second epitaxial oxide materials are formed on the epitaxial transition layer, and a metal layer is formed over the one or more epitaxial active regions, the metal layer comprising one or more electrical contacts. The multilayer semiconductor device includes one of the following: a metal-oxide-semiconductor field-effect transistor (MOSFET), a vertically conductive MOSFET, a lateral MOSFET, a metal-semiconductor field-effect transistor (MSFET), a bipolar junction transistor (BJT), a junction field-effect transistor (JFET), a metal-insulator-semiconductor (MIS) device, a PN device, a PNP device, an NPN device, or an insulated-gate bipolar transistor (IGBT).

A junction field-effect transistor that is normally off rather than normally on, and a method of making such a device. The junction field-effect transistor includes a volume of semiconductor material, a first gate located at a first side of the semiconductor material, a second gate located at a second side opposite and spaced apart from the first gate, a Schottky barrier diode, and a drain. The Schottky barrier diode is located at a first end of the semiconductor material between the first and second gates, and replaces a conventional source. The drain is located at the second end, opposite the diode, and a region of the semiconductor material between the diode and the drain provides a channel. The Schottky barrier diode conducts in a forward mode (i.e., the device is on) only when the anode-to-cathode voltage exceeds the metal-to-semiconductor barrier potential, which means the device is normally off.

The application discloses a trench gate silicon carbide MOSFET device and a manufacturing method thereof, and relates to the technical field of power semiconductor devices. The device has a substrate, an epitaxial layer on the substrate, and a drain below. A gate trench is above the epitaxial layer, and both sides of the gate trench are multi-stage gate trench integration areas, and an interlayer dielectric and a source are on the multi-stage gate trench integration areas. The gate trench has polycrystalline silicon and a gate dielectric, the multi-stage gate trench integration area includes a connection area, multi-stage gate trenches and a current expansion layer, the bottom has a shielding layer, and the shielding layer has polycrystalline silicon and a gate dielectric. The source is connected with the drain through the connection area, and is isolated from the multi-stage gate trenches through the interlayer dielectric, the shielding layer is of a second conductive type, and the rest is of a first conductive type. In the application, when the device is blocked, the electric field at the gate dielectric is reduced by applying zero or negative gate voltage, when the device is turned on, positive gate voltage is applied to inhibit JFET effect, improve turn-on capacity and reduce loss. When avalanche occurs, the multi-stage trench structure moves down the breakdown point, prolongs the heat transfer path, delays the melting of the metal, and enhances the avalanche robustness.

The invention provides a planar SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device integrated with a junction barrier Schottky diode and a manufacturing method. The planar SiC MOSFET device comprises a substrate; a first conductive type epitaxial layer; a second conductive type body region; the first conductive type source region-is formed in the second conductive type body region; the at least two second conductive type source regions are formed in the second conductive type body regions; the JFET region is arranged on the outer side of the second conductive type body region; the oxide layer is arranged on one side, deviating from the substrate, of the second conductive type body region and the first conductive type source region; the grid electrode is arranged on one side, deviating from the substrate, of the oxide layer; the gate-source dielectric layer is arranged on one side, deviating from the substrate, of the first conductive type source region and the second conductive type source region and covers the gate; the gate-source dielectric layer is provided with an active region groove; the Schottky metal layer is in contact with the first conductive type source region, and the second conductive type source region is in contact with the JEFT region; a source electrode covering the Schottky metal layer; and the drain electrode is arranged on the back surface of the substrate.

This invention relates to the field of semiconductor power device manufacturing technology, and discloses a SiC MOSFET structure with etched gate and low input capacitance, and its manufacturing method. The structure includes an N-type SiC substrate with an N-type SiC drift layer; a P-well, a heavily doped P-well region, and a heavily doped N-region are disposed within the surface of the N-type SiC drift layer; a gate oxide layer is disposed on the surface, and a discrete polysilicon gate is disposed above the gate oxide layer. The discrete polysilicon gate has an etched window to remove the polysilicon material directly above the JFET region; the surface of the discrete polysilicon gate is covered with an interlayer insulating dielectric; a source electrode and a polysilicon gate connection line are disposed on the front side, and the polysilicon gate connection line electrically shorts the strip-shaped polysilicon gate units separated by etching; a drain electrode is disposed on the back side. This invention reduces the plate area and lowers the input capacitance and reverse transfer capacitance by removing the polysilicon directly above the JFET region; and avoids potential floating by shorting the separated gate with the connection line, thus reducing switching losses.

The invention discloses a field effect transistor. A first JFET (Junction Field Effect Transistor) and a second MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) are respectively formed in first and second epitaxial layers with different forbidden bandwidths. A first gate region of the first JFET comprises a plurality of first buried layers arranged in parallel, and first channel regions are arranged between the first buried layers. The first source region and the drain region respectively form a top surface and a back surface of the first epitaxial layer. A second buried layer is formed on the top surface of the selected area of each first buried layer; the second epitaxial layer includes parallel first and second regions. The second MOSFET is formed in the first region, and a floating metal buried layer is formed on the top surface of the first source region and connected to the second drain region. The second region spans the second buried layer and the first epitaxial layer between the second buried layers; in the second region, JFET gate lead-out regions are formed on the top surface of the second buried layer, and Schottky contact alloy is formed on the surface between the JFET gate lead-out regions. According to the invention, the cascade connection of JFETs and MOSFETs made of materials with different forbidden bandwidths and the integration of Schottky diodes can be realized.

The planar junction field-effect transistor provides enhanced channel control. A method of making such a JFET is also disclosed. A volume of semiconductor material includes a first end and a second end, a source and a first gate are located at the first end, a drain is spaced apart from the source, and a channel is provided between the source and the drain. A second gate is located between the source and drain so as to be surrounded, or buried, in a first dimension and a second dimension by the semiconductor material, and thereby divides the channel into multiple non-linear channel paths. The gates cooperatively determine the channel paths and enhance the channel control. The second gate may include an extension in a third dimension through the semiconductor material. The extension may present an exposed surface for an electrical terminal for receiving a voltage.

The embodiment of the invention provides a semiconductor device structure and a preparation method thereof, and relates to the technical field of semiconductors. The semiconductor device structure comprises a substrate, a bottom doped region, a drift region, a first doped region, a second doped region and a plurality of mutually independent third doped regions, the third doped regions are located in the drift region and are connected with the first doped region, and the number, depth and doping concentration of the third doped regions in the longitudinal direction are flexibly adjusted. JFETs with different pinch-off voltages can be designed, and an original GSD structure does not need to be changed. And the multi-channel structure enables the current capability of the JFET to be improved. Compared with the prior art, the embodiment of the invention can realize different pinch-off voltages by adjusting the process structure under the condition of the original GSD structure, the pinch-off voltage diversity is better, and the electrical performance is better.

This disclosure provides a junction field-effect transistor (JFET) device, its fabrication method, and an electronic device. The p-type gate region is formed by implantation ions on the side of the n-drift layer away from the n+ substrate. Therefore, it eliminates the need for high-energy p-type ion deep implantation to achieve the p-type gate region, thereby improving production efficiency. The n-type channel layer can be formed using homoepitaxial growth, which improves device design flexibility and channel mobility. Therefore, compared to Figure 1, this disclosure avoids using deep p-type ion implantation to form the bottom p-type gate region and deep n-type ion implantation to form the n-type channel layer, thus improving device design flexibility, production efficiency, and channel mobility.

The present invention relates to a planar split-gate VDMOSFET and a manufacturing method therefor. The planar split-gate VDMOSFET comprises: a drain region; a drift region, which is located on the drain region; a drain electrode, which is located on the side of the drain region that faces away from the drift region; a JFET region, which is located on the drift region; a body region, which is located on the drift region and on both sides of the JFET region; a source region, which is located on the body region and on both sides of the JFET region; a contact region, which is of a second conductivity type and is located outside the body region, wherein the bottom of the contact region is deeper than the bottom of the body region; a split gate electrode, which is split from the middle, wherein a separation region is located directly above the JFET region; and a source electrode, which is located on the source region and the contact region and is in direct contact with the source region and the contact region. The present invention reduces the gate-drain capacitance, reduces the switch power consumption of a device, and improves the performance of the device at a high frequency. Without affecting the specific on-resistance, the breakdown voltage of the device is increased, and the long-term reliability of the device is improved.

The application provides a planar silicon carbide MOSFET device and a manufacturing method thereof, and the device structure comprises an N+ substrate, an N-drift region, a P-well region with a buried layer, an N+ source region, a P+ source region, a current spreading layer, P-type polysilicon, gate medium, insulating medium, N-type polysilicon, a gate, a source and a drain. On the basis of a traditional planar MOSFET, a P-type buried layer connected with the source potential and P-type polysilicon are introduced, a low third quadrant conduction voltage drop is realized through a silicon-silicon carbide heterojunction, and the saturation conduction current of the device is reduced and the short circuit resistance time is improved through the introduced JFET region. In addition, due to the fact that the device adopts split gate and contains a P-type buried layer, the area of the gate and the drain is reduced, the Cgd of the device is improved, and the switching speed of the device is improved.