335 results about "JFET" patented technology

According to the junction field effect transistor device, the preparation method thereof and the electronic equipment provided by the invention, the threshold voltage of the device can be controlled through the low-voltage JFET channel region (namely the first horizontal part) formed by the first P-type ion implantation. Meanwhile, the size of the vertical channel (namely the first vertical part) is determined through first P-type ion implantation, groove etching is carried out in an implantation region, the size of the etched vertical channel and the size of the P-type gate (namely the second P-type region) are decoupled, and the influence of vertical channel etching on threshold voltage and drain breakdown voltage is avoided. Moreover, the gate ohmic contact layer is formed in the trench region (namely above the second horizontal part) to be connected to the gate of the device, so that the gate-drain capacitance CGD of the device can be reduced, the input capacitance and gate charge of the device are reduced, the switching speed of the device can be improved, the switching loss of the device is reduced, and the switching performance of the device is improved. The method is very suitable for the common direct drive type application of the high-voltage normally-open JFET.

A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.

A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

The invention discloses a component bidirectional aging tool based on aging equipment and a testing method. The component bidirectional aging tool comprises an aging plate; station needles are arranged on the aging plate and used for aging different types of devices and installing aging sockets, golden fingers are arranged at the two ends of the aging plate, polarity conversion slots are formed in the positions close to the golden fingers, and the polarity conversion slots are connected with the golden fingers; an electrode connecting line is arranged on the aging plate, one end of the electrode connecting line is connected with an aging test device electrode, and the other end of the electrode connecting line is correspondingly connected with the polarity conversion slot; and a polarity conversion plate is arranged on the polarity conversion slot. By applying the technical scheme of the invention, the problems of device appearance damage and low production efficiency caused by manual reversing operation in the aging process of a non-polar capacitor and a bidirectional TVS (Transient Voltage Suppressor) in the prior art can be effectively solved, and the problem of high cost during aging of devices such as transistors with different polarities, JFETs (Junction Field Effect Transistor) and the like can be effectively solved, and an aging tool does not need to be manufactured again.

According to the device structure for improving the switching speed and robustness of the SiC MOS device and the manufacturing method, an arc-shaped gate oxide layer which is locally thickened is selectively additionally arranged above a JFET area of a device cell, the total input capacitance is reduced by reducing the gate-drain capacitance, the switching speed is improved, and power consumption is reduced; meanwhile, the thickened JFET region gate oxide layer improves the gate oxide reliability and the single particle resistance, and the channel region gate oxide layer is kept thin so as to maintain low Ron. The key preparation method comprises two gate oxidation and polycrystalline silicon deposition processes: local oxidation is carried out in a JFET region, an arc-shaped polycrystalline silicon gate is formed, a main gate structure is formed through second overall oxidation, and doping distribution is regulated and controlled in combination with self-aligned injection, hard mask step-by-step treatment and a high-temperature activation process. According to the invention, low Ron, high switching speed and high robustness are taken into account, the method is suitable for SiC and Si-based MOS devices, and the performance and reliability of the devices are significantly improved.

The invention discloses a channel mobility testing method, a channel mobility testing structure and a manufacturing method of the channel mobility testing structure. The channel mobility test method comprises the following steps: applying test voltage to source electrodes, drain electrodes and grid electrode structures of at least two different semiconductor devices, and determining resistance between the source electrode and the drain electrode of each semiconductor device; wherein the channel widths of at least part of the semiconductor devices in the at least two different semiconductor devices are different; the channel width is the width of the well region between the JFET region and the first region in the direction from the first region to the JFET region; measuring the resistance between the source electrode and the drain electrode of each semiconductor device; and determining the channel mobility of each semiconductor device according to the resistance between the source electrode and the drain electrode of each semiconductor device and the channel width of each semiconductor device. According to the embodiment of the invention, the measurement of the channel field effect mobility can be realized, the measurement mode is simple, and the measurement efficiency is high.

The invention relates to an audio decoding output stage circuit and audio equipment, the audio decoding output stage circuit comprises an I / V conversion module and a low-pass filtering module, and the I / V conversion module comprises a conversion circuit, a crossed diamond amplification circuit, an overcurrent protection circuit and a Roche network circuit; the conversion circuit comprises a JFET (Junction Field Effect Transistor) audio operational amplifier chip and an I / V (Input / Output) conversion resistor and is used for converting an input current into an analog voltage signal; the crossed diamond amplifying circuit can reduce the input offset voltage; the over-current protection circuit can carry out over-current protection; the rowbell network circuit can prevent high-frequency self-oscillation of the power output stage; and the low-pass filtering module comprises a filtering circuit and an ultrahigh frequency filtering circuit arranged at the output end of the audio decoding output stage circuit. The scheme can bring high-performance sound performance, and has the advantages of lower distortion, higher conversion rate, low output impedance and large pushing current.

A field-effect transistor with a buried gate, and a method of making the same. A volume of semiconductor material includes first and second ends and left and right sides. A source is located at the first end, a drain is provided, a left first gate structure is located at the left side, and a right first gate structure is located at the right side. A second, buried gate is located between and spaced apart from the source and the drain and the left and right first gate structures so as to be surrounded in first and second dimensions by the semiconductor material. The second gate divides a channel into multiple paths for current to flow between the source and the drain. The second gate includes a projection extending in a third dimension and presenting an exposed surface operable to receive a voltage.

A common-source cascode switching system and its operation method, as well as a half-bridge circuit, are disclosed. The common-source cascode switching system includes a JFET and a MOSFET coupled in series between the drain and source terminals, and a driving circuit. The driving circuit includes: a JFET driver that receives an input signal and outputs a JFET drive signal to a capacitor coupled in series with the gate of the JFET; a switch coupled between the gate and source terminals of the JFET and configured to respond to the input signal; and a comparator for comparing the JFET gate voltage with a threshold. The driving circuit also includes a MOSFET driver circuit to drive the MOSFET in a MOSFET on state during an input signal on state, and to drive the MOSFET in either a MOSFET off state or a MOSFET on state during an input signal off state in response to a comparison signal from the comparator.

A kind of anti-radiation reinforced SiC super-junction JFET structure and preparation method, from bottom to top are in order: drain metallization layer, N+ substrate layer, N buffer layer, P column region, N column region, P-base region, current expansion region, N+ source region, P+ gate region, isolation dielectric layer, gate metallization layer, source metallization layer.P column region and N column region are arranged alternately on the upper surface of N buffer layer, P column region is symmetrically arranged, and N column region is arranged between two P column regions.P column region and P-base region form a P-type doped region as a whole, and are connected with source metallization layer.Electrically conductive channel structure is formed between P+ gate region and P-base region, and the opening and closing of channel are realized by controlling the voltage on P+ gate region.The application effectively solves the problem of electric field concentration caused by high-energy charged particle bombardment in the device, reduces local high temperature, and greatly improves the anti-single-particle radiation capability of SiC JFET.

The invention firstly comprises a junction field effect transistor (JFET), namely a SiC JFET, which is completely made of SiC. The transistor is preferably manufactured by adopting a top-down method, and the manufacturing process is suitable for large-scale production. The electrical properties of the proposed SiC JFET have been evaluated under dry conditions and in a liquid medium. The concept feasibility of the SiC JFET as a biosensor 0 is verified through pH value measurement. The sensitivity of the SiC JFET provided by the invention is up to 495 mV / ph, that is, the sensitivity is nearly 100 times higher than the theoretical Nernst limit. Therefore, the device is suitable for various in-vitro and in-vivo biochemical detection applications because the device meets performance indexes generally required in the field, such as sensitivity and chemical stability, especially long-term stability.

This invention belongs to the field of power semiconductor technology, specifically relating to a silicon carbide power MOSFET and its fabrication method. The silicon carbide power MOSFET provided by this invention includes a substrate, a first epitaxial layer, a first CSL layer, a first P-body region, a second epitaxial layer, a second CSL layer, and a second P-body region. A trench region is provided between the two P-body regions, with P+ regions injected at the bottom of the trench and N+ regions distributed on the sidewalls. Specifically, the on-resistance is reduced by the double CSL layer and P-body structure, while the JFET region length is extended to limit short-circuit current, significantly improving short-circuit withstand time. This makes it suitable for high-power, high-reliability power electronic devices.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

A method of manufacturing a silicon carbide power device includes performing a first ion implantation process to form a JFET region in an epitaxial layer over a substrate. A patterned mask layer is formed on the epitaxial layer above the JFET region. A second ion implantation process is performed to form well regions at both sides of the JFET region. A first spacer is formed on sidewalls of the patterned mask layer. A third ion implantation process is performed to form a self-aligned heavily doped region in the well regions. A second spacer is formed on a side of the first spacer to shield a portion of the heavily doped region. A fourth ion implantation process is performed to form another self-aligned heavily doped region in the heavily doped region. A gate structure is formed after removing the patterned mask layer, the first spacer, and the second spacer.

The application relates to the technical field of semiconductors, in particular to a planar SiC MOSFET device structure and a manufacturing method thereof. The device structure comprises a substrate, an epitaxial layer located on the substrate, a doped region and a JFET region located on the epitaxial layer, wherein the substrate is a silicon carbide (SiC) substrate, and the epitaxial layer is a SiC epitaxial layer; the JFET region is located between the doped regions and is in contact with the doped regions; the upper surface of the JFET region, the upper surface of the doped region and the upper surface of the epitaxial layer are located on the same set surface, and the set surface is a concave surface; the concave part of the concave surface covers the specified region of the JFET region and the doped region, and the specified region is a region containing at least a channel of the doped region. Through the device structure, the on-resistance of the device is effectively reduced under the premise of guaranteeing the performance of the device except the on-resistance.

This disclosure relates to bidirectional current limiting circuits for use in aircraft electric power distribution systems. Example embodiments include a bidirectional current limiting circuit (500a-c) comprising first and second JFETs (501, 502) connected between first and second terminals (503, 504), wherein: the first terminal (503) is connected to a drain of the first JFET (501) and to a gate of the second JFET (502) via a first biasing element (505, 701); he second terminal (504) is connected to a drain of the second JFET (502) and to a gate of the first JFET (501) via a second biasing element (506, 702); and a source of the first JFET (501) is connected to a source of the second JFET (502).

In a longitudinal channel fin structure channel MOSFET, the on-resistance is reduced while ensuring short circuit tolerance. A longitudinal channel fin structure channel MOSFET having a plurality of first channels (2) having a length direction in a first direction and arranged in a plurality in a second direction, has a first JFET region (8A) of a first conductivity type arranged below a channel region (5), sandwiched by a first body region (9A) of a second conductivity type, and a second JFET region (8B) of the first conductivity type arranged in contact with a lower surface of the first JFET region (8A), sandwiched by a second body region (9B) of the second conductivity type, the length in the first direction of the second JFET region (8B) being longer than the first JFET region (8A), the impurity concentration of the first JFET region (8A) being higher than the second JFET region (8B), the impurity concentration of the second JFET region (8B) being higher than a drift region (10), and the dimensions in the depth direction of the first body region (9A) and the first JFET region (8A) from the lower portion of the first channel (2) are both greater than 0.5 μm.

A field-effect transistor with a shielded source, and a method of making the same. A volume of semiconductor material includes first and second vertically spaced ends and first and second laterally spaced sides. First and second laterally spaced gates are provided in the volume of semiconductor material. A source is located at the first end between the first and second gates, a drain is provided, and a channel extends therebetween. The first gate includes a lower first gate portion spaced below and extending beneath the source so as to create a turn in the channel around the lower first gate portion.

The embodiment of the invention provides a metal oxide semiconductor cellular structure, a power chip and a preparation method of the metal oxide semiconductor cellular structure. Comprising a first conductive type substrate, a first conductive type epitaxial layer located on the substrate, a second conductive type active region formed in the epitaxial layer, and a first conductive type source layer formed in the active region; the cellular structure further comprises a second conduction type ohmic contact layer, and the second conduction type ohmic contact layer is at least partially located in the second conduction type active region. Wherein a junction field effect transistor (JFET) region of the cellular structure comprises a region provided with a second conduction type ohmic contact layer and other regions located in the junction field effect transistor (JFET) region, and the other regions are constructed as channel regions; the second conductivity type ohmic contact layer is connected to a junction field effect transistor (JFET) region. According to the invention, the transverse size of the unit cell is reduced so as to reduce the forward on-resistance, and the output performance of the device is improved.

The invention relates to the technical field of semiconductor devices, in particular to a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: providing a substrate with an epitaxial layer; sequentially forming a JFET layer and a first type doping layer on the epitaxial layer, wherein a cellular region and a bus region are defined on the surface of the first type doping layer; a second type doped column is formed by extending from the surface of the first type doped layer, the second type doped column penetrates through the first type doped layer and the JFET layer, and the bottom of the second type doped column is located in the epitaxial layer; a groove is formed in the second type doping column through etching, a second type doping area is reserved between the inner wall of the groove and the outer wall of the second type doping column, and the groove comprises a cellular groove formed in the cellular area and a bus groove formed in the bus area. The method has the advantages that the technological process is simple, and the uniform second-type doped region can be formed without accurately controlling the injection angle like a traditional method.

The invention discloses a vertical JFET (Junction Field Effect Transistor) power device for enhancing gate end driving capability by ohmic contact and a manufacturing method thereof, and belongs to the technical field of semiconductor power devices. In order to solve the problem of poor switching performance caused by high electrical resistivity of a grid active region and serious attenuation of a driving signal in the existing vertical JFET, the invention provides a metal ohmic contact layer (such as nickel) formed on the surface of the grid active region. And the low-resistance metal layer is connected in parallel with the grid electrode P region, and an efficient current path from the grid electrode contact end to each grid junction in the chip is constructed, so that the grid electrode resistance is greatly reduced, and the grid end driving capability is enhanced. According to the manufacturing method, an ohmic contact preparation step in the prior art is utilized, introduction of non-compatible materials such as polycrystalline silicon and complex procedures is not needed, and gate source short circuit is reliably prevented through the design of selectively reserving an insulating layer above a gate region. According to the invention, the switching speed and reliability of the device are improved, and excellent process compatibility and cost advantages are maintained.

The invention discloses a circuit for simplifying electroencephalogram signal detection, amplification and transmission, and relates to the technical field of electroencephalogram signal acquisition. Comprising a distributed JFET signal amplification module, a differential amplification and common-mode recovery module and a differential-to-single-ended module. The distributed JFET signal amplification module directly amplifies weak electroencephalogram signals at an electroencephalogram signal acquisition point, and noise is reduced and measurement errors caused by Vos are eliminated through cooperation of a JFET tube and an operational amplifier in combination with a reference current source and a zero setting circuit; the differential amplification and common-mode recovery module further amplifies the amplified differential signal and recovers a common-mode signal, so that the influence of the input current on a pre-stage circuit is reduced; the differential-to-single-ended module converts the differential signal into a single-ended signal and couples the single-ended signal to a specified common-mode voltage, so that ADC acquisition is facilitated. Interference in the electroencephalogram signal transmission process is effectively reduced, the authenticity and accuracy of signal collection are improved, complex digital bus control is not needed, the number of connecting lines is reduced, and connection between point locations is simplified.

A vertical junction field effect (JFET) semiconductor device according to some embodiments includes a drift layer, a channel layer on the drift layer, and a plurality of alternating trenches and mesas in the channel layer, wherein a first plurality of the trenches includes gate contact regions. A source metallization is on the mesas. The device includes a second different than the first plurality of trenches, wherein the source metallization is electrically connected to the drift layer at a bottom of the second trench.

A power metal oxide semiconductor field-effect transistor is radiation-hardened against a single-event gate rupture effect, and a method of making such a transistor is disclosed. A volume of semiconductor material includes first and second sides and a centrally located junction field effect transistor neck region. The metal oxide semiconductor field-effect transistor includes a source, a well located between the source and the JFET neck region, and a dielectric material. The well includes a first well portion and a second well portion. The second well portion is located between the first well portion and the JFET neck region and has a lower dopant concentration than the first well portion. The dielectric material overlies the first well portion, at least part of the second well portion, and at least part of the source. The dielectric material presents a thicker dielectric portion located over the second well portion.

This application belongs to the field of power device technology and provides a silicon carbide power device with improved BV and Ron, as well as its fabrication method and chip. By setting a first P-type well region in the top epitaxial region, a heavily doped P-type region is formed on the first P-type well region, and adjacent second P-type well regions are isolated by the top epitaxial region. At least the second P-type well regions are symmetrically arranged with heavily doped P-type regions, and the depth of the second P-type well region is less than the depth of the first P-type well region. This allows the JFET region inside the device to have a higher doping concentration of donor doping. While ensuring the ideal BVDSS of the device, the on-resistance can be effectively reduced and the current density of the device can be increased.

The invention discloses a method and a structure for integrating a double-gate JFET (junction field effect transistor) device in a bipolar junction transistor process, and the method comprises the steps: providing a substrate, and forming a buried layer structure, an epitaxial layer and an isolation structure of the bipolar junction transistor and the JFET device on the substrate; carrying out penetration doping and well region doping in the epitaxial layer; forming a collector crystalline region, a base crystalline region, a bottom gate crystalline region, a top gate crystalline region, a source crystalline layer and a drain crystalline region above the epitaxial layer; depositing a dielectric layer on the epitaxial layer, etching to form a base region window, and forming a heavily doped collector region, a heavily doped outer base region, a heavily doped bottom gate, a heavily doped top gate, a source region and a drain region through the base region window; s500, forming an emitter region window, and forming an emitter crystalline region in the emitter region window; and forming electrodes of the bipolar junction transistor and the JFET device on the dielectric layer. According to the invention, the high-speed bipolar junction transistor and the JFET device can be integrated in a single manufacturing process under the condition that a large amount of process complexity is not increased.

The present application relates to the field of geophysical exploration equipment, and relates to a multi-discrete current source low-noise JFET differential parallel amplifier, which comprises a JFET primary amplifier circuit and an IOA secondary amplifier circuit; the JFET primary amplifier circuit comprises a common-source amplifier circuit composed of two groups of JFET pairs in parallel, the drain of each group of JFET pairs is connected to the positive pole of a lithium battery, the source of the JFET pair is connected to the negative pole of the lithium battery through an NPN-type BJT, the gate of the JFET pair is connected to the output signal of one side of a differential coil, and the drain of the JFET pair serves as an output; the IOA secondary amplifier circuit adopts a subtractor structure and is connected to the two outputs of the JFET primary amplifier circuit through two input ends. Discrete current sources are used to supply power to two pairs of parallel JFETs, the parameter difference between JFET pairs is reduced, parallel method is used to reduce the background noise of JFET devices, and the advantages of low-noise amplification of JFET devices are exerted.

The application discloses a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle. The manufacturing method comprises the following steps: providing a semiconductor body; comprising a first surface; forming a barrier portion on the side of the first surface away from the semiconductor body; performing a preset number of operations of forming a side wall structure and a JFET region on the semiconductor body; wherein the side wall structure is located on both sides of the barrier portion; the JFET region is of a first conductivity type; removing the barrier portion and forming a central JFET region in the semiconductor body; wherein the central JFET region is coincident with the orthogonal projection of the barrier portion on the first surface; the ion concentration of the central JFET region is less than that of the JFET region; forming an insulating layer on the first surface; forming a gate electrode on the side of the insulating layer away from the first surface. The embodiment of the application can improve the voltage resistance of the gate oxide layer and reduce the resistance of the JFET region.

The invention belongs to the technical field of power semiconductors, and particularly relates to a silicon carbide power MOSFET and a manufacturing method thereof. The silicon carbide power MOSFET provided by the invention comprises a substrate, a first epitaxial layer, a first CSL layer, a first P body region, a second epitaxial layer, a second CSL layer and a second P body region, a groove region is arranged between the two P body regions, a P + region is injected into the bottom of the groove, and an N + region is distributed on the side wall of the groove; specifically, the on-resistance is reduced through the double-layer CSL layer and the P body structure, the length of the JFET region is prolonged to limit the short-circuit current, the short-circuit tolerance time is remarkably prolonged, and the structure is suitable for the field of high-power and high-reliability power electronic devices.