435 results about "JFET" patented technology

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The invention relates to a SiC groove type JFET device structure and a preparation method thereof. The SiC groove type JFET device structure comprises a drain metallization layer, a SiC N + substrate layer, a first N type drift region, a source groove structure, a second N type drift region, a P-well region, an N + source region, a P + gate region, an isolation dielectric layer, a gate metallization layer and a source metallization layer. The source trench structure is arranged in the first N-type drift region, the upper surface of the source trench structure is in contact with the P-well region and the source metallization layer, and an oxide layer and a polycrystalline silicon layer are sequentially filled in a trench, so that the upper surface of the trench structure is flush with the upper surface of the first N-type drift region. By introducing the trench structure connected with the source electrode in the drift region, the transverse electric field distribution condition in the device can be optimized, the peak electric field is reduced, the conduction capability of the device is further improved under the condition of ensuring that the original breakdown voltage is not changed, the performance of the SiC JFET is greatly improved, and the conduction loss during working is reduced.

The utility model provides a semiconductor device. The semiconductor device comprises a semiconductor substrate of a first conductive type; the deep well of the second conduction type is located in the semiconductor substrate; the shallow well of the first conductive type is located in the semiconductor substrate on the outer side of the deep well of the second conductive type; the JFET source electrode region, the drain electrode region and the LDMOS source electrode region are arranged at intervals; a field oxide layer, a JFET polysilicon gate and an LDMOS polysilicon gate, the field oxide layer is located in the deep trap of the second conduction type, and the JFET polysilicon gate and the LDMOS polysilicon gate are located on the field oxide layer; and the high-voltage well of the first conduction type comprises a first part and a second part, the first part is located in the deep well of the second conduction type between the JFET source region and the drain region, the second part is located in the deep well of the second conduction type between the drain region and the LDMOS polysilicon gate, and the second part is distributed in a polygonal matrix. The semiconductor device provided by the utility model can meet the performance requirements of the LDMOS and the JFET at the same time.

A Schottky barrier integrated field effect transistor and a manufacturing method therefor. The field effect transistor comprises: a first conductive type substrate (1); a first conductive type epitaxial layer (2), wherein the first conductive type epitaxial layer (2) comprises second conductive type doped regions (21), and a JFET region (23) is formed between adjacent second conductive type doped regions (21); gate-source isolation structures (3), wherein an accommodating region (4) is formed between adjacent gate-source isolation structures (3); a Schottky barrier layer (5), wherein the Schottky barrier layer (5) is located in the accommodating region (4) and in contact with the JFET region (23); and gates (6), separated from the Schottky barrier layer (5) by means of at least the gate-source isolation structures (3), wherein the thickness of the sides of the gate-source isolation structures (3) close to the Schottky barrier layer (5) is greater than the thickness of the sides of the gate-source isolation structures (3) distant from the Schottky barrier layer (5).

According to the junction field effect transistor device, the preparation method thereof and the electronic equipment provided by the invention, the threshold voltage of the device can be controlled through the low-voltage JFET channel region (namely the first horizontal part) formed by the first P-type ion implantation. Meanwhile, the size of the vertical channel (namely the first vertical part) is determined through first P-type ion implantation, groove etching is carried out in an implantation region, the size of the etched vertical channel and the size of the P-type gate (namely the second P-type region) are decoupled, and the influence of vertical channel etching on threshold voltage and drain breakdown voltage is avoided. Moreover, the gate ohmic contact layer is formed in the trench region (namely above the second horizontal part) to be connected to the gate of the device, so that the gate-drain capacitance CGD of the device can be reduced, the input capacitance and gate charge of the device are reduced, the switching speed of the device can be improved, the switching loss of the device is reduced, and the switching performance of the device is improved. The method is very suitable for the common direct drive type application of the high-voltage normally-open JFET.

The SiC JFET structure comprises a drain electrode metallization layer, an N + substrate layer, an N-drift region, a P first gate region, an N current expansion region, a P second gate region, an N + source region, a gate electrode metallization layer, an insulating dielectric layer, a source electrode ohmic contact layer, a source electrode Schottky contact layer and a source electrode metallization layer. The P first gate regions are embedded in the upper surface of the N-drift region, the gap between the two P first gate regions forms a vertical conductive channel structure, and the source Schottky contact layer is located right above a channel to form a Schottky diode structure, so that the conduction loss during follow current of the device can be effectively reduced; meanwhile, the gate metallization layer is located at the bottom of the gate trench and directly connected with the P first gate region, the gate metallization layer is isolated from the source metallization layer through the insulating dielectric layer in the gate trench, and the device has the advantages of being small in reverse blocking leakage current, high in reliability and the like.

The invention discloses a direct-current solid-state circuit breaker with a voltage limiting protection circuit and a control method thereof. The direct-current solid-state circuit breaker comprises a solid-state switch module, the solid-state switch module comprises a first sub-module and a second sub-module which are the same, and each of the first sub-module and the second sub-module comprises a SiC JFET device J, capacitors C, Cgd and Cgs, a comparator U, an MOSFET device Q, a resistor Rg and resistors ra and rb; the first end of Rg is used for receiving a driving signal, and the second end of Rg is connected to the grid electrode of J after being connected with the first end of C, the second end of Cgd and the first end of Cgs; the second end of ra and the first end of rb are connected as a comparison voltage sampling point; the first end of ra is connected to the first end of Cgd and the drain electrode of J; the second end of the rb is connected to the second end of the Cgs, the source electrode of the Q and the source electrode of the J; the second end of C is connected to the drain electrode of Q; the output end of U is connected to the grid electrode of Q; the anode input of U is comparison voltage, and the cathode input is reference voltage; the source electrode of the first sub-module J is connected to the drain electrode of the second sub-module J.

The utility model discloses a TBU circuit, which comprises an N-channel depletion type MOSFET or an N-channel JFET, a P-channel depletion type MOSFET and a current limiting element, the source electrode of the N-channel depletion type MOSFET or the N-channel JFET is connected with the source electrode of the P-channel depletion type MOSFET, one end of the current limiting element is connected with the grid electrode of the N-channel depletion type MOSFET or the N-channel JFET, and the other end of the current limiting element is connected with the drain electrode of the P-channel depletion type MOSFET; a first voltage stabilizing branch is connected in parallel between the grid electrode and the source electrode of the N-channel depletion type MOSFET or the N-channel JFET, and a second voltage stabilizing branch is connected in parallel between the source electrode and the grid electrode of the P-channel depletion type MOSFET. According to the utility model, the voltage proportion of the N-channel depletion type MOSFET or the N-channel JFET and the P-channel depletion type MOSFET can be adjusted, and the withstand voltage value of the N-channel depletion type MOSFET or the N-channel JFET and the P-channel depletion type MOSFET can be designed flexibly.

According to the field effect transistor, a first JFET is formed in a first epitaxial layer, and a second MOSFET is formed in a second epitaxial layer. The forbidden band width of the material of the first epitaxial layer is greater than that of the material of the second epitaxial layer; the second epitaxial layer is formed on the top surface of the first epitaxial layer, and the contact surface of the first epitaxial layer and the second epitaxial layer is heterojunction; a first source region of the first JFET and a second drain region of the second MOSFET are connected through a first floating metal contact hole penetrating through the heterojunction. A first gate region of the first JFET is connected to a source consisting of a front metal layer through a deep contact hole penetrating through the heterojunction; the second source region is connected with the source electrode. The back face of the first drain region is connected to a drain electrode composed of a back face metal layer. The invention further discloses a manufacturing method of the field effect transistor. The invention has the advantages of a wide bandgap semiconductor material device, and can overcome the problems of high channel carrier mobility, high driving voltage and poor reliability of the gate dielectric layer of the wide bandgap semiconductor material device.

A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.

A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

The invention provides a JFET (Junction Field Effect Transistor) device and a preparation method thereof. The JFET device comprises a substrate layer; the drift layer is positioned on one side of the substrate layer along the first direction; the first doped regions are spaced along the second direction, the conduction type of the first doped regions is opposite to that of the drift layer, and the first doped regions and the surface of one side, facing the substrate layer, of the drift layer are spaced along the first direction; the gate doped region is positioned on one side, deviating from the substrate layer, of the first doped region along the first direction; the source regions are located between the adjacent first doped regions; the pinch-off regions are positioned between the adjacent first doped regions and between the substrate layer and the source region; wherein the size of the first doped region in the first direction is 0.8-4 microns; wherein the second direction intersects with the first direction.

The invention discloses a component bidirectional aging tool based on aging equipment and a testing method. The component bidirectional aging tool comprises an aging plate; station needles are arranged on the aging plate and used for aging different types of devices and installing aging sockets, golden fingers are arranged at the two ends of the aging plate, polarity conversion slots are formed in the positions close to the golden fingers, and the polarity conversion slots are connected with the golden fingers; an electrode connecting line is arranged on the aging plate, one end of the electrode connecting line is connected with an aging test device electrode, and the other end of the electrode connecting line is correspondingly connected with the polarity conversion slot; and a polarity conversion plate is arranged on the polarity conversion slot. By applying the technical scheme of the invention, the problems of device appearance damage and low production efficiency caused by manual reversing operation in the aging process of a non-polar capacitor and a bidirectional TVS (Transient Voltage Suppressor) in the prior art can be effectively solved, and the problem of high cost during aging of devices such as transistors with different polarities, JFETs (Junction Field Effect Transistor) and the like can be effectively solved, and an aging tool does not need to be manufactured again.

The present application discloses a SiC MOSFET cell structure and a manufacturing method therefor. The cell structure comprises: a source electrode metal region (source), a source electrode OHM region, a source electrode ohmic contact region N+, a channel N-type doped region NC, a channel P-type doped region PC, a vertical conductive channel JFET region, a Pwell region, a drift layer N-, a substrate N+, a drain electrode OHM region, a gate electrode region (gate), and a gate-source isolation medium SiO2.

A semiconductor device includes a substrate and a drift layer on the substrate, the drift layer having a first conductivity type. The device includes a first plurality of vertical junction field effect (JFET) subcells and a second plurality of vertical JFET subcells on the drift layer. The first plurality of vertical JFET subcells are connected in parallel to form a first JFET device, and the second plurality of vertical JFET subcells are connected in parallel to form a second JFET device. The second JFET device is connected in anti-series with the first JFET device through the drift layer. The device further includes a first gate electrode and a first current terminal in contact with the first plurality of vertical JFET subcells, and a second gate electrode and a second current terminal in contact with the second plurality of vertical JFET subcells.

According to the device structure for improving the switching speed and robustness of the SiC MOS device and the manufacturing method, an arc-shaped gate oxide layer which is locally thickened is selectively additionally arranged above a JFET area of a device cell, the total input capacitance is reduced by reducing the gate-drain capacitance, the switching speed is improved, and power consumption is reduced; meanwhile, the thickened JFET region gate oxide layer improves the gate oxide reliability and the single particle resistance, and the channel region gate oxide layer is kept thin so as to maintain low Ron. The key preparation method comprises two gate oxidation and polycrystalline silicon deposition processes: local oxidation is carried out in a JFET region, an arc-shaped polycrystalline silicon gate is formed, a main gate structure is formed through second overall oxidation, and doping distribution is regulated and controlled in combination with self-aligned injection, hard mask step-by-step treatment and a high-temperature activation process. According to the invention, low Ron, high switching speed and high robustness are taken into account, the method is suitable for SiC and Si-based MOS devices, and the performance and reliability of the devices are significantly improved.

The invention discloses a channel mobility testing method, a channel mobility testing structure and a manufacturing method of the channel mobility testing structure. The channel mobility test method comprises the following steps: applying test voltage to source electrodes, drain electrodes and grid electrode structures of at least two different semiconductor devices, and determining resistance between the source electrode and the drain electrode of each semiconductor device; wherein the channel widths of at least part of the semiconductor devices in the at least two different semiconductor devices are different; the channel width is the width of the well region between the JFET region and the first region in the direction from the first region to the JFET region; measuring the resistance between the source electrode and the drain electrode of each semiconductor device; and determining the channel mobility of each semiconductor device according to the resistance between the source electrode and the drain electrode of each semiconductor device and the channel width of each semiconductor device. According to the embodiment of the invention, the measurement of the channel field effect mobility can be realized, the measurement mode is simple, and the measurement efficiency is high.

An improved silicon carbide (SiC) planar MOSFET having at least one buried P-shield (BPS) region including one center portion and two side portions for the gate oxide electric field and saturation current reductions is disclosed. Two saturation current pitching (SCP) structures formed in two Junction Field Effect Transistor (JFET) regions sandwiched between the side portions and the center portion of the BPS region limit a saturation current of the device in a forward conduction stage for the short-circuit capability improvement. Moreover, a Junction barrier Schottky diode (JBSD) is integrated with the SiC MOSFET in a location between the two adjacent split gate electrodes for the reverse conduction switching loss reduction.

The invention relates to an audio decoding output stage circuit and audio equipment, the audio decoding output stage circuit comprises an I / V conversion module and a low-pass filtering module, and the I / V conversion module comprises a conversion circuit, a crossed diamond amplification circuit, an overcurrent protection circuit and a Roche network circuit; the conversion circuit comprises a JFET (Junction Field Effect Transistor) audio operational amplifier chip and an I / V (Input / Output) conversion resistor and is used for converting an input current into an analog voltage signal; the crossed diamond amplifying circuit can reduce the input offset voltage; the over-current protection circuit can carry out over-current protection; the rowbell network circuit can prevent high-frequency self-oscillation of the power output stage; and the low-pass filtering module comprises a filtering circuit and an ultrahigh frequency filtering circuit arranged at the output end of the audio decoding output stage circuit. The scheme can bring high-performance sound performance, and has the advantages of lower distortion, higher conversion rate, low output impedance and large pushing current.

A field-effect transistor with a buried gate, and a method of making the same. A volume of semiconductor material includes first and second ends and left and right sides. A source is located at the first end, a drain is provided, a left first gate structure is located at the left side, and a right first gate structure is located at the right side. A second, buried gate is located between and spaced apart from the source and the drain and the left and right first gate structures so as to be surrounded in first and second dimensions by the semiconductor material. The second gate divides a channel into multiple paths for current to flow between the source and the drain. The second gate includes a projection extending in a third dimension and presenting an exposed surface operable to receive a voltage.

A common-source cascode switching system and its operation method, as well as a half-bridge circuit, are disclosed. The common-source cascode switching system includes a JFET and a MOSFET coupled in series between the drain and source terminals, and a driving circuit. The driving circuit includes: a JFET driver that receives an input signal and outputs a JFET drive signal to a capacitor coupled in series with the gate of the JFET; a switch coupled between the gate and source terminals of the JFET and configured to respond to the input signal; and a comparator for comparing the JFET gate voltage with a threshold. The driving circuit also includes a MOSFET driver circuit to drive the MOSFET in a MOSFET on state during an input signal on state, and to drive the MOSFET in either a MOSFET off state or a MOSFET on state during an input signal off state in response to a comparison signal from the comparator.

A kind of anti-radiation reinforced SiC super-junction JFET structure and preparation method, from bottom to top are in order: drain metallization layer, N+ substrate layer, N buffer layer, P column region, N column region, P-base region, current expansion region, N+ source region, P+ gate region, isolation dielectric layer, gate metallization layer, source metallization layer.P column region and N column region are arranged alternately on the upper surface of N buffer layer, P column region is symmetrically arranged, and N column region is arranged between two P column regions.P column region and P-base region form a P-type doped region as a whole, and are connected with source metallization layer.Electrically conductive channel structure is formed between P+ gate region and P-base region, and the opening and closing of channel are realized by controlling the voltage on P+ gate region.The application effectively solves the problem of electric field concentration caused by high-energy charged particle bombardment in the device, reduces local high temperature, and greatly improves the anti-single-particle radiation capability of SiC JFET.

The invention firstly comprises a junction field effect transistor (JFET), namely a SiC JFET, which is completely made of SiC. The transistor is preferably manufactured by adopting a top-down method, and the manufacturing process is suitable for large-scale production. The electrical properties of the proposed SiC JFET have been evaluated under dry conditions and in a liquid medium. The concept feasibility of the SiC JFET as a biosensor 0 is verified through pH value measurement. The sensitivity of the SiC JFET provided by the invention is up to 495 mV / ph, that is, the sensitivity is nearly 100 times higher than the theoretical Nernst limit. Therefore, the device is suitable for various in-vitro and in-vivo biochemical detection applications because the device meets performance indexes generally required in the field, such as sensitivity and chemical stability, especially long-term stability.

This invention belongs to the field of power semiconductor technology, specifically relating to a silicon carbide power MOSFET and its fabrication method. The silicon carbide power MOSFET provided by this invention includes a substrate, a first epitaxial layer, a first CSL layer, a first P-body region, a second epitaxial layer, a second CSL layer, and a second P-body region. A trench region is provided between the two P-body regions, with P+ regions injected at the bottom of the trench and N+ regions distributed on the sidewalls. Specifically, the on-resistance is reduced by the double CSL layer and P-body structure, while the JFET region length is extended to limit short-circuit current, significantly improving short-circuit withstand time. This makes it suitable for high-power, high-reliability power electronic devices.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

A method of manufacturing a silicon carbide power device includes performing a first ion implantation process to form a JFET region in an epitaxial layer over a substrate. A patterned mask layer is formed on the epitaxial layer above the JFET region. A second ion implantation process is performed to form well regions at both sides of the JFET region. A first spacer is formed on sidewalls of the patterned mask layer. A third ion implantation process is performed to form a self-aligned heavily doped region in the well regions. A second spacer is formed on a side of the first spacer to shield a portion of the heavily doped region. A fourth ion implantation process is performed to form another self-aligned heavily doped region in the heavily doped region. A gate structure is formed after removing the patterned mask layer, the first spacer, and the second spacer.

The invention discloses a high-performance and low-on-resistance octagonal cellular array structure and a preparation method thereof. The octagonal cellular array structure comprises a substrate, a cellular array structure, an ohmic contact layer and a gate structure, wherein the cellular array structure, the ohmic contact layer and the gate structure are stacked on the substrate. The cellular array structure comprises a plurality of cellular structures which are periodically arranged; the cellular structure comprises four sub-cellular structures which are symmetrically distributed; the sub-cellular structure comprises a first sub-cellular structure and a second sub-cellular structure; the first sub-cellular structure comprises a first epitaxial layer, a JFET region, a first P well region and a first N + source region; the second sub-cellular structure comprises a second epitaxial layer, a second P well region, a P + source region and a second N + source region; the ohmic contact layer is superposed on one side, far away from the JFET region, of the upper surface of the cellular array structure; and the gate structure is superposed on one side, close to the JFET region, of the upper surface of the cellular array structure. Through the structural design, the cellular structure area is reduced, the characteristic on-resistance is reduced, and the high-frequency performance of the device is improved.

The application relates to the technical field of semiconductors, in particular to a planar SiC MOSFET device structure and a manufacturing method thereof. The device structure comprises a substrate, an epitaxial layer located on the substrate, a doped region and a JFET region located on the epitaxial layer, wherein the substrate is a silicon carbide (SiC) substrate, and the epitaxial layer is a SiC epitaxial layer; the JFET region is located between the doped regions and is in contact with the doped regions; the upper surface of the JFET region, the upper surface of the doped region and the upper surface of the epitaxial layer are located on the same set surface, and the set surface is a concave surface; the concave part of the concave surface covers the specified region of the JFET region and the doped region, and the specified region is a region containing at least a channel of the doped region. Through the device structure, the on-resistance of the device is effectively reduced under the premise of guaranteeing the performance of the device except the on-resistance.

This disclosure relates to bidirectional current limiting circuits for use in aircraft electric power distribution systems. Example embodiments include a bidirectional current limiting circuit (500a-c) comprising first and second JFETs (501, 502) connected between first and second terminals (503, 504), wherein: the first terminal (503) is connected to a drain of the first JFET (501) and to a gate of the second JFET (502) via a first biasing element (505, 701); he second terminal (504) is connected to a drain of the second JFET (502) and to a gate of the first JFET (501) via a second biasing element (506, 702); and a source of the first JFET (501) is connected to a source of the second JFET (502).