525 results about "JFET" patented technology

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device and particularly to MOSFET transistors. A semiconductor device including a first-conductivity-type substrate, a first-conductivity-type epitaxy layer including a JFET region, two first well regions including two source regions, two second well regions, a scatter oxide layer, the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, the two first well regions are adjacent to the first-conductivity-type epitaxy layer and each of the two first well regions is adjacent to one second well region, the JFET region is adjacent to the two second well regions, the scatter oxide layer is adjacent to the two source regions, the two first well regions, the two second well region and the JFET region, and a width of the JFET region is greater near the scatter oxide layer than in part closest to the first-conductivity-type substrate.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region; and the trench pseudo gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. According to the invention, the grid electrode and the grid electrode groove are arranged on the side surface of the doped column, and a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, and the grid electrode groove is arranged towards the interior of the doped column, so that the cell size and the pitch between two source electrode contact holes can be reduced to the greatest extent, and the performance of the MESA is improved. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The invention relates to a SiC groove type JFET device structure and a preparation method thereof. The SiC groove type JFET device structure comprises a drain metallization layer, a SiC N + substrate layer, a first N type drift region, a source groove structure, a second N type drift region, a P-well region, an N + source region, a P + gate region, an isolation dielectric layer, a gate metallization layer and a source metallization layer. The source trench structure is arranged in the first N-type drift region, the upper surface of the source trench structure is in contact with the P-well region and the source metallization layer, and an oxide layer and a polycrystalline silicon layer are sequentially filled in a trench, so that the upper surface of the trench structure is flush with the upper surface of the first N-type drift region. By introducing the trench structure connected with the source electrode in the drift region, the transverse electric field distribution condition in the device can be optimized, the peak electric field is reduced, the conduction capability of the device is further improved under the condition of ensuring that the original breakdown voltage is not changed, the performance of the SiC JFET is greatly improved, and the conduction loss during working is reduced.

A semiconductor device includes a semiconductor layer structure comprising a junction field-effect transistor (JFET) region of a first conductivity type, a well region of a second conductivity type on the JFET region, a source region of the first conductivity type on the well region and a plurality of support shields of the second conductivity type. The support shields are spaced apart from one another in a first direction parallel to an upper surface of the semiconductor layer structure and extend through the source region, the well region and the JFET region. The semiconductor device further includes a trenched gate structure formed in the semiconductor layer structure between a pair of adjacent support shields. Edges of at least two of the JFET region, the well region and the source region are aligned in a second direction perpendicular to the first direction.

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) cellular structure for improving high-frequency performance, the silicon carbide MOSFET cellular structure comprises four square silicon carbide MOSFET cells, the four square silicon carbide MOSFET cells are arranged in order to form a square, and channels with equal distance are arranged between every two square silicon carbide MOSFET cells; the center of the square is provided with a cross-shaped JFET region; a cross-shaped JFET region is arranged on the four square silicon carbide MOSFET cells, a P + region is arranged on the cross-shaped JFET region, the P + region covers channel regions at the corners of the four square silicon carbide MOSFET cells, the P + region is of a split gate structure, and gates of other regions in the square are of a traditional gate structure. The periodic array of the silicon carbide MOSFET cellular structure forms a silicon carbide MOSFET layout structure capable of improving high-frequency performance. The invention further provides a manufacturing method of the MOSFET layout structure. According to the invention, the problem that the on resistance and the Cgd capacitance of the existing device are too large is solved.

A semiconductor device comprises a semiconductor layer structure comprising a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, and a first JFET region having the first conductivity type, and a gate trench extending into the semiconductor layer structure. An upper surface of the first JFET region is positioned below the gate trench. A first conductivity dopant concentration of the first JFET region exceeds a first conductivity dopant concentration of the drift region.

The invention discloses a manufacturing method of a SiC groove terminal structure, and belongs to the technical field of semiconductor manufacturing. Comprising the following steps: forming a plurality of P + regions in an N-epitaxial layer to divide the N-epitaxial layer into a terminal region and a plurality of cellular regions, forming a first Pwell region in the terminal region, and respectively forming a JFET injection region, a second Pwell region and an N + region in the cellular regions; defining a gradual change groove terminal ring in the terminal area and defining a grid electrode groove pattern on the cellular area through photoresist; forming a plurality of terminal region grooves of which the depths are gradually increased in the direction of the cellular region in the terminal region through the pattern, and forming a grid electrode groove in the cellular region; and forming side walls on the terminal region trench and the gate trench, and forming a P-type protection region at the bottom. And removing the side wall and the hard mask layer, and further forming a grid electrode, a source electrode and a drain electrode. According to the method, a mask plate required by the process is not added, a single groove and deep pplus scheme is compatible, and the problem of electric field concentration of a deep pplus transition region during reverse voltage withstanding is solved.

An electrical protection device capable of operating without auxiliary electrical power supply includes a control module configured to detect an electrical fault and a switching module, a first circuit including at least two normally-on JFET transistors and a switching member including a first contact. The switching module is configured so that, upon a switchover of the first contact when the current circuits, an electric arc is formed and so that the appearance of the electric arc generates an electrical signal transmitted to at least one of the transistors, the electrical signal driving the switching of the transistor.

The utility model provides a semiconductor device. The semiconductor device comprises a semiconductor substrate of a first conductive type; the deep well of the second conduction type is located in the semiconductor substrate; the shallow well of the first conductive type is located in the semiconductor substrate on the outer side of the deep well of the second conductive type; the JFET source electrode region, the drain electrode region and the LDMOS source electrode region are arranged at intervals; a field oxide layer, a JFET polysilicon gate and an LDMOS polysilicon gate, the field oxide layer is located in the deep trap of the second conduction type, and the JFET polysilicon gate and the LDMOS polysilicon gate are located on the field oxide layer; and the high-voltage well of the first conduction type comprises a first part and a second part, the first part is located in the deep well of the second conduction type between the JFET source region and the drain region, the second part is located in the deep well of the second conduction type between the drain region and the LDMOS polysilicon gate, and the second part is distributed in a polygonal matrix. The semiconductor device provided by the utility model can meet the performance requirements of the LDMOS and the JFET at the same time.

A Schottky barrier integrated field effect transistor and a manufacturing method therefor. The field effect transistor comprises: a first conductive type substrate (1); a first conductive type epitaxial layer (2), wherein the first conductive type epitaxial layer (2) comprises second conductive type doped regions (21), and a JFET region (23) is formed between adjacent second conductive type doped regions (21); gate-source isolation structures (3), wherein an accommodating region (4) is formed between adjacent gate-source isolation structures (3); a Schottky barrier layer (5), wherein the Schottky barrier layer (5) is located in the accommodating region (4) and in contact with the JFET region (23); and gates (6), separated from the Schottky barrier layer (5) by means of at least the gate-source isolation structures (3), wherein the thickness of the sides of the gate-source isolation structures (3) close to the Schottky barrier layer (5) is greater than the thickness of the sides of the gate-source isolation structures (3) distant from the Schottky barrier layer (5).

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure for improving dynamic characteristics, which comprises a SiC VDMOSFET structure formed by mutually connecting a plurality of VDMOS cells in parallel, each VDMOS cell comprises a drain electrode, a metal source electrode, a grid electrode and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, an N well layer, a P well layer and a depletion layer; wherein the N well layer is isolated from the diffusion layer by the P well layer, and the N well layer is in ohmic short circuit with the metal source electrode. According to the utility model, the charge conduction performance of the depletion layer is changed by doping phosphorus elements with different concentrations in the depletion layer region, the depletion layer has a better charge attraction effect in a conduction state, and the JFET region is reduced to the third region of the depletion layer along with the increase of the grid voltage, so that the conductivity of a charge channel is multiplied, and the conductivity of the charge channel is improved. Therefore, bidirectional optimization of switching loss and switching EMI noise can be realized, and the purpose of improving the dynamic characteristics of the device is achieved.

According to the junction field effect transistor device, the preparation method thereof and the electronic equipment provided by the invention, the threshold voltage of the device can be controlled through the low-voltage JFET channel region (namely the first horizontal part) formed by the first P-type ion implantation. Meanwhile, the size of the vertical channel (namely the first vertical part) is determined through first P-type ion implantation, groove etching is carried out in an implantation region, the size of the etched vertical channel and the size of the P-type gate (namely the second P-type region) are decoupled, and the influence of vertical channel etching on threshold voltage and drain breakdown voltage is avoided. Moreover, the gate ohmic contact layer is formed in the trench region (namely above the second horizontal part) to be connected to the gate of the device, so that the gate-drain capacitance CGD of the device can be reduced, the input capacitance and gate charge of the device are reduced, the switching speed of the device can be improved, the switching loss of the device is reduced, and the switching performance of the device is improved. The method is very suitable for the common direct drive type application of the high-voltage normally-open JFET.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses a silicon carbide semiconductor device with an N-top region, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that the semiconductor epitaxial layer comprises an N substrate layer and an N drift layer, a P + well layer, an N well layer and a P well layer are formed in the N drift layer through ion implantation; a first N-type doped region is formed in the N drift layer and located under the grid electrode through ion implantation, and a P-type doped region is formed in the first N-type doped region through ion implantation. A PN junction formed by P-type doping can generate a large depletion layer, the depletion layer mainly expands to a JFET region with low doping concentration, short-circuit current flows through a position closer to the center of the JFET region, the density of the short-circuit current can be effectively reduced by adding the first N-type doping region and the P-type doping region, and the short-circuit tolerance time of the device is prolonged.

The SiC JFET structure comprises a drain electrode metallization layer, an N + substrate layer, an N-drift region, a P first gate region, an N current expansion region, a P second gate region, an N + source region, a gate electrode metallization layer, an insulating dielectric layer, a source electrode ohmic contact layer, a source electrode Schottky contact layer and a source electrode metallization layer. The P first gate regions are embedded in the upper surface of the N-drift region, the gap between the two P first gate regions forms a vertical conductive channel structure, and the source Schottky contact layer is located right above a channel to form a Schottky diode structure, so that the conduction loss during follow current of the device can be effectively reduced; meanwhile, the gate metallization layer is located at the bottom of the gate trench and directly connected with the P first gate region, the gate metallization layer is isolated from the source metallization layer through the insulating dielectric layer in the gate trench, and the device has the advantages of being small in reverse blocking leakage current, high in reliability and the like.

The invention discloses a direct-current solid-state circuit breaker with a voltage limiting protection circuit and a control method thereof. The direct-current solid-state circuit breaker comprises a solid-state switch module, the solid-state switch module comprises a first sub-module and a second sub-module which are the same, and each of the first sub-module and the second sub-module comprises a SiC JFET device J, capacitors C, Cgd and Cgs, a comparator U, an MOSFET device Q, a resistor Rg and resistors ra and rb; the first end of Rg is used for receiving a driving signal, and the second end of Rg is connected to the grid electrode of J after being connected with the first end of C, the second end of Cgd and the first end of Cgs; the second end of ra and the first end of rb are connected as a comparison voltage sampling point; the first end of ra is connected to the first end of Cgd and the drain electrode of J; the second end of the rb is connected to the second end of the Cgs, the source electrode of the Q and the source electrode of the J; the second end of C is connected to the drain electrode of Q; the output end of U is connected to the grid electrode of Q; the anode input of U is comparison voltage, and the cathode input is reference voltage; the source electrode of the first sub-module J is connected to the drain electrode of the second sub-module J.

The utility model discloses a TBU circuit, which comprises an N-channel depletion type MOSFET or an N-channel JFET, a P-channel depletion type MOSFET and a current limiting element, the source electrode of the N-channel depletion type MOSFET or the N-channel JFET is connected with the source electrode of the P-channel depletion type MOSFET, one end of the current limiting element is connected with the grid electrode of the N-channel depletion type MOSFET or the N-channel JFET, and the other end of the current limiting element is connected with the drain electrode of the P-channel depletion type MOSFET; a first voltage stabilizing branch is connected in parallel between the grid electrode and the source electrode of the N-channel depletion type MOSFET or the N-channel JFET, and a second voltage stabilizing branch is connected in parallel between the source electrode and the grid electrode of the P-channel depletion type MOSFET. According to the utility model, the voltage proportion of the N-channel depletion type MOSFET or the N-channel JFET and the P-channel depletion type MOSFET can be adjusted, and the withstand voltage value of the N-channel depletion type MOSFET or the N-channel JFET and the P-channel depletion type MOSFET can be designed flexibly.

The invention provides a planar silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof. The planar silicon carbide MOSFET device structurally comprises an N + substrate, an N-drift region, a P-well region with a buried layer, an N + source region, a P + source region, a current expansion layer, P-type polycrystalline silicon, a gate medium, an insulating medium, N-type polycrystalline silicon, a gate electrode, a source electrode and a drain electrode. A P-type buried layer connected with a source potential and P-type polycrystalline silicon are introduced on the basis of a traditional planar MOSFET, low third quadrant conduction voltage drop is realized through a silicon-silicon carbide heterojunction, and the saturation conduction current of the device is reduced and the short-circuit tolerance time is prolonged through an introduced JFET region. In addition, because the device adopts the split gate and comprises the P-type buried layer, the overlapping area of the gate and the drain is reduced, the Cgd of the device is reduced, and the switching speed of the device is improved.

According to the field effect transistor, a first JFET is formed in a first epitaxial layer, and a second MOSFET is formed in a second epitaxial layer. The forbidden band width of the material of the first epitaxial layer is greater than that of the material of the second epitaxial layer; the second epitaxial layer is formed on the top surface of the first epitaxial layer, and the contact surface of the first epitaxial layer and the second epitaxial layer is heterojunction; a first source region of the first JFET and a second drain region of the second MOSFET are connected through a first floating metal contact hole penetrating through the heterojunction. A first gate region of the first JFET is connected to a source consisting of a front metal layer through a deep contact hole penetrating through the heterojunction; the second source region is connected with the source electrode. The back face of the first drain region is connected to a drain electrode composed of a back face metal layer. The invention further discloses a manufacturing method of the field effect transistor. The invention has the advantages of a wide bandgap semiconductor material device, and can overcome the problems of high channel carrier mobility, high driving voltage and poor reliability of the gate dielectric layer of the wide bandgap semiconductor material device.

A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.

The present invention discloses a radiation-hardened SiC MOSFET device structure and a preparation method thereof, including an N- drift layer. An N+ substrate layer is provided below the N- drift layer, and a drain metal layer is provided below the N+ substrate layer. A carrier storage layer is provided above the N- drift layer, and a source metal layer is provided above the carrier storage layer. A JFET region is provided in the middle below the source metal. Trenches are introduced into the JFET region, and a P-type doping region and a filling region are provided inside the trenches. P-base regions are provided on both sides of the trenches, and an N+ source region and a P+ region are provided in the P-base regions. By adopting the above-mentioned radiation-hardened SiC MOSFET device structure and preparation method, the present invention greatly reduces the electric field strength in the thin oxide, thereby improving the single-event upset resistance of the SiC MOSFET device; only processes such as trench etching, P-type ion implantation on the sidewalls and bottom of the trench, and trench backfilling are required, and the process complexity is not high.

The invention provides a SiC transverse JFET device, and the device comprises a substrate of a second doping type, and the substrate is grounded; an epitaxial layer of a SIC material of a first doping type formed over the substrate; the first through hole downwards penetrates through the epitaxial layer from the upper surface of the epitaxial layer, and the bottom end of the first through hole enters the substrate; the connection region of the SIC material of the second doping type is filled in the first through hole; the source electrode of the first doping type is formed in the epitaxial layer; the source electrode contact metal compound is formed on the connecting region and is electrically connected with the source electrode; wherein the source contact metal compound is electrically connected with the grounded substrate of the second doping type through the connecting region of the second doping type. The technical problem that the occupied device area is large due to the fact that the source electrode of a traditional SiC transverse JFET device is grounded is solved.

A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

The invention provides a JFET (Junction Field Effect Transistor) device and a preparation method thereof. The JFET device comprises a substrate layer; the drift layer is positioned on one side of the substrate layer along the first direction; the first doped regions are spaced along the second direction, the conduction type of the first doped regions is opposite to that of the drift layer, and the first doped regions and the surface of one side, facing the substrate layer, of the drift layer are spaced along the first direction; the gate doped region is positioned on one side, deviating from the substrate layer, of the first doped region along the first direction; the source regions are located between the adjacent first doped regions; the pinch-off regions are positioned between the adjacent first doped regions and between the substrate layer and the source region; wherein the size of the first doped region in the first direction is 0.8-4 microns; wherein the second direction intersects with the first direction.

The invention discloses a low-noise high-gain preamplifier which comprises a first differential amplification circuit, a second differential amplification circuit and a secondary amplification module, the first input end of the first differential amplification circuit is electrically connected with a differential input signal, and the output end of the first differential amplification circuit is electrically connected with the input end of the second differential amplification circuit; the output end of the second differential amplification circuit is electrically connected with the second input end of the first differential amplification circuit and the input end of the secondary amplification module, the output end of the secondary amplification module is electrically connected with the input end of the receiving terminal, the first differential amplification circuit comprises a plurality of JFETs, and the second differential amplification circuit comprises a plurality of operational amplifiers; the first differential amplification circuit amplifies the differential signal, the second differential amplification circuit amplifies the amplified differential signal again to obtain a primarily amplified voltage signal, and the secondary amplification module amplifies the primarily amplified voltage signal. According to the invention, low-noise and high-gain amplification processing on the differential input signal is realized.

The invention provides a semiconductor device capable of improving short-circuit tolerance and reducing gate capacity while maintaining a high channel density in a trench MOSFET having a vertical channel fin structure. The present invention is provided with: a plurality of trenches (2) arranged in a second direction and having a long side direction in a first direction and a short side direction in the second direction in plan view; a first source region (3) of the first conductivity type; a second source region (4) of the first conductivity type including a region at least partially having a fin structure demarcated by the plurality of trenches (2); a second conductivity-type channel region (5) having a fin structure, the channel region (5) being partitioned by the plurality of trenches (2); a gate insulating film and a gate electrode disposed inside the trench (2); a JFET region (8) of the first conductivity type; and a body region (9) of a second conductivity type in which a channel current flows in the vertical direction, and in the semiconductor device (1), the depth of the second source region (4) from the surface is shallower than that of the first source region (3).

The invention discloses a component bidirectional aging tool based on aging equipment and a testing method. The component bidirectional aging tool comprises an aging plate; station needles are arranged on the aging plate and used for aging different types of devices and installing aging sockets, golden fingers are arranged at the two ends of the aging plate, polarity conversion slots are formed in the positions close to the golden fingers, and the polarity conversion slots are connected with the golden fingers; an electrode connecting line is arranged on the aging plate, one end of the electrode connecting line is connected with an aging test device electrode, and the other end of the electrode connecting line is correspondingly connected with the polarity conversion slot; and a polarity conversion plate is arranged on the polarity conversion slot. By applying the technical scheme of the invention, the problems of device appearance damage and low production efficiency caused by manual reversing operation in the aging process of a non-polar capacitor and a bidirectional TVS (Transient Voltage Suppressor) in the prior art can be effectively solved, and the problem of high cost during aging of devices such as transistors with different polarities, JFETs (Junction Field Effect Transistor) and the like can be effectively solved, and an aging tool does not need to be manufactured again.

The invention discloses a SiC MOSFET cellular structure with a built-in junction barrier Schottky structure and a preparation method thereof.The cellular structure comprises a substrate, an epitaxial layer, a JFET region, P-well regions, a gate oxide layer and a gate poly layer, the epitaxial layer is arranged on the upper surface of the substrate, the JFET region is arranged in the middle of the upper surface of the epitaxial layer, the P-well regions are arranged on the left side and the right side of the JFET region, the gate oxide layer is arranged on the P-well regions, and the gate poly layer is arranged on the P-well regions. Each P-well region comprises an N + region and a P + region, the JFET region is composed of a low-doped N-high-resistance region and two high-doped N + low-resistance regions, the N-high-resistance region is located in the middle of the JFET region, and the two N + low-resistance regions are located on the two sides of the N-high-resistance region respectively. A doped region similar to a sandwich is adopted in the JFET region of the cellular structure provided by the invention. According to the structure, the specific on-resistance of the device can be reduced, and meanwhile, the short-circuit performance of the device is improved.

The present application discloses a SiC MOSFET cell structure and a manufacturing method therefor. The cell structure comprises: a source electrode metal region (source), a source electrode OHM region, a source electrode ohmic contact region N+, a channel N-type doped region NC, a channel P-type doped region PC, a vertical conductive channel JFET region, a Pwell region, a drift layer N-, a substrate N+, a drain electrode OHM region, a gate electrode region (gate), and a gate-source isolation medium SiO2.