14results about How to "Increase the doping concentration" patented technology

This invention relates to the field of CMOS integrated circuit manufacturing processes and discloses a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by implantation. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

The embodiment of the present application provides a diode device, which comprises: a first semiconductor layer of a first doping type; a field termination layer of the first doping type formed on the first semiconductor layer; a field transition layer of the first doping type formed on the field termination layer; a drift region of the first doping type formed on the field transition layer, and a plurality of column regions of a second doping type formed in the drift region and arranged at intervals; a second semiconductor layer of the second doping type formed above the drift region; the doping concentration of the field transition layer is less than the doping concentration of the field termination layer, the drift region and the field transition layer can respectively cause a conductive modulation effect to accumulate minority carriers; when the diode device is turned off, the field transition layer is completely depleted, the electric field is reduced in the field transition layer and reduced to 0 in the field termination layer. The embodiment of the present application solves the technical problem that the traditional SJ-diode device has large turn-off energy loss caused by tail current in the turn-off process.

The present application belongs to the technical field of solar cells, and relates to a heterojunction solar cell, which comprises, from a light-facing side to a back light-facing side, a first electrode, a first conductive film layer, an N-type semiconductor film layer, an intrinsic film layer, a semiconductor substrate, a tunneling oxide layer, a P-type carbon-doped semiconductor film layer, a high-concentration P-type doped semiconductor film layer, a second conductive film layer, and a second electrode; the first conductive film layer fully covers the N-type semiconductor film layer, and the first electrode is electrically connected to the N-type semiconductor film layer through the first conductive film layer; the second conductive film layer fully covers the high-concentration P-type doped semiconductor film layer, and the second electrode is electrically connected to the high-concentration P-type doped semiconductor film layer through the second conductive film layer. The present application aims to provide a heterojunction solar cell, which can improve the electrical power loss caused by the carrier transmission on the back of the cell and improve the cell efficiency.

The application provides a transverse gallium oxide Schottky diode with equivalent transverse variable doping realized by a multilayer P-type nickel oxide and a preparation method thereof. The device comprises a substrate, an N-type gallium oxide epitaxial layer provided with an N-type gallium oxide heavily doped region, a multilayer P-type nickel oxide layer arranged in a longitudinal ladder shape, an anode metal layer, a cathode metal layer and a passivation layer. In view of the characteristics of non-uniform electric field distribution and high concentration of anode area electric field in a transverse power device, the application adopts a multilayer P-type nickel oxide structure to relieve the concentration of anode area electric field peak and the electric field of a flat surface through equivalent transverse variable doping design. The first P-type nickel oxide layer cooperates with the second P-type nickel oxide and the third P-type nickel oxide layer to form a gradient doping distribution, effectively expands the depletion region and reduces the peak electric field strength, thereby significantly improving the reverse blocking capability and the breakdown voltage of the device, and meanwhile, the carrier concentration of the epitaxial layer can be appropriately increased to reduce the on-resistance. Therefore, the device can realize a higher reverse breakdown voltage and a lower on-resistance.

The invention relates to a solar cell and a photovoltaic module, and the solar cell comprises a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first conductive layer, and a second conductive layer. A first conductive layer is arranged on one surface of the first semiconductor layer deviating from the silicon substrate; at least part of the first conductive layer comprises alternating amorphous conductive layers and microcrystalline conductive layers; a second conductive layer is arranged on one surface, deviating from the silicon substrate, of the second semiconductor layer; the second conductive layer is an amorphous conductive layer. According to the scheme, the amorphous conducting layers and the microcrystalline conducting layers are alternately arranged on the first semiconductor layer, the contact resistance and the optical transmittance of the cell can be better balanced, and therefore the overall performance of the cell is improved, the second conducting layer is arranged to be the amorphous conducting layer, the characteristic that the optical transmittance of the amorphous conducting layer is better is utilized, and the performance of the cell is improved. Therefore, the purpose of balancing the optical and electrical properties of the conductive layer of the second area is achieved.

The application discloses a semiconductor device structure, a preparation method thereof and a semiconductor device. The semiconductor device structure comprises: an active region arranged on a substrate; a contact hole arranged on the active region; and a doped semiconductor layer filled in the contact hole, wherein the doped semiconductor layer has a recess structure on a top surface thereof, and the recess structure increases a contact area on the top surface of the doped semiconductor layer. The application increases the doping concentration of the doped semiconductor layer to be higher than a conventional doping concentration, so that the doped semiconductor layer forms filling defects when being filled, and the recess structure is formed on the top surface, thereby significantly increasing the contact area, greatly reducing the contact resistance and the resistance of the contact hole itself, significantly reducing the overall resistance of a circuit, reducing RC delay, reducing power consumption, enhancing signal integrity, prolonging service life, and being beneficial to further miniaturization of the device.

The application provides a solar cell, a photovoltaic module and a preparation method of the solar cell. The solar cell comprises a substrate, a first surface and a second surface oppositely arranged along a thickness direction, an emitter arranged on the first surface, a tunneling layer arranged on the second surface, and a polysilicon doped layer arranged on a side of the tunneling layer away from the substrate, and a first conductive layer arranged on a surface of the emitter away from the substrate. The application helps to reduce the lateral resistance of the emitter, avoids increasing the doping concentration of the contact position of the metal and the silicon wafer, effectively reduces the surface contact recombination, improves the cell efficiency, and improves the electrical performance and service life of the cell.

The invention discloses a preparation method of a gluconic acid modified oxygen evolution electrocatalyst and application of the gluconic acid modified oxygen evolution electrocatalyst in catalysis of seawater oxidation, foamed nickel is placed in deionized water of (NH4) 6Mo7O24. 4H2O and monobasic strong acid for reaction, and then the reacted foamed nickel is placed in a reaction system containing ferrous gluconate to prepare the oxygen evolution electrocatalyst. The oxygen evolution electrocatalyst can form a hydrogen bond on an outer Helmholtz layer through a gluconic acid ligand in a seawater oxidation process, so that the stability of a hydrated potassium ion layer is effectively reduced, and OH <-> is smoothly transferred to an inner Helmholtz layer; meanwhile, the formed hydrogen bond network is beneficial to reducing the dehydrogenation energy barrier in the oxygen evolution reaction process, and the technical problem that the seawater oxygen evolution reaction efficiency is low is solved to a certain extent; charges on the surface of the catalyst can be modified through the reduction effect of gluconic acid, the technical problem that seawater oxidation reaction selectivity is poor is solved, and the method has important significance on development of seawater oxygen evolution electrocatalysts with high selectivity and activity.

The invention discloses rare earth doped multi-component optical glass ink, an additive manufacturing method thereof and optical glass. The ink is prepared from a metal salt containing a rare earth metal salt, a precursor compound, deionized water, a photocuring monomer, a photoinitiator and other raw materials through a sol-gel technology, and in-situ uniform doping of rare earth ions on the molecular level is achieved. The ink can be molded into a gel blank with a complex structure through a photocuring 3D printing technology, and then the gel blank is dried, sintered and annealed to finally obtain the high-performance rare earth doped multi-component optical glass. According to the method, the limitation of a traditional high-temperature melting method and an existing second-phase doping additive manufacturing technology is broken through, organic combination of a device with a complex structure, molecular-level uniform doping and low-temperature preparation is achieved, and the method has wide application prospects in the fields of micro lasers, integrated optical devices and the like.

The application relates to an AlGaN / GaN vertical high electron mobility transistor and a manufacturing method thereof; solves the problem that when the field plate technology is applied to a device with a vertical drift region, the vertical drift region is easily affected by charge imbalance, thereby affecting the on-current; comprises a substrate of a GaN material; an N-type drift region, a GaN channel layer and an AlGaN barrier layer are sequentially grown above the substrate; a source region is formed on the upper surface of the AlGaN barrier layer, and a source electrode is arranged in the source region; the same number of P-type floating buried layers are formed on the left and right sides of the N-type drift region, and a P-type blocking layer is formed on the upper portion of the N-type drift region; a multilayer stepped dielectric groove is formed by etching through the middle portions of the N-type drift region, the P-type blocking layer, the GaN channel layer and the AlGaN barrier layer; a multilayer stepped oxide layer is arranged on the inner wall of each side of the dielectric groove; an SIPOS field plate is deposited between the oxide layers on the two sides; polycrystalline silicon is deposited above the SIPOS field plate; a gate electrode and a passivation layer are arranged above the polycrystalline silicon; and the two source electrodes are connected in common.

This invention provides a GGNMOS device in which a first N-type sub-doped layer, a second N-type sub-doped layer, and a third N-type sub-doped layer are formed at the N-type well layer. This is equivalent to forming a large parasitic resistance between the first N-type sub-doped layer and the second N-type sub-doped layer, and similarly, a large parasitic resistance between the first N-type sub-doped layer and the third N-type sub-doped layer. This ensures that the drain structure of the GGNMOS device has a high breakdown voltage while reducing the manufacturing cost of the GGNMOS device.

The application discloses a preparation method of a buried heterojunction for a distributed feedback laser, which can reduce the threshold current of a laser, greatly improve the consistency of a device and has strong process compatibility. The method introduces a selective Zn diffusion treatment process step after growing a buried layer on a top cladding layer. A high-concentration p-type region formed through the diffusion step can form a more ideal ohmic contact with a metal electrode. In addition, an extra thin gold layer with a thickness of 5-10 nm is evaporated on the top cladding layer, which can significantly reduce the ohmic contact. The ohmic contact is reduced from 1.2e ‑5 to 4.5e ‑7 , about 26.6 times. In addition, while reducing the ohmic contact, the current limiting effect is significantly enhanced. The threshold current of the laser prepared by the method can be reduced to 15-18 mA. In addition, the method has low process difficulty, high operability, high freedom and greatly improved device consistency. Moreover, the method has strong process compatibility. The method is suitable for popularization and application in the field of semiconductor lasers.

This invention relates to the field of N-type crystalline silicon solar cell manufacturing technology, specifically to a graded deposition LPCVD process for N-type cell passivation layers. The main steps include depositing a silicon-oxygen tunneling layer of 1.5–2.5 nm and graded deposition of the film layers. The graded deposition steps include: a first-stage deposition to obtain a polycrystalline silicon film of 90–150 nm with a crystallinity of 80–95%; a second-stage deposition to obtain a polycrystalline silicon film of 50–100 nm with a crystallinity of 60–80%; and a third-stage deposition to obtain a polycrystalline silicon film of 30–80 nm with a crystallinity ≤50%. This invention achieves polycrystalline silicon films with crystallization gradient characteristics by changing process parameters, such as pressure, temperature, and gas flow rate ratio, within the same deposition process. The crystallinity of polycrystalline silicon significantly affects the diffusion behavior of impurity atoms subsequently doped using methods such as boron diffusion and phosphorus diffusion. This technology can optimize film performance, meet specific process application requirements, and further improve cell performance.

The application relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a buried layer arranged in the substrate, a first well region arranged on the upper surface layer of the buried layer, a second well region arranged on the upper surface layer of the buried layer and partially in contact with the substrate, the second well region being located at the periphery of the first well region, a plurality of emitter lead-out regions and base lead-out regions arranged on the upper surface layer of the first well region and spaced apart from each other, a gate structure arranged on the upper surface of the substrate and comprising a gate, the orthographic projection of the gate on the first well region being staggered with the emitter lead-out regions, and a collector lead-out region formed in the upper surface layer of the second well region. The plurality of emitter lead-out regions are connected in parallel to lead out the emitter, and the gate and the collector lead-out region are connected in parallel to lead out the collector. The input voltage of the collector can be changed to control the gain current of the semiconductor device and the effective doping concentration of the emitter lead-out region.