66results about How to "Increase the doping concentration" patented technology

The invention belongs to the technical field of crystal growth, and provides a low-resistivity silicon carbide single crystal growth method and system and a single crystal, silicon carbide powder is uniformly paved at the bottom of a graphite crucible, metal carbide material particles are uniformly paved on the surface of the silicon carbide powder, and silicon carbide seed crystals are adhered to the top of the graphite crucible; the graphite crucible is sealed, and the interior of the graphite crucible is vacuumized; heating the graphite crucible subjected to vacuumizing treatment, filling carrier gas into the graphite crucible, then slowly replacing the carrier gas with doped source gas, slowly increasing the growth pressure to a set pressure, and growing a buffer layer; after the growth of the buffer layer is completed, changing the growth condition to grow the heavily doped silicon carbide single crystal; and after the growth of the crystal is completed, cooling the graphite crucible subjected to vacuumizing treatment, so that the crystal is naturally cooled, and the low-resistivity silicon carbide single crystal is obtained. The doping concentration of the silicon carbide single crystal can be improved, and the resistivity of the silicon carbide material can be reduced.

The invention provides a quasi-super junction planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, forming a plurality of N-type body regions and a plurality of diffusion regions, and forming a P-type well region, an N-type source region and a current sharing layer; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; the preparation method comprises the following steps of: re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that a quasi-super junction structure and a current sharing layer are constructed in the device, and the voltage endurance capability, the gate reliability and the conduction capability of the device can be effectively improved.

According to the SGT MOSFET of the Low-k material and the preparation method of the SGT MOSFET, a gate insulating layer of the SGT MOSFET is deposited by adopting the Low-k material based on carbon-doped silicon oxide, and an oxide layer on the side wall of a shielding gate adopts an ONO structure, so that on one hand, the capacitance effect of a device can be reduced through the Low-k material under the condition that the physical thickness of the insulating layer is kept unchanged and electric leakage is not influenced, and the performance of the device is improved; the performance of the device is improved; and on the other hand, the compactness of the silicon nitride layer is high, and the side wall and the bottom of the shield gate polycrystalline silicon are protected by the silicon nitride layer, so that the on resistance of the device is further reduced and the conduction loss of the device is reduced by improving the doping concentration of the epitaxial layer on the basis of not reducing the breakdown voltage. Meanwhile, by controlling the depth of the oxide layer and the silicon nitride layer which are etched on the side wall of the groove, the silicon nitride layer is far away from the grid polycrystalline silicon, and the reliability of the device is improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a high-voltage SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) under-gate anti-radiation reinforcing structure which comprises a drain electrode, a semiconductor epitaxial layer, a metal source electrode and a gate electrode, the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and a heavily doped N well layer; wherein the diffusion layer comprises a low-doped N body region I and a carrier storage layer; a groove structure is etched in the surface area of the semiconductor epitaxial layer between the adjacent lightly doped P well layers I; a P-type doped region is formed on the inner surface of the groove structure through ion implantation; and a dielectric layer is formed in the inner cavity of the P-type doped region through deposition. A groove structure is introduced into a JFET region of the SiC MOSFET device, P-type impurities are injected into the side wall and the bottom of the groove to form a P-type doped region, the groove is filled with dielectric materials such as SiO2, the groove structure transfers a strong electric field at a gate oxide interface to the bottom of the JFET region, the electric field intensity in thin gate oxide is greatly reduced, and therefore the single-particle gate penetration resistance of the SiC MOSFET device is improved.

The invention relates to an erbium-doped, ytterbium-doped or erbium-ytterbium co-doped lithium niobate crystal as well as a preparation method and application thereof, and belongs to the field of nonlinear optical crystals. The erbium-doped, ytterbium-doped or erbium-ytterbium co-doped lithium niobate crystal provided by the invention is prepared from Li2CO3, Nb2O5 and Er2O3 and / or Yb2O3 with the purity of 99.99%; wherein the atomic molar ratio of Li to Nb is 0.80-0.92, and the doping molar fraction of Er2O3, the doping molar fraction of Yb2O3 and the total doping molar fraction of Er2O3 and Yb2O3 are respectively 0.75%-1.25%. The erbium-doped, ytterbium-doped or erbium-ytterbium co-doped lithium niobate crystal prepared by the invention is high in crystallization quality, large in doping concentration, uniform and transparent as a whole and free from obvious macroscopic defects, and can be used for preparing a high-quality lithium niobate bulk material and a submicron lithium niobate film so as to further prepare high-efficiency photoelectric functional devices such as a laser, an amplifier and a detector; and a foundation is laid for development of the fields of integrated photonics and the like.

The invention provides a quasi-super junction trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed above the drift layer, etching and ion implantation are carried out, a plurality of N-type regions, a plurality of P-type masking regions, a P-type well region, an N-type source region and a P-type source region are formed, the barrier layer is formed again, etching and oxidation are carried out to form a gate dielectric layer, and a groove is formed in the gate dielectric layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. An N-type region and a masking region are constructed in the device, so that a transverse and longitudinal combined quasi super junction voltage-withstanding structure is formed to improve the voltage-withstanding capability of the device, and meanwhile, the N-type region can reduce the on resistance of the device.

The invention discloses a self-aligned double-epitaxial super-junction MOSFET and a manufacturing method, the self-aligned double-epitaxial super-junction MOSFET comprises a semiconductor layer arranged on a substrate, a plurality of body regions distributed along the surface of the semiconductor layer are arranged in the semiconductor layer, and a source region located below the surface of the semiconductor layer is arranged in each body region; the pair of first side walls are arranged on the surface of the semiconductor layer above each source region in a self-aligned manner; the super junction groove is arranged in the semiconductor layer in a penetrating manner between each pair of first side walls; the first epitaxial layer of the first conductive type and the second epitaxial layer of the second conductive type are arranged in the super junction groove and are connected with the body region; and the gate oxide layer and the gate electrode are arranged on the surface of the semiconductor layer between two adjacent pairs of first side walls. According to the invention, the range of ion implantation can be accurately adjusted while the number of photomasks is reduced and self-alignment is realized, and the drift region can be directly changed into the intrinsic semiconductor layer, so that the on-resistance can be reduced while the withstand voltage is improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device for improving single-particle radiation recombination efficiency, which comprises a drain electrode, a semiconductor epitaxial layer, a metal source electrode and a grid electrode, and is characterized in that an isolation medium is deposited on the outer surface of the grid electrode; the semiconductor epitaxial layer comprises a substrate layer, an epitaxial layer, a P well layer and a heavily doped N well layer; the P well layer comprises a lightly doped P well layer and a heavily doped P well layer; p-type doped regions are formed between the adjacent lightly doped P well layers through ion implantation, and N-type impurity ions are injected into the P-type doped regions to form N-type polycrystalline silicon. According to the invention, the P-type doped region is formed by injecting P-type impurities in the SiC MOSFET device, the N-type polycrystalline silicon is formed by ion injection in the P-type doped region, and the N-type polycrystalline silicon is in short circuit with the source metal, so that the trench structure transfers a strong electric field at a gate oxide interface to the bottom of the JFET region, the electric field intensity in the thin gate oxide is greatly reduced, and the single-particle gate penetration resistance of the SiC MOSFET device is improved.

The invention discloses a solar cell, a photovoltaic module and a semiconductor substrate, relates to the technical field of photovoltaics, and aims to improve the passivation effect of a passivation layer, improve the contact performance of a doped semiconductor layer and an electrode and improve the shaping of the electrode. The solar cell includes a semiconductor substrate and a passivation layer. The side, away from the semiconductor substrate, of the passivation layer is provided with a first tower footing texture structure and a second tower footing texture structure. The first tower footing texture structure comprises a plurality of first substructures, and the bottom surfaces of the first substructures are recessed into the passivation layer. In the first tower footing texture structure, the first substructure of which the bottom surface is a complete pattern is a target substructure. The second tower footing texture structure includes a plurality of second sub-structures disposed within the first sub-structure, the bottom surfaces of the second sub-structures being recessed into the passivation layer relative to the surface of the first sub-structure. The one-dimensional size of each target substructure is larger than that of each second substructure, and the number of the second substructures arranged on at least one target substructure is larger than or equal to 10.

The invention discloses a preparation process of a poly laminated double-passivation structure of a TOPCon battery and the TOPCon battery, and belongs to the technical field of solar cells, the preparation process of the poly laminated double-passivation structure of the TOPCon battery comprises the following steps: S1, a pretreatment process; s2, preparation of a laminated double-passivation structure: feeding the silicon wafer subjected to the pretreatment process into a furnace tube of a PECVD (Plasma Enhanced Chemical Vapor Deposition) machine, preparing a tunneling oxide layer on the back of the silicon wafer, and preparing the laminated double-passivation structure on the tunneling oxide layer, the laminated double-passivation structure sequentially comprising a buffer layer, a barrier layer and an N-type amorphous silicon layer; the buffer layer is an intrinsic amorphous silicon layer, and the barrier layer is a tunneling oxidation barrier layer. According to the poly laminated double-passivation structure, the controllability of phosphorus doping distribution can be improved, the doping uniformity is further improved, the contact performance can be improved through high phosphorus doping concentration, meanwhile, the N / N high-low junction phenomenon caused by too high phosphorus doping concentration is avoided, the passivation contact performance of a battery piece is improved, and high battery conversion efficiency is obtained.

The invention discloses a planar gate power device. A device unit comprises a drift region, a planar gate, a channel region, a source region and an anti-JFET region. The anti-JFET region is at least divided into an anti-JFET top layer region and an anti-JFET bottom layer region, and the anti-JFET top layer region is located between the channel regions on the two sides of the plane gate. The doping concentration of the anti-JFET top layer region is smaller than that of the anti-JFET bottom layer region, and the lower doping concentration of the anti-JFET top layer region is used for reducing stepping of the device. The higher doping concentration of the bottom region is used to reduce the specific on-resistance of the device. The first doping layer penetrates through the source region and the channel region, and the top region of the first doping layer is used for being in contact with the channel region and serving as a channel leading-out region for leading out the channel region; and the bottom region of the first doping layer is used for exhausting the bottom region of the anti-JFET, so that the breakdown voltage of the device is improved. The invention further discloses a manufacturing method of the planar gate power device. The on-resistance of the device can be reduced and the breakdown voltage of the device can be increased while the stepping of the device is reduced.

This invention relates to the field of CMOS integrated circuit manufacturing processes and discloses a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by implantation. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

The embodiment of the present application provides a diode device, which comprises: a first semiconductor layer of a first doping type; a field termination layer of the first doping type formed on the first semiconductor layer; a field transition layer of the first doping type formed on the field termination layer; a drift region of the first doping type formed on the field transition layer, and a plurality of column regions of a second doping type formed in the drift region and arranged at intervals; a second semiconductor layer of the second doping type formed above the drift region; the doping concentration of the field transition layer is less than the doping concentration of the field termination layer, the drift region and the field transition layer can respectively cause a conductive modulation effect to accumulate minority carriers; when the diode device is turned off, the field transition layer is completely depleted, the electric field is reduced in the field transition layer and reduced to 0 in the field termination layer. The embodiment of the present application solves the technical problem that the traditional SJ-diode device has large turn-off energy loss caused by tail current in the turn-off process.

The invention provides an IGBT (Insulated Gate Bipolar Translator) device and a manufacturing method thereof, the IGBT device comprises an N-type semiconductor layer and a plurality of grooves located in the N-type semiconductor layer, gate electrodes are arranged in the grooves, and the gate electrodes are insulated and isolated from the N-type semiconductor layer through gate dielectric layers; the P-type body region is located between the adjacent grooves, and an N-type emitter region is arranged in the P-type body region; the N-type carrier storage layer is positioned below the P-type body region and is positioned between the adjacent grooves; the bottom of each groove is provided with a P-type protection layer, and the P-type protection layer is located below the N-type carrier storage layer and surrounds the bottom of the groove. The IGBT device adopts the shallow trench, so that the on-state voltage drop can be reduced, and the process yield can be improved; the bottom of the groove is surrounded by the P-type protection layer, so that local charge balance can be formed, and voltage resistance is improved.

The invention discloses a trench LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor with a ring gate structure and a multi-surface high-K dielectric region. The transistor comprises a substrate layer, a buried oxide layer, a silicon film layer and a device top layer. High-K medium thin layers with the same thickness and K value are arranged on the outer surface, except the bottom, of the silicon material in the silicon film layer; and the gate adopts a ring gate structure distributed around the source region. The large-area covered high-K dielectric thin layer is favorable for guiding electric flux and modulating the distribution of a circle of electric field of the annular groove, so that the distribution of the electric field around the groove is more uniform, the RESURF effect is improved, and the breakdown voltage of the device is favorably improved; meanwhile, the high-K medium is helpful to assist in depletion of the drift region, so that the doping concentration of the drift region is improved, and the on-resistance of the device is greatly reduced. In addition, the high-K dielectric thin layer is arranged in a surrounding manner, so that the gate electrode can be embedded in the high-K dielectric thin layer in a surrounding manner to form an annular gate structure; therefore, the problem that the source end of the device is broken down in advance due to the fact that the contacted high-K dielectric is too thick can be prevented.

The invention discloses an RC-IGBT structure and a semiconductor device. The RC-IGBT structure comprises a substrate, a drift region of a first conduction type, a collector region of a second conduction type, a first trench gate and a base region of the second conduction type, a first emitter region of the first conductivity type; a second emitter region of a second conductivity type; the second trench gate extends into the drift region from the second main surface to the first main surface; the anode regions of the second conduction type are arranged on one side, facing the second main surface, of the drift region and are positioned on two sides of the trench gate in the horizontal direction; a channel cut-off region of a first conductive type, wherein the channel cut-off region is arranged at one side, far away from the first trench gate, of the anode region; wherein the anode region is conductively connected with the collector region through an external connecting line. According to the RC-IGBT structure and the semiconductor device, the voltage rebound phenomenon can be effectively eliminated.

The present invention provides a method for manufacturing an HBT device, comprising: providing a substrate on which a heavily doped layer and a plurality of field oxide layers are formed; forming a collector region; forming a first dielectric layer, wherein a first opening is formed in the first dielectric layer; forming a base region, and performing in-situ doping of P-type ions during the growth of the base region; forming a second dielectric layer; etching the second dielectric layer to the surface of the base region to form a second opening and an emitter region, wherein the emitter region has N-type doping; wherein before any step after forming the base region, the method may further include: performing a heat treatment process on the base region. The present invention also provides an HBT device. By performing a heat treatment process on the base region before any step after forming the base region, the present application can avoid the diffusion of P-type ions in the base region, increase the doping concentration of the base region, reduce the resistance of the base region, and increase the characteristic frequency.

Disclosed are a bidirectional TVS device and a preparation method thereof. The device comprises: a substrate of a first doping type; an epitaxial layer of a second doping type located on the substrate, wherein the second doping type is opposite to the first doping type; an isolation structure extending from the surface of the epitaxial layer into the substrate, defining a first region, a second region, a third region, a fourth region and a fifth region isolated from each other in the epitaxial layer; wherein a first diode, a second diode, a third diode and a fourth diode are respectively formed in the first region, the second region, the third region and the fourth region, and a triode is formed in the fifth region; and a metal interconnection structure connecting the cathodes of the first diode and the third diode to the first potential of the triode, and connecting the anodes of the second diode and the fourth diode to the second potential of the triode.

The invention discloses a self-aligned double-epitaxial super-junction IGBT and a manufacturing method, the self-aligned double-epitaxial super-junction IGBT comprises a semiconductor layer arranged on the front surface of a substrate, a plurality of body regions distributed along the surface of the semiconductor layer are arranged in the semiconductor layer, and a source region located below the surface of the semiconductor layer is arranged in each body region; the pair of first side walls are arranged on the surface of the semiconductor layer above each source region in a self-aligned manner; the super junction groove is arranged in the semiconductor layer in a penetrating manner between each pair of first side walls; the first epitaxial layer of the first conductive type and the second epitaxial layer of the second conductive type are arranged in the super junction groove and are connected with the body region; the gate oxide layer and the gate electrode are arranged on the surface of the semiconductor layer between two adjacent pairs of first side walls; the collector region layer and the buffer region layer are sequentially arranged below the surface of the back surface of the substrate. According to the invention, the range of ion implantation can be accurately adjusted while the number of photomasks is reduced and self-alignment is realized, the drift region can be changed into the intrinsic semiconductor layer, and the on-resistance is reduced while the withstand voltage is improved.

The utility model discloses an N-type high-efficiency battery and a battery assembly. The N-type high-efficiency battery comprises an N-type silicon substrate, and a front tunneling layer, a doped crystalline silicon layer and a front antireflection function layer which are sequentially arranged on the front surface of the N-type silicon substrate, the doped crystalline silicon layer at least comprises a first doped crystalline silicon layer, a second doped crystalline silicon layer and a third doped crystalline silicon layer which are sequentially arranged in the direction far away from the front surface of the N-type silicon substrate; the doping concentration of the first doped crystalline silicon layer is larger than that of the N-type silicon substrate. The doping concentration of the first doped crystalline silicon layer and the doping concentration of the third doped crystalline silicon layer are both larger than or smaller than the doping concentration of the second doped crystalline silicon layer. The front side of the N-type high-efficiency battery adopts the structure that the front side tunneling layer is matched with the multi-layer doped crystalline silicon layer with specific concentration change, so that light parasitic absorption can be reduced, the composite loss can be reduced, the resistivity can be reduced, and the comprehensive performance of the N-type high-efficiency battery can be improved.

The invention relates to the technical field of photovoltaic cells, in particular to a TOPCon cell with improved contact resistance and a preparation method thereof.The TOPCon cell comprises a silicon substrate, a phosphorus-doped region, a front passivation layer, a front anti-reflection film, front grid lines, a tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a back anti-reflection film and back grid lines, the back anti-reflection film is a four-layer laminated silicon nitride film layer, wherein at least one layer is a phosphorus-doped silicon nitride film layer, and the refractive index of each layer is gradually reduced; the preparation method of the TOPCon battery comprises the step of depositing a back surface anti-reflection film on the back surface, wherein the preparation method of the back surface anti-reflection film comprises the step of introducing silane, ammonia gas and phosphorane into atmosphere by adopting a PECVD (Plasma Enhanced Chemical Vapor Deposition) machine table for deposition. Phosphorus is doped in a back anti-reflection film to form a phosphorus-doped laminated silicon nitride film layer, after printing and sintering, slurry corrodes the anti-reflection film, phosphorus in the anti-reflection film is activated to enter a polycrystalline silicon layer, the phosphorus doping concentration in the polycrystalline silicon layer is improved, ohmic contact of silver-silicon alloy is improved, and contact resistance is reduced.

The invention belongs to the technical field of nano material preparation. The invention provides a doped silicon nanowire as well as a preparation device, a preparation method and application thereof, an aluminum chloride generation chamber is arranged in a main reaction chamber of the preparation device and is communicated with a silicon source inlet, a catalytic source inlet and a doping source inlet, and aluminum chloride, the silicon source, the catalytic source and the doping source are mixed in an inner cavity of the main reaction chamber by utilizing the preparation device to prepare the doped silicon nanowire. The method comprises the following steps: adding a silicon source into a catalytic source, carrying out a reaction, reducing the silicon source and the catalytic source into monatomic silicon and a metal catalyst by aluminum monochloride in the reaction process, catalyzing the monatomic silicon by the metal catalyst to generate a silicon nanowire, and carrying out in-situ doping on the silicon nanowire by a doping source to obtain a doped silicon nanowire; the scheme is simple and convenient, doped silicon nanowires can be generated on a large scale, the doping type and the doping effect are controllable, and the improvement effect of doping on the performance of the silicon nanowires is ensured.

The present application belongs to the technical field of solar cells, and relates to a heterojunction solar cell, which comprises, from a light-facing side to a back light-facing side, a first electrode, a first conductive film layer, an N-type semiconductor film layer, an intrinsic film layer, a semiconductor substrate, a tunneling oxide layer, a P-type carbon-doped semiconductor film layer, a high-concentration P-type doped semiconductor film layer, a second conductive film layer, and a second electrode; the first conductive film layer fully covers the N-type semiconductor film layer, and the first electrode is electrically connected to the N-type semiconductor film layer through the first conductive film layer; the second conductive film layer fully covers the high-concentration P-type doped semiconductor film layer, and the second electrode is electrically connected to the high-concentration P-type doped semiconductor film layer through the second conductive film layer. The present application aims to provide a heterojunction solar cell, which can improve the electrical power loss caused by the carrier transmission on the back of the cell and improve the cell efficiency.

This application provides a semiconductor device with a silicon carbide ohmic contact and a method for fabricating the same. The semiconductor device includes: a silicon carbide substrate; a single-crystal silicon carbide epitaxial layer formed on the silicon carbide substrate; a first doped region formed downwards from the upper surface of the silicon carbide epitaxial layer; a polycrystalline silicon carbide layer covering the first doped region, wherein the first doped region and the silicon carbide layer have the same doping type, and the doping concentration of the silicon carbide layer is higher than that of the silicon carbide epitaxial layer; and an alloy metal layer covering the silicon carbide layer; wherein both the polycrystalline silicon carbide layer and the single-crystal silicon carbide epitaxial layer are made of silicon carbide, and a tunnel is formed between the polycrystalline silicon carbide layer and the alloy metal layer. This application solves the technical problem of the extremely high requirements for the fabrication process of traditional ohmic contacts.

The invention provides a power device and a manufacturing method thereof, and the power device comprises a semiconductor layer which comprises a first doped region, a second doped region, a well region and a third doped region which are sequentially adjacent to each other in a direction from a second surface to a first surface; the isolation part extends into the second doped region from the first surface of the semiconductor layer and is adjacent to the well region and the third doped region; the semiconductor device further comprises a resistor structure and a diode structure, at least part of the resistor structure and / or the diode structure are / is located in the isolation part, the resistor structure is used for forming a first resistor, the diode structure is used for forming a first diode, one end of the first resistor is electrically connected with the third doped region, and the other end of the first resistor is electrically connected with the second doped region. The other end of the first resistor is electrically connected with the cathode of the first diode, and the anode of the first diode is electrically connected with the well region. The additional resistors and diodes are arranged in the power device, so that the potentials of different areas in the power device are adjusted, and the conduction voltage drop of the power device is further reduced.

The invention discloses a preparation method of a zinc aluminum oxide transparent conductive oxide film. Preparing defective nano aluminum oxide sol; preparing a zinc oxide precursor solution; preparing defect aluminum oxide modulated and doped zinc oxide sol to obtain homogeneous zinc oxide aluminum precursor sol; spin-coating by a sol-gel method; the six dried glass sheets are respectively spin-coated with five different zinc oxide aluminum precursor sols with the doping ratio of 2%-10% and an undoped zinc oxide precursor solution, the spin-coating speed is 2000 rpm, the time is 30 s, and annealing treatment is conducted for 10 min at the temperature of 250 DEG C; detecting the mobility; the problem that the overall performance is affected due to non-uniform conductivity and transparency caused by non-uniform doping in an existing alternative doping technology is solved; and the transparency may be reduced by increasing the doping concentration to improve the conductivity, and traditional doping causes lattice distortion, changes the lattice constant, influences the grain size and shape and the like.

The application provides a transverse gallium oxide Schottky diode with equivalent transverse variable doping realized by a multilayer P-type nickel oxide and a preparation method thereof. The device comprises a substrate, an N-type gallium oxide epitaxial layer provided with an N-type gallium oxide heavily doped region, a multilayer P-type nickel oxide layer arranged in a longitudinal ladder shape, an anode metal layer, a cathode metal layer and a passivation layer. In view of the characteristics of non-uniform electric field distribution and high concentration of anode area electric field in a transverse power device, the application adopts a multilayer P-type nickel oxide structure to relieve the concentration of anode area electric field peak and the electric field of a flat surface through equivalent transverse variable doping design. The first P-type nickel oxide layer cooperates with the second P-type nickel oxide and the third P-type nickel oxide layer to form a gradient doping distribution, effectively expands the depletion region and reduces the peak electric field strength, thereby significantly improving the reverse blocking capability and the breakdown voltage of the device, and meanwhile, the carrier concentration of the epitaxial layer can be appropriately increased to reduce the on-resistance. Therefore, the device can realize a higher reverse breakdown voltage and a lower on-resistance.

An SGT device includes a drift region, a channel region on a surface of the drift region, and a plurality of gate trenches through the channel region. And in the primitive cell region, a source field plate and a gate conductive material layer are simultaneously formed in the gate trench, the side surface of the gate conductive material layer also covers the top region of the drift region at the bottom of the channel region, and the gate conductive material layer forms the gate field plate for transversely depleting the top region of the drift region during reverse biasing. In the source electrode field plate leading-out region, a source electrode field plate is formed in the grid electrode groove and is not provided with a grid electrode conductive material layer, a first compensation region is formed in the interface region of the channel region and the drift region at the bottom, and compensation injection impurities are added in the first compensation region so as to improve the depletion capability of the top region of the drift region. According to the invention, the doping concentration of the drift region in the primitive cell region is relatively high, so that the specific on-resistance of the device is reduced, the weakness of the top region of the drift region in the source field plate extraction region is eliminated, and the withstand voltage of the device is improved.

The present application relates to a p-type AlGaN material and a preparation method thereof, and a preparation method of an ultraviolet photoelectronic device, and belongs to the field of semiconductor technology. The preparation method of the p-type AlGaN material comprises: introducing an organic metal source and an N source at a first temperature to grow the p-type AlGaN material; pausing the introduction of the organic metal source and maintaining the temperature at a second temperature for a certain period of time to allow some Ga atoms in the p-type AlGaN material to escape, thereby generating cation vacancies in the p-type AlGaN material; wherein the second temperature is higher than the first temperature, and the difference between the second temperature and the first temperature ranges from 20°C to 200°C. Thus, the hole concentration of the p-type AlGaN material is increased.

The invention discloses a semiconductor power device and an electronic device. The semiconductor power device comprises a substrate, a drift region, a base region, an active gate, two virtual gates and a carrier storage region, the base body is provided with a first surface and a second surface which are opposite; the drift region is arranged in the substrate and is positioned between the first surface and the second surface; the base region is arranged on one side of the drift region facing the first surface; an emitter region, a contact region and a preset injection region are arranged in the base region; the active gate and the virtual gate penetrate through the base region and extend to the drift region; the active gate is located between the two virtual gates; the carrier storage region is arranged on one side, facing the base region, in the drift region, and is positioned on two sides of the active gate and the virtual gate; the drift region comprises a first drift region which penetrates through the carrier storage region to be in contact with the base region, and the first drift region and the preset injection region are located on the same side, away from the active gate, of the virtual gate. The turn-off loss of the semiconductor power device is reduced while the conduction voltage drop of the semiconductor power device is reduced.