127results about How to "Prevent punch-through" patented technology

A memory cell unit including: a semiconductor substrate having a source diffusion layer provided in a surface thereof; a column-shaped semiconductor layer provided on the source diffusion layer and having a drain diffusion layer provided in an uppermost portion thereof; a memory cell arrangement which includes a plurality of memory cells arranged in series with the intervention of a first impurity diffusion layer; a first selection transistor connected to one end of the memory cell arrangement with the intervention of a second impurity diffusion layer and connected to the drain diffusion layer; and a second selection transistor connected to the other end of the memory cell arrangement with the intervention of a third impurity diffusion layer and connected to the source diffusion layer; wherein a distance between the third impurity diffusion layer and the source diffusion layer is greater than a distance between impurity diffusion layers disposed on opposite sides of each of the memory cells, whereby punch-through of the second selection transistor is prevented when a writing prevention voltage is applied between the source diffusion layer and the first impurity diffusion layer.

The invention discloses a semiconductor structure and a manufacturing method thereof. The method comprises steps: a base is provided, wherein the base comprises a substrate and fin parts protruding against the substrate; a gate structure which crosses over the fin parts and covers the top surfaces and the side wall surfaces of part of the fin parts is formed; the fin parts at two sides of the gatestructure are removed, and grooves with the substrate exposed are formed at two sides of the gate structure; the substrate at the bottom part of the groove is internally provided with an anti-diffusion doping area; and after the anti-diffusion doping area is formed, a stress layer is formed in the groove, and a source-drain doping area is formed in the stress layer. After the grooves with the substrate exposed are formed at two sides of the gate structure, the substrate at the bottom part of the groove is internally provided with the anti-diffusion doping area; later, after the stress layer is formed in the groove and the source-drain doping area is formed in the stress layer, the anti-diffusion doping area is located in the substrate at the bottom part of the source-drain doping area, the anti-diffusion doping area can suppress diffusion of doping ions of the source-drain doping area to a channel area, bottom through can be prevented from happening to the source-drain doping area, and channel leakage current can thus be reduced.

According to some embodiments of the invention, transistors of a semiconductor device have a punchthrough protection layer, and methods of forming the same are provided. A channel-portion hole extends downward from a main surface of a semiconductor substrate. A punchthrough protection layer and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line pattern fills an upper portion of the channel-portion hole, and is formed on the semiconductor substrate. The word line pattern is formed to have a word line and a word line capping layer pattern stacked thereon, and the channel-portion layer is a channel region. The punchthrough protection layer can reduce a leakage current of a capacitor of the transistor embodied in a DRAM.

A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic layer, and a second step of forming a metal atomic layer on the substrate and forming an oxygen atomic layer on the metal atomic layer, wherein the concentration of the metal atoms in the insulator thin film is controlled by controlling the number of times the first step and the second step are carried out.

After forming a gate insulating film on a semiconductor substrate, a silicon film is deposited on the gate insulating film, and a high-melting point metal film is deposited on the silicon film. After forming a hard mask made of a silicon oxide film or a silicon nitride film on the high-melting point metal film, the high-melting point metal film is dry etched by using the hard mask as a mask. After removing a residue or a natural oxide film present on the silicon film through dry etching, the silicon film is dry etched by using the hard mask as a mask. The residue or the natural oxide film is removed while suppressing excessive etching of the silicon film.

The invention provides a semiconductor structure forming method which comprises the following steps: providing a substrate with a well region, wherein a first type of ions are disposed in the well region; using a first anti-punch-through-injection process to inject the first type of ion into the well region wherein the depth of the first anti- punch-through injection process is less than the distance from the bottom of the well region to the top surface of the substrate, forming an anti-punch-through region in the well region; using a second anti- punch-through-injection process to inject carbon ions into the well region to form a carbon doped region in the well region wherein the doped concentration of the carbon ions is greater than that of the first type of ion in the anti-punch-through region and the carbon doped region surrounds the anti-punch-through region; and using a third anti-punch-through-injection process to inject nitrogen ions into the well region wherein the third anti-punch-through-injection depth is less than those of the first anti- punch-through -injection and the second anti-punch-through-injection, forming a nitrogen doped region between the anti- punch-through regions and the top part of the substrate. According to the semiconductor structure forming method, it is possible to improve the performances of a semiconductor device.

The invention discloses a trench metal oxide semiconductor field effect transistor device, which comprises a plurality of closed trench metal oxide semiconductor field effect transistor units surrounded by trench gates, forming a square or rectangular pattern in the active region. Closed cell structure. And in the terminal area of ​​the device, multiple trench rings with floating voltage are included to improve the breakdown voltage of the device.

The part includes a substrate, a silicon monoxide layer. The silicon monoxide layer is deposited on the substrate, making entire part insulate from the substrate. Two grid electrodes are formed on silicon oxide layer. There is a groove between the two grid electrodes. The source electrode and drain electrode are formed on two sides of above grid electrode at plane higher than surface of the groove.

There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.

The invention provides a method for repairing ion implantation damage, comprising the following steps of: providing a semiconductor substrate, and implementing ion implantation process on the semiconductor substrate; performing heat treatment process on the semiconductor substrate in a hydrogen atmosphere, so as to repair ion implantation damage; performing metallization treatment on the semiconductor substrate; and forming a metal connection wire above the semiconductor substrate. Via the method, the lattice damage on the surface of the semiconductor substrate caused by ion implantation can be repaired, thus effectively preventing the deposited metal from entering in the semiconductor substrate during the subsequent metallization treatment process, and then reducing a leakage current, and avoiding a problem of the penetration of a device.

A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.

This invention relates to a method for producing an NROM semiconductor memory device and a corresponding NROM semiconductor memory device. The inventive production method comprises the following steps: a plurality of spaced-apart U-shaped MOSFETS are provided along rows in a first direction and along gaps in a second direction inside trenches of a semiconductor substrate, said U-shaped MOSFETS comprising a multilayer dielectric, especially an ONO dielectric, for trapping charges; source/drain areas are provided between the U-shaped MOSFETS in intermediate spaces located between the rows that extend parallel to the gaps; insulating trenches are provided in the source/drain areas between the U-shaped MOSFETS of adjacent gaps, down to a certain depth in the semiconductor substrate, said insulating trenches cutting up the source/drain areas into respective bit lines; the insulating trenches are filled with an insulating material; and word lines are provided for connecting respective rows of U-shaped MOSFETS.

A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/ID region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell.