Manufacturing method of non-volatile memory

Abstract

A non-volatile memory including at least a substrate, a memory cell and source / drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source / drain regions are disposed in the substrate at both sides of the memory cell.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is a divisional of an application Ser. No. 11 / 306,093, filed on Dec. 15, 2005, now allowed, which claims the priority benefit of Taiwan application serial no. 94121378, filed on Jun. 27, 2005. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE INVENTION[0002]1. Field of Invention[0003]The present invention relates to a semiconductor device, and particularly to a non-volatile memory (NVM), a manufacturing method and an operating method thereof.[0004]2. Description of the Related Art[0005]Among various types of non-volatile memory products, electrically erasable programmable read only memory (EEPROM) is a memory device that has been widely used in personal computers and electronic equipment. Data can be stored, read out or erased from the EEPROM many times and stored data are retained even after power supplying the...

AI Technical Summary

Benefits of technology

[0011]Another object of the present invention is to provide a manufacturing method of the non-volatile memory suitable for fabricating memories with simple process and without punch-through problems.

[0012]Still another object of the present invention is to provide an operating method with higher operation efficiency, lower applied voltage, less power consumption and faster operation speed.

[0018]The non-volatile memory of the present invention combining a first memory unit and a second memory unit is able to avoid second bit effect in the conventional EEPROMs and capable of storing two bits in a single memory cell.

[0023]In the manufacturing method of the non-volatile memory, due to different etching selection ratios between the charge trapping structure and the conductive layer, the charge trapping structure can serve as a self-alignment mask to remove the conductive layer on the first memory unit, which simplifies the process and prevents the memory from punch-through.

[0029]According to the operating method of the non-volatile memory in the embodiment of the present invention, during the above-mentioned erasing operations, an eighth voltage is applied to the second source / drain region, a ninth voltage and a tenth voltage are applied to the first control gate and the second control gate, respectively, and an eleventh voltage is applied to the N-type well region for floating the first source / drain region. Wherein, the ninth voltage and the tenth voltage are less than the eleventh voltage, so that a FN tunneling effect is used for inducing the electrons stored in the floating gate and the charge trapping layer into the N-type well region.

[0035]In the operating method of the non-volatile memory, the adopted operation mode for programming and erasing has a higher efficiency and is capable of injecting and pulling out the electrons more quickly. Therefore, the operation voltage on the memory is reduced, the power consumption is lowered and the device operation speed is advanced.

Problems solved by technology

When erasing data in the EEPROM however, it is likely to over-erase, which leads to misjudgment of data.

Therefore, when programming the memory cell, an abnormal punch-through phenomenon occurs between a drain region and a source region, which has an adverse impact on the electrical performance of the memory.

Since the silicon nitride is able to capture electrons, the electrons injected in the silicon nitride layer would not be evenly distributed in the whole layer.

The memory cells still face the challenge of higher integrity of memory cell and shorter channel length.

As a result, when erasing data, the distribution curve formed by injected hot holes in the silicon nitride layer is not able to overlap with the electron-distribution curve, which leads to incomplete erasing and longer erasing time.

This problem results in a slow operating speed and poor efficiency, even lower reliability.

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