Manufacturing method of non-volatile memory

Abstract

A non-volatile memory including at least a substrate, a memory cell and source / drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source / drain regions are disposed in the substrate at both sides of the memory cell.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is a divisional of an application Ser. No. 11 / 306,093, filed on Dec. 15, 2005, now allowed, which claims the priority benefit of Taiwan application serial no. 94121378, filed on Jun. 27, 2005. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE INVENTION[0002]1. Field of Invention[0003]The present invention relates to a semiconductor device, and particularly to a non-volatile memory (NVM), a manufacturing method and an operating method thereof.[0004]2. Description of the Related Art[0005]Among various types of non-volatile memory products, electrically erasable programmable read only memory (EEPROM) is a memory device that has been widely used in personal computers and electronic equipment. Data can be stored, read out or erased from the EEPROM many times and stored data are retained even after power supplying the...

AI Technical Summary

Benefits of technology

The present invention provides a non-volatile memory that can store multi-bit data in a single memory cell without the second bit effect, and a manufacturing method and operating method for the memory. The non-volatile memory includes a substrate, memory cells, and source / drain regions. The memory cells have a first memory unit and a second memory unit with a charge trapping structure between the first and second control gates. The charge trapping structure includes a tunneling dielectric layer, a charge trapping layer, and a barrier dielectric layer. The non-volatile memory can avoid the second bit effect and has lower power consumption, faster operation speed, and higher efficiency. The manufacturing method includes forming a first memory unit with a floating gate and inter-gate dielectric layer, and a second memory unit with a charge trapping layer and second control gate. The operating method includes applying different voltages to the memory cells for programming.

Problems solved by technology

When erasing data in the EEPROM however, it is likely to over-erase, which leads to misjudgment of data.

Therefore, when programming the memory cell, an abnormal punch-through phenomenon occurs between a drain region and a source region, which has an adverse impact on the electrical performance of the memory.

Since the silicon nitride is able to capture electrons, the electrons injected in the silicon nitride layer would not be evenly distributed in the whole layer.

The memory cells still face the challenge of higher integrity of memory cell and shorter channel length.

As a result, when erasing data, the distribution curve formed by injected hot holes in the silicon nitride layer is not able to overlap with the electron-distribution curve, which leads to incomplete erasing and longer erasing time.

This problem results in a slow operating speed and poor efficiency, even lower reliability.

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