Manufacturing method of silicon MOS transistor on partially consumed insulating layer

Abstract

The invention discloses a manufacturing method of a PD SOI MOS transistor, which comprises the processes of defining an active area on an SOI silicon chip and doping after a gate electrode is formed, wherein the processes comprise the steps of: A. implanting angled ions by taking the gate electrode as a masking film, wherein the type of the implanted impurity is a first type of impurity with the same type as that of the impurity at the bottom inside the silicon film layer of the SOI silicon chip; B. implanting conventional ions by taking the gate electrode as the masking film, wherein the type of the implanted impurity is a second type of impurity with the type opposite to that of the first type of impurity; C. forming side wall layers at two sides of the gate electrode; D. implanting theangled ions by taking the gate electrode and the side wall layers as the masking film, wherein the type of the implanted impurity is the first type of impurity, and the ion implantation energy is setto be higher than that of the angled ions in step A; and E, implanting the conventional ions by taking the gate electrode and the side wall layers as the masking film, wherein the type of the implanted impurity is the second type of impurity. The method effectively inhibits the punch-through of DIBL effect and source leakage deep areas, thus greatly promoting the short channel effect resistant capability of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits and its manufacture, in particular to a method for manufacturing SOIMOS transistors. Background technique [0002] The main device of an integrated circuit, especially a VLSI, is a MOS transistor (MetalOxide Semiconductor Field Effect Transistor, Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET for short). Since the invention of the MOS transistor, it has made rapid progress in performance and function, and this progress has been achieved largely by continuously reducing the size of the device and increasing the chip area. The shrinking of device size leads to the continuous improvement of circuit performance, the continuous increase of circuit density, and the expansion of chip size also promotes the continuous increase of circuit functions. As the geometries of MOSFETs continue to shrink, now with feature sizes at the nanoscale, various practical and fundament...

AI Technical Summary

Problems solved by technology

However, in the prior art, due to the limited control ability of the gate to the channel of the PD SOI MOS transistor, the short-channel effect is serious, and the short-channel effect reduces the threshold voltage, and at the same time leads to the punch-through in the source-drain region, so the PD SOIMOS transistors are also difficult to apply to the production of integrated circuits at the nanoscale

Images