Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The method comprises steps: a base is provided, wherein the base comprises a substrate and fin parts protruding against the substrate; a gate structure which crosses over the fin parts and covers the top surfaces and the side wall surfaces of part of the fin parts is formed; the fin parts at two sides of the gatestructure are removed, and grooves with the substrate exposed are formed at two sides of the gate structure; the substrate at the bottom part of the groove is internally provided with an anti-diffusion doping area; and after the anti-diffusion doping area is formed, a stress layer is formed in the groove, and a source-drain doping area is formed in the stress layer. After the grooves with the substrate exposed are formed at two sides of the gate structure, the substrate at the bottom part of the groove is internally provided with the anti-diffusion doping area; later, after the stress layer is formed in the groove and the source-drain doping area is formed in the stress layer, the anti-diffusion doping area is located in the substrate at the bottom part of the source-drain doping area, the anti-diffusion doping area can suppress diffusion of doping ions of the source-drain doping area to a channel area, bottom through can be prevented from happening to the source-drain doping area, and channel leakage current can thus be reduced.

Description

Technical field [0001] The present invention relates to the field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of the MOSFET has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET. [0003] However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened. As a result, the ability of the gate to control the channel becomes worse, causing subthreshold leakage, namely The so-called short-channel effects (SCE: short-channel effects) are more likely to occur, which increases...

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Problems solved by technology

[0006] However, even if the FinFET structure is introduced in the ultra-shallow junction technology, the electrical performance of the prior art semiconductor structure still needs to be improved.

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