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Backlight assembly for a display

Systems and methods for providing an LGD with a collimated backlight and a non-Lambertian diffuser are described. An LCD system includes: an illumination source for producing light; a collimating waveguide optically connected to the illumination source, the collimating waveguide including a top surface, an incident end and a plurality of substantially parallel optical elements for redirecting light from the incident end to, and through, the top surface by total internal reflection (TR), each of the plurality of substantially parallel optical elements including a first facet that is nonparallel to the top surface and a mirrored second facet that is nonparallel to the top surface; a reflector optically connected to the light source and optically connected to the collimating waveguide, the reflector (1) at least partially surrounding the illumination source, and (2) reflecting light from said illumination source to said incident end by direct reflection; a liquid crystal display optically connected to the collimating waveguide; and a non-Lambertian diffuser optically connected to the liquid crystal display for directing light from said liquid crystal display. The light from the reflector is directly incident upon the incident end. The systems and methods provide advantages in that the light from the LCD is bright and homogenous.
Owner:UNITED CALIFORNIA BANK +1

Apparatus and method for optimized self-synchronizing serializer/deserializer/framer

InactiveUS6459393B1Negatively impact design timeNegatively integrated circuit clock loadingParallel/series conversionViruses/bacteriophagesSerial transferTelecommunications link
An apparatus and method for improving the communication capabilities of computer systems is disclosed. The most preferred embodiments of the present invention use a series of data buffers and data registers to process an incoming high speed data signal. By using the buffers and registers, the incoming signal can be reformatted and manipulated at a much lower frequency than the original transmission frequency. The deserializer of the present invention also samples a greater portion of the incoming data signal than usual to further increase reliability. These various features of the invention provide for a more stable and reliable communication link and will also provide a less expensive solution for serialization/deserialization. The present invention includes a serializer that receives parallel data input from a computer and serializes the data for transmission over a high-speed serial communication link. On the receiving end, the present invention provides a deserializer that can quickly and efficiently transform the serial data back into parallel form for use within the computer system on the receiving end. By utilizing two related clock signals, one clock signal being an integer multiple of the other, a self-synchronizing serializer/deserializer can be created. In addition, by increasing the size of the data sample on the receiving end, the comparisons necessary to retrieve a parallel signal from a serial transmission can occur at a much lower frequency than the frequency of the serial transmission. In the most preferred embodiment, the invention is provided as a integrated solution manufactured on a Peripheral Component Interconnect (PCI) card, thereby allowing the present invention to be easy installed into existing computer systems.
Owner:MEDIATEK INC
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