4 results about "Hot-carrier injection" patented technology

The application provides a semiconductor device and a preparation method thereof, wherein the gate dielectric layer comprises a first edge region and a first central region, the thickness of the first edge region is greater than that of the first central region, and the source-drain region is formed in the semiconductor substrate on both sides of the gate dielectric layer. Since the thickness of the first edge region of the gate dielectric layer is greater than that of the first central region, the electric field intensity of the first edge region of the gate dielectric layer can be reduced, the longitudinal electric field intensity near the source-drain region is reduced, the injection energy of the electrons is reduced, the difficulty of the electrons to inject into the gate through the first edge region of the gate dielectric layer is increased, the hot carrier injection effect of the device is improved, the reliability of the device is improved, and the risk of circuit failure in the device is reduced.

This application discloses a memory, a system, and a method for operating the memory, belonging to the field of memory technology. After the programming stage of the first stack in a memory string, the memory applies a first voltage to one end of the memory string, and applies a second voltage and a third voltage to the first and second selection transistors of the memory string, respectively, turning them on. A fourth voltage is applied to the memory cells of the first stack, turning them on, and a fifth voltage is applied to the memory cells of the second stack, turning them off. This discharges the channel of the memory string. During the discharge process, since some memory cells in the memory string are in a conducting state while others are in a non-conducting state, the current in the channel during the discharge process can be reduced, reducing hot carrier injection into the memory cells of the second stack and decreasing interference to the memory cells of the second stack.

This invention relates to an LDMOS device and its manufacturing method. The LDMOS device includes: a source region; a drain region; a drift region; a field oxide layer; a gate extending from near the edge of the source region onto the field oxide layer; a first low-doped region located directly below the field oxide layer on the side near the source region; and a second low-doped region located directly below the gate on the side near the drain region. The region between the first and second low-doped regions has a first conductivity type. The first and second low-doped regions have the first conductivity type, and their doping concentration is lower than that of the region between them; or the first and second low-doped regions have a second conductivity type. This invention introduces low-doped or inverted regions into areas of concentrated electric field, making the potential line distribution sparser in these two areas, reducing the collisional ionization rate, and mitigating the hot carrier injection effect in these areas.

This invention discloses a semiconductor data testing anomaly early warning method and system, relating to the field of integrated circuit testing technology. The method includes: performing a stepped voltage test on the chip under test by calibrating a purely electronic current signal, while simultaneously monitoring changes in drain current, substrate current increments, and voltage states; calculating hot carrier injection efficiency parameters based on drain current changes and substrate current increments, and combining these parameters with the voltage states to generate photon detection commands; driving an InGaAs avalanche photodiode array to collect photon pulse counts based on the photon detection commands, and calculating a chip damage risk index based on the hot carrier injection efficiency parameters and photon pulse counts to generate a risk assessment report. This invention calculates the chip damage risk index using hot carrier injection efficiency parameters and photon pulse counts, achieving dynamic damage quantification analysis by integrating electrical parameters and optical data, thus achieving holographic perception and early risk identification of chip anomalies.