16 results about "Hot-carrier injection" patented technology

The application provides a semiconductor device and a preparation method thereof, wherein the gate dielectric layer comprises a first edge region and a first central region, the thickness of the first edge region is greater than that of the first central region, and the source-drain region is formed in the semiconductor substrate on both sides of the gate dielectric layer. Since the thickness of the first edge region of the gate dielectric layer is greater than that of the first central region, the electric field intensity of the first edge region of the gate dielectric layer can be reduced, the longitudinal electric field intensity near the source-drain region is reduced, the injection energy of the electrons is reduced, the difficulty of the electrons to inject into the gate through the first edge region of the gate dielectric layer is increased, the hot carrier injection effect of the device is improved, the reliability of the device is improved, and the risk of circuit failure in the device is reduced.

This application discloses a memory, a system, and a method for operating the memory, belonging to the field of memory technology. After the programming stage of the first stack in a memory string, the memory applies a first voltage to one end of the memory string, and applies a second voltage and a third voltage to the first and second selection transistors of the memory string, respectively, turning them on. A fourth voltage is applied to the memory cells of the first stack, turning them on, and a fifth voltage is applied to the memory cells of the second stack, turning them off. This discharges the channel of the memory string. During the discharge process, since some memory cells in the memory string are in a conducting state while others are in a non-conducting state, the current in the channel during the discharge process can be reduced, reducing hot carrier injection into the memory cells of the second stack and decreasing interference to the memory cells of the second stack.

This invention relates to the field of integrated circuit technology, and discloses a switching circuit and method for suppressing the hot carrier injection effect. The switching circuit includes a first switching transistor and a second switching transistor array. The second switching transistor array includes multiple switching transistors connected in parallel. The first switching transistor is connected in parallel with the second switching transistor array, and the conduction area of ​​the first switching transistor is smaller than the total conduction area of ​​the second switching transistor array. The first switching transistor is configured to turn on before the second switching transistor array. This invention can effectively suppress the hot carrier injection effect while achieving high current transmission.

Various embodiments provide apparatuses, systems, and methods for a hot carrier injection (HCI) physically unclonable function (PUF) circuit. For example, described herein is a HCI PUF circuit with n-type metal oxide semiconductor (NMOS) transistors and a Pi-shaped reset structure. Other embodiments may be described and claimed.

Devices including an arrangement of multiple of physically unclonable function (PUF) cells organized to generate a bit pattern, and wherein the PUF cells each includes multiple inverting stages, each inverting stage configured to enable a short circuit between outputs of a pair of inverters to enable accelerated aging of one of the inverters.

This invention relates to an LDMOS device and its manufacturing method. The LDMOS device includes: a source region; a drain region; a drift region; a field oxide layer; a gate extending from near the edge of the source region onto the field oxide layer; a first low-doped region located directly below the field oxide layer on the side near the source region; and a second low-doped region located directly below the gate on the side near the drain region. The region between the first and second low-doped regions has a first conductivity type. The first and second low-doped regions have the first conductivity type, and their doping concentration is lower than that of the region between them; or the first and second low-doped regions have a second conductivity type. This invention introduces low-doped or inverted regions into areas of concentrated electric field, making the potential line distribution sparser in these two areas, reducing the collisional ionization rate, and mitigating the hot carrier injection effect in these areas.

Hot carrier injection (HCI) may be used to provide various improvements for one-time programmable (OTP) read-only memory (ROM) or physical unclonable function (PUF) circuits. HCI may be used to write a memory bit (e.g., logical 0 or 1), which may be used in OTP ROM. HCI may be used to provide improved programmable ROM (PROM) memory devices, such as to facilitate programming or to increase sensing window. HCI may also be used to write a memory bit in a PUF circuit. HCI may provide a cross-foundry portable PUF circuit that has an associated adjustable bit error rate (BER), which may be used to secure root key generation, or may be used to provide a unique identification (ID) for fuse replacement.

A circuit for driving digital-to-analog converter (DAC) comprising a serializer configured to combine multiple signals to one input signal to drive a forward inverter coupled to a first node with a first impedance in serial configuration and a first capacitance in shunt configuration. The circuit includes a chain of inverters coupled in series to transfer the input signal from the first node to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter between the third node and the first node to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node. A second feedback inverter can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

This invention discloses a semiconductor data testing anomaly early warning method and system, relating to the field of integrated circuit testing technology. The method includes: performing a stepped voltage test on the chip under test by calibrating a purely electronic current signal, while simultaneously monitoring changes in drain current, substrate current increments, and voltage states; calculating hot carrier injection efficiency parameters based on drain current changes and substrate current increments, and combining these parameters with the voltage states to generate photon detection commands; driving an InGaAs avalanche photodiode array to collect photon pulse counts based on the photon detection commands, and calculating a chip damage risk index based on the hot carrier injection efficiency parameters and photon pulse counts to generate a risk assessment report. This invention calculates the chip damage risk index using hot carrier injection efficiency parameters and photon pulse counts, achieving dynamic damage quantification analysis by integrating electrical parameters and optical data, thus achieving holographic perception and early risk identification of chip anomalies.

The invention relates to an asymmetric fin heat conduction enhanced GaN HEMT device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices, the asymmetric fin heat conduction enhanced GaN HEMT device comprises a substrate, a buffer layer, a channel layer, a barrier layer, a grid electrode, a source electrode and a drain electrode, a composite passivation layer is formed by embedding high heat conduction heat dissipation fins in a drain electrode side passivation layer, a heat conduction side wall is introduced, and a high heat conduction material and a composite structure are utilized to form a high heat conduction enhanced GaN HEMT device. The heat conduction bottleneck of a surface medium is effectively broken, the surface heat dissipation area is increased, a multi-dimensional heat dissipation path is constructed, the peak temperature in the device is remarkably reduced, parameter degradation and hot carrier injection damage under electrothermal coupling cooperation are relieved from the source, and therefore the overall electrical performance and reliability of the device are improved.

The utility model provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which is characterized in that a source end lightly doped region and a drain end lightly doped region are asymmetrically distributed relative to a grid electrode, and the ratio of the width of the source end lightly doped region extending to the lower part of the grid electrode to the width of the drain end lightly doped region extending to the lower part of the grid electrode is 1: 1.5-1: 2. Therefore, by controlling the ratio of the asymmetrical distribution degrees of the lightly doped regions on the two sides of the grid electrode, the effective channel length of the device is not affected while the hot carrier injection (HCI) effect is improved, then it is guaranteed that electric leakage is not affected, and the performance of the device is improved.

Techniques and mechanisms for accessing memory arrays which are formed in a back end of line (BEOL) of an integrated circuit (IC) die. In an embodiment, a differential sense amplifier of the IC die is coupled to a first array and a second array via a first bit line and a second bit line, respectively. The first bit line and the second bit line extend from a first level of BEOL memory arrays, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first array, wherein the differential sense amplifier is in a footprint region for the first memory array. In another embodiment, a word line driver circuit comprises a two stage charger-discharger circuit which mitigates hot carrier injection.

The invention provides an operation method of a split-gate memory array. The method is applied to a mirror image type memory cell array consisting of a selection tube and memory tubes on two sides. The core is that the erasing operation is realized through grid current carrier tunneling, and positive voltage is applied to a storage tube grid, so that a grid hole is injected into a charge storage layer; write-in operation is achieved through channel hot carrier injection (HCI), a selection tube is weakly turned on to generate nA-level electric leakage, and hot electron injection is formed at the drain end. In the whole operation process, the well region is kept grounded, and a deep N-well (DNW) process is not needed. The invention also provides a refined write suppression bias scheme for three architectures, i.e., an independent source line (DSL), a shared source line (SSL), and a common source line (CSL), to avoid perturbations of non-selected cells. The method has the advantages of high-speed writing, ultra-low power consumption, simplified process and the like, and the operation reliability of the storage array is improved.

The invention provides a BCD device and a preparation method, and the BCD device comprises a wafer substrate which comprises a high-voltage region and a low-voltage region; the first shallow trench is arranged in the high-voltage region, and the first shallow trench is filled with silicon oxide; and the second shallow trench is arranged in the low-voltage region, the second shallow trench is filled with silicon oxide and silicon nitride, and the silicon oxide filled in the second shallow trench is located at two sides of the silicon nitride. According to the invention, the oxide and the nitride are filled in the shallow trench of the low-voltage region to prevent the silicon dislocation defect of the low-voltage region caused by the stress problem, and the oxide is only filled in the shallow trench of the high-voltage region to prevent the hot carrier injection effect of the shallow trench of the high-voltage region to avoid the trap charge defect. The technical problem of silicon dislocation defect caused by stress in the prior art is solved, and the technical effect of improving the performance of the BCD device is achieved.

The invention provides a method for improving the reliability of a laterally diffused metal oxide semiconductor. The method comprises the following steps: providing a P-type semiconductor substrate; defining a drift region and a well region in the substrate; carrying out ion implantation by adopting a P-type heavily doped element to define a P-type body region; defining a gate structure on the surface of the substrate; and defining a source-drain contact region. According to the invention, heavily doped elements such as indium, aluminum and the like are adopted to replace boron to carry out P-type body region injection, and the junction depth and transverse diffusion are effectively controlled and the length of a drift region is maintained by utilizing the low diffusion capability and steep doping characteristics of the elements; meanwhile, the surface electric field peak value is reduced, the electric field distribution is optimized, the hot carrier injection problem is relieved, and the reliability service life of the LDMOS device is remarkably prolonged.

The invention provides a method for improving the reliability of a laterally diffused metal oxide semiconductor. The method comprises the following steps: providing a semiconductor substrate and defining a drift region and a well region on the semiconductor substrate; performing ion implantation in the substrate to form a body region, and introducing a damage layer on the surface of the body region in the implantation process; carrying out a surface treatment process on the surface of the body region, and stripping a damaged layer; and performing source and drain injection. Preferably, silicon surface damage caused by ion implantation (such as arsenic ions) is removed by using hot phosphoric acid wet etching. According to the method, the surface damage layer is removed, the interface state density is effectively reduced, the surface electric field distribution is optimized, and on the premise that the direct-current electrical performance of the device is kept unchanged, the heat carrier injection aging resistance of the device is remarkably improved, and the long-term service life of the device is remarkably prolonged.