49 results about "Hot-carrier injection" patented technology

A P-type Extended Drain MOS (PEDMOS) FETs capable of high speed operation and the capability to withstand relatively high drain voltages. The PEDMOS device includes an active layer (preferably <110> orientated Si) having a P+ SiGe source region, a first P− Si drift region, a second P− SiGe drift region, and a P+ SiGe drain region. The SiGe regions exert compression on the N-type Si channel, improving hole mobility within the PEDMOS device and resulting in low leakage currents at active layer edges, low channel resistance, and good HCI and GIDL characteristics. Forming the SiGe regions may include etching voids in the Si active layer and depositing SiGe within the voids; implanting Ge into defined regions of the Si active layer; or etching partial voids in the Si active layer, depositing SiGe within the partial voids in contact with Si, and diffusing the Ge into the Si.

The invention relates to an enhanced gallium nitride device based on lamination passivation and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device sequentially comprises a substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer from bottom to top, a P-GaN cap layer is arranged on the upper side of the AlGaN barrier layer, passivation layers are arranged on the portions, on the two sides of the P-GaN cap layer, of the AlGaN barrier layer, source electrode metal and drain electrode metal are arranged on the two sides of each passivation layer respectively, the source electrode metal and the drain electrode metal extend to the GaN buffer layer, and grid electrode metal is arranged on the upper side of the P-GaN cap layer. According to the invention, the interface quality of the device is obviously improved, the surface trap effect and hot carrier injection are inhibited, the thermal stress mismatch is relieved, and the overall electrical performance and reliability of the device are improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a silicon carbide SiCMOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) device with improved gate oxide layer reliability, the silicon carbide SiCMOSFET device is composed of a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, a high-K medium is arranged between the grid electrode and the P well layer, and doped polycrystalline silicon is arranged on one side of the high-K medium and located between the source electrode and the N well layer. The high-K medium is one of hafnium oxide, aluminum oxide or zirconium dioxide. Through the double-layer stacked structure of the high-K dielectric and the SiOO gate oxide layer, the high dielectric constant of the high-K material is utilized to share the gate voltage, the electric field intensity of a SiOO interface is remarkably reduced, meanwhile, two orders of magnitude of gate leakage current are reduced, and gate oxide layer degradation caused by hot carrier injection is fundamentally inhibited.

The application provides a semiconductor device and a preparation method thereof, wherein the gate dielectric layer comprises a first edge region and a first central region, the thickness of the first edge region is greater than that of the first central region, and the source-drain region is formed in the semiconductor substrate on both sides of the gate dielectric layer. Since the thickness of the first edge region of the gate dielectric layer is greater than that of the first central region, the electric field intensity of the first edge region of the gate dielectric layer can be reduced, the longitudinal electric field intensity near the source-drain region is reduced, the injection energy of the electrons is reduced, the difficulty of the electrons to inject into the gate through the first edge region of the gate dielectric layer is increased, the hot carrier injection effect of the device is improved, the reliability of the device is improved, and the risk of circuit failure in the device is reduced.

A non-volatile memory cell includes a select transistor and a memory transistor. The first drain / source terminal of the select transistor is connected with a first control terminal. The second drain / source terminal of the select transistor is connected with the first drain / source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain / source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain / source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.

This application discloses a memory, a system, and a method for operating the memory, belonging to the field of memory technology. After the programming stage of the first stack in a memory string, the memory applies a first voltage to one end of the memory string, and applies a second voltage and a third voltage to the first and second selection transistors of the memory string, respectively, turning them on. A fourth voltage is applied to the memory cells of the first stack, turning them on, and a fifth voltage is applied to the memory cells of the second stack, turning them off. This discharges the channel of the memory string. During the discharge process, since some memory cells in the memory string are in a conducting state while others are in a non-conducting state, the current in the channel during the discharge process can be reduced, reducing hot carrier injection into the memory cells of the second stack and decreasing interference to the memory cells of the second stack.

The invention provides a semiconductor device and a manufacturing method thereof. In the semiconductor device, an isolation structure located in a substrate comprises a first isolation structure and a plurality of second isolation structures connected with the first isolation structure, and the plurality of second isolation structures are located on the same side of the first isolation structure and extend into the substrate in a first direction; the gate structure is positioned above the substrate on one side, far away from the first isolation structure, of the second isolation structures, and extends in the first direction to cover the plurality of second isolation structures and cover part of the first isolation structure; the source region is located in the substrate on one side of the gate structure away from the isolation structure; the drain region is located in the substrate at one side of the isolation structure away from the gate structure. Therefore, the fringe electric field of the isolation structure is reduced, and the problem of hot carrier injection failure of the semiconductor device is improved. The manufacturing method of the semiconductor device provided by the invention can be used for manufacturing the semiconductor device.

Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a substrate having a first region, a second region disposed outside the first region, and a third region disposed outside the second region, wherein, in a direction perpendicular to the substrate surface, the surface of the first region is higher than the surface of the second region, and the surface of the second region is higher than the surface of the third region; a gate structure disposed on the substrate surface in the first region; a gate spacer covering the sidewalls of the gate structure and at least covering the substrate surface in the second region; and a source region and a drain region located within the substrate in at least the third region. In a direction perpendicular to the substrate surface, the substrate includes the first region, the second region, and the third region, each with a decreasing surface height. This separates the point of most concentrated current in the substrate from the point of greatest electric field strength in the substrate, thereby reducing the number of hot carriers and thereby lowering the risk of hot carrier injection.

The present technology includes a memory device and a method of operating the same. The memory device includes a memory block including pages configured of a plurality of memory cells, a peripheral circuit configured to perform a read operation on a selected page among the pages, and a control logic configured to control the peripheral circuit to perform a first read operation on a first logical page and then perform a second read operation on a second logical page, among the first and second logical pages in the selected page, during the read operation. The control logic is configured to control the peripheral circuit to adjust a channel initialization time according to the first logical page after the first read operation is ended, and perform a channel initialization operation during the channel initialization time during the second read operation.

The present application provides a semiconductor device and a method for manufacturing the same. In the semiconductor device, an isolation structure in a substrate includes a first isolation structure and a plurality of second isolation structures connected to the first isolation structure, the plurality of second isolation structures being on the same side of the first isolation structure and extending into the substrate in a first direction; a gate structure is above the substrate on a side of the second isolation structure away from the first isolation structure and extends in the first direction to cover the plurality of second isolation structures and part of the first isolation structure; a source region is in the substrate on a side of the gate structure away from the isolation structure; and a drain region is in the substrate on a side of the isolation structure away from the gate structure. This reduces the edge electric field of the isolation structure and improves the hot carrier injection failure problem of the semiconductor device. The method for manufacturing the semiconductor device provided by the present application can be used to manufacture the semiconductor device described above.

This invention relates to the field of integrated circuit technology, and discloses a switching circuit and method for suppressing the hot carrier injection effect. The switching circuit includes a first switching transistor and a second switching transistor array. The second switching transistor array includes multiple switching transistors connected in parallel. The first switching transistor is connected in parallel with the second switching transistor array, and the conduction area of ​​the first switching transistor is smaller than the total conduction area of ​​the second switching transistor array. The first switching transistor is configured to turn on before the second switching transistor array. This invention can effectively suppress the hot carrier injection effect while achieving high current transmission.

Various embodiments provide apparatuses, systems, and methods for a hot carrier injection (HCI) physically unclonable function (PUF) circuit. For example, described herein is a HCI PUF circuit with n-type metal oxide semiconductor (NMOS) transistors and a Pi-shaped reset structure. Other embodiments may be described and claimed.

The embodiment of the present application provides a test circuit, a method for testing the hot carrier injection effect, and a test device. The device includes: N resistor units, which are connected in series to form a resistor string structure; a current detection unit for detecting the current flowing through the resistor string structure; a first electrode, a second electrode, a switching device, and N test electrodes, wherein the first end of the resistor string structure is electrically connected to the power supply end, the second end of the resistor string structure is electrically connected to the first electrode and the first end of the switching device respectively, and the second end of the switching device is grounded; the second ends of the N resistor units are used to be electrically connected to the gates of the N MOS devices to be tested in a one-to-one correspondence; the N test electrodes are used to be electrically connected to the drains of the N MOS devices to be tested in a one-to-one correspondence. This test circuit can measure the HCI of different gate voltages or drain voltages of multiple MOS devices to be tested at one time, thereby improving the test efficiency.

Devices including an arrangement of multiple of physically unclonable function (PUF) cells organized to generate a bit pattern, and wherein the PUF cells each includes multiple inverting stages, each inverting stage configured to enable a short circuit between outputs of a pair of inverters to enable accelerated aging of one of the inverters.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device, which is characterized in that a substrate internally comprises a first well region and a second well region with different doping types, and the first well region and the second well region have an overlapped region; the channel region stretches across the first well region and the second well region, the channel region is overlapped with the first well region, the channel region is overlapped with the second well region, the overlapping length of the channel region and the first well region is reduced, and the overlapping length of the channel region and the second well region is increased. The overlapping length of the channel region and the first well region is smaller than the overlapping length of the channel region and the second well region; the gate is over the channel region. By adjusting the design sizes of the overlapping area of the channel region and the first well region and the overlapping area of the channel region and the second well region of the LDMOS device, the overlapping length of the channel region and the first well region is reduced, the overlapping length of the channel region and the second well region is increased, the electric field of the channel region of the LDMOS device is obviously weakened, the injection life of hot carriers is prolonged, and the performance of the LDMOS device is improved. And the reliability of the LDMOS device is improved.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with a variable-angle funnel-shaped field oxide structure. The STI side wall angle is regulated and controlled in a segmented mode, an inclination angle structure is introduced to the position close to a high-voltage drift region, a gradually-changed field oxygen boundary is formed, transverse expansion and gradient slow release of an electric field at the edge of the drift region can be achieved, the electric field concentration effect at the STI corner is remarkably weakened, and the vertical boundary of the lower portion maintains the structural stability; and stress concentration caused by deep groove etching is avoided. Finally, compared with a traditional STI LDMOS structure with a single side wall angle, breakdown voltage (BV) can be partially improved, on resistance (Ron) of a drift region can be remarkably reduced, collision ionization rate on a drain electrode-field oxygen interface is reduced, a hot carrier injection (HCI) effect is remarkably inhibited, and the service life of a device is prolonged.

The invention discloses an SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory array structure which comprises a plurality of memory units which are arranged in an array and have the same structure, each memory unit is composed of a selection tube, a first memory tube and a second memory tube, the first memory tube and the second memory tube are arranged on two sides of the selection tube, and the two memory tubes are used for respectively storing data; grid electrodes of the selection tubes of each row of storage units are connected with corresponding word lines; the grid electrode of the first storage tube of each row of storage units is connected with a corresponding first storage tube word line; the grid electrode of the second storage tube of each row of storage units is connected with a corresponding second storage tube word line; and one bit line between adjacent storage unit columns is alternately connected with different storage tubes of two adjacent storage units in the same row on the two sides of the bit line respectively. According to the SONOS memory array structure provided by the invention, the erasing speed can be improved based on hot carrier injection, and the array area can be reduced.

This invention relates to an LDMOS device and its manufacturing method. The LDMOS device includes: a source region; a drain region; a drift region; a field oxide layer; a gate extending from near the edge of the source region onto the field oxide layer; a first low-doped region located directly below the field oxide layer on the side near the source region; and a second low-doped region located directly below the gate on the side near the drain region. The region between the first and second low-doped regions has a first conductivity type. The first and second low-doped regions have the first conductivity type, and their doping concentration is lower than that of the region between them; or the first and second low-doped regions have a second conductivity type. This invention introduces low-doped or inverted regions into areas of concentrated electric field, making the potential line distribution sparser in these two areas, reducing the collisional ionization rate, and mitigating the hot carrier injection effect in these areas.

Hot carrier injection (HCI) may be used to provide various improvements for one-time programmable (OTP) read-only memory (ROM) or physical unclonable function (PUF) circuits. HCI may be used to write a memory bit (e.g., logical 0 or 1), which may be used in OTP ROM. HCI may be used to provide improved programmable ROM (PROM) memory devices, such as to facilitate programming or to increase sensing window. HCI may also be used to write a memory bit in a PUF circuit. HCI may provide a cross-foundry portable PUF circuit that has an associated adjustable bit error rate (BER), which may be used to secure root key generation, or may be used to provide a unique identification (ID) for fuse replacement.

A circuit for driving digital-to-analog converter (DAC) comprising a serializer configured to combine multiple signals to one input signal to drive a forward inverter coupled to a first node with a first impedance in serial configuration and a first capacitance in shunt configuration. The circuit includes a chain of inverters coupled in series to transfer the input signal from the first node to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter between the third node and the first node to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node. A second feedback inverter can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

This invention discloses a semiconductor data testing anomaly early warning method and system, relating to the field of integrated circuit testing technology. The method includes: performing a stepped voltage test on the chip under test by calibrating a purely electronic current signal, while simultaneously monitoring changes in drain current, substrate current increments, and voltage states; calculating hot carrier injection efficiency parameters based on drain current changes and substrate current increments, and combining these parameters with the voltage states to generate photon detection commands; driving an InGaAs avalanche photodiode array to collect photon pulse counts based on the photon detection commands, and calculating a chip damage risk index based on the hot carrier injection efficiency parameters and photon pulse counts to generate a risk assessment report. This invention calculates the chip damage risk index using hot carrier injection efficiency parameters and photon pulse counts, achieving dynamic damage quantification analysis by integrating electrical parameters and optical data, thus achieving holographic perception and early risk identification of chip anomalies.

The present disclosure provides a write method for a flash memory cell. The flash memory cell includes a storage transistor and a select transistor connected in series. The write method according to the present disclosure includes applying write voltages to electrodes of the flash memory cell and gate electrodes of the transistors, wherein the write method applies a lower write voltage to a gate electrode of a storage transistor to be written in a first write step and a higher write voltage to the gate electrode of the storage transistor to be written in a second write step based on a channel hot carrier injection mechanism. The write method for the flash memory cell according to the present disclosure adopts a write step of a double channel hot carrier injection mechanism, which can reduce the impact of trap charge mismatch effect (TCME) compared to existing write methods, thereby improving durability and retention reliability.

A P-type Extended Drain MOS (PEDMOS) FETs capable of high speed operation and the capability to withstand relatively high drain voltages. The PEDMOS device includes an active layer (preferably <110> orientated Si) having a P+ SiGe source region, a first P− Si drift region, a second P− SiGe drift region, and a P+ SiGe drain region. The SiGe regions exert compression on the N-type Si channel, improving hole mobility within the PEDMOS device and resulting in low leakage currents at active layer edges, low channel resistance, and good HCI and GIDL characteristics. Forming the SiGe regions may include etching voids in the Si active layer and depositing SiGe within the voids; implanting Ge into defined regions of the Si active layer; or etching partial voids in the Si active layer, depositing SiGe within the partial voids in contact with Si, and diffusing the Ge into the Si.

The invention relates to an asymmetric fin heat conduction enhanced GaN HEMT device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices, the asymmetric fin heat conduction enhanced GaN HEMT device comprises a substrate, a buffer layer, a channel layer, a barrier layer, a grid electrode, a source electrode and a drain electrode, a composite passivation layer is formed by embedding high heat conduction heat dissipation fins in a drain electrode side passivation layer, a heat conduction side wall is introduced, and a high heat conduction material and a composite structure are utilized to form a high heat conduction enhanced GaN HEMT device. The heat conduction bottleneck of a surface medium is effectively broken, the surface heat dissipation area is increased, a multi-dimensional heat dissipation path is constructed, the peak temperature in the device is remarkably reduced, parameter degradation and hot carrier injection damage under electrothermal coupling cooperation are relieved from the source, and therefore the overall electrical performance and reliability of the device are improved.

The utility model provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which is characterized in that a source end lightly doped region and a drain end lightly doped region are asymmetrically distributed relative to a grid electrode, and the ratio of the width of the source end lightly doped region extending to the lower part of the grid electrode to the width of the drain end lightly doped region extending to the lower part of the grid electrode is 1: 1.5-1: 2. Therefore, by controlling the ratio of the asymmetrical distribution degrees of the lightly doped regions on the two sides of the grid electrode, the effective channel length of the device is not affected while the hot carrier injection (HCI) effect is improved, then it is guaranteed that electric leakage is not affected, and the performance of the device is improved.

Techniques and mechanisms for accessing memory arrays which are formed in a back end of line (BEOL) of an integrated circuit (IC) die. In an embodiment, a differential sense amplifier of the IC die is coupled to a first array and a second array via a first bit line and a second bit line, respectively. The first bit line and the second bit line extend from a first level of BEOL memory arrays, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first array, wherein the differential sense amplifier is in a footprint region for the first memory array. In another embodiment, a word line driver circuit comprises a two stage charger-discharger circuit which mitigates hot carrier injection.

A method for forming a semiconductor structure. The method comprises: providing a substrate; forming a gate structure on the substrate; forming a threshold-voltage-adjustment region in the substrate, wherein the threshold-voltage-adjustment region has threshold-voltage-adjusting ions; and forming a lightly doped drain region in the substrate, wherein the lightly doped drain region has light-doping ions. Threshold-voltage-adjusting ions are implanted after a gate structure is formed, such that the threshold-voltage-adjusting ions have a deeper implantation depth outside a channel region. The implantation of light-doping ions is performed after the implantation of the threshold-voltage-adjusting ions, and since the threshold-voltage-adjusting ions have a deeper implantation depth outside the channel region, the formation of deeper and more hierarchical junction depths in source-drain regions by the implanted light-doping ions is thus facilitated, thereby alleviating the hot carrier injection effect. During such procedure, it is not necessary to increase the implantation energy and annealing heat for the light-doping ions, thereby effectively reducing damage to the structure and performance of a device. Moreover, it is also not necessary to perform non-self-aligned masked ion implantation, thereby effectively simplifying the process.

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a first well disposed in the substrate, a second well disposed in the substrate and adjacent to the first well, an isolation structure disposed in the first well, and a gate structure disposed on the substrate and including a first gate portion and a second gate portion, wherein the first gate portion overlaps the first well and the second well, and an opening between the first gate portion and the second gate portion exposes a portion of the isolation structure. The semiconductor structure can be effectively reduced in damage caused by hot carrier injection testing, and the reliability of the semiconductor structure can be improved.

The present application relates to the field of MOS semiconductor technology, and discloses a silicon carbide (SiC) MOSFET device with improved gate oxide reliability, which is composed of a plurality of mutually juxtaposed MOS cells, the MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source, the semiconductor epitaxial layer comprising an N substrate layer, an N diffusion layer, a P+ layer, a P well layer and an N well layer, a high-K dielectric being provided between the gate and the P well layer, wherein one side of the high-K dielectric and between the source and the N well layer is provided with doped polysilicon; the high-K dielectric is one of hafnium dioxide, aluminum oxide or zirconium dioxide. Through the double-layer stacked structure of the high-K dielectric and the SiO2 gate oxide layer, the high dielectric constant of the high-K material is used to share the gate voltage, the electric field intensity of the SiO2 interface is significantly reduced, the gate leakage current is reduced by two orders of magnitude, and the degradation of the gate oxide layer caused by hot carrier injection is fundamentally inhibited.

The application discloses a MOS device with extended drain and a manufacturing method thereof. The MOS device comprises a substrate, an epitaxial layer, a gate, the epitaxial layer is arranged on the substrate and has the same conductive type as the substrate, the epitaxial layer is formed with a well region, a channel doped region, an extended drain region, a drain region and a source region; the gate is formed on the epitaxial layer; the channel doped region is located below the gate, and the conductive type of the channel doped region is opposite to that of the epitaxial layer; the well region is located below the channel doped region and is in contact with the extended drain region, and the conductive type of the well region is the same as that of the epitaxial layer; and the conductive type of the source region is opposite to that of the substrate. The application reduces the thermal process of processing, simplifies the process, improves the device consistency, suppresses the hot carrier injection effect of the device, improves the doping concentration of the extended drain region, further reduces the on-resistance of the device, and improves the device performance.