Method and structures for highly efficient hot carrier injection programming for non-volatile memories

Abstract

A method programs a memory cell by controlling a reverse bias voltage across the PN junction between a source electrode of a MOSFET in the memory cell and the substrate, and pulling back the pinch-off point of the inversion region toward the source electrode, thereby increasing the programming efficiency of the memory cell. The method applies the main positive supply voltage Vcc to, the drain electrode of the memory cell from the chip main voltage supply, rather than the conventional method of using a higher voltage than Vcc. To optimize the programming condition, the source voltage and the substrate voltage are adjusted to achieve the maximum threshold voltage shifts under the same applied gate voltage pulse condition (i.e. using the gate pulse with the same voltage amplitude and duration regardless of the source voltage and the substrate voltage). The substrate voltage to the drain voltage can not exceed the avalanche multiplication junction breakdown for a small programming current during the bias voltage adjustment.

Description

FIELD OF INVENTION[0001]This invention relates to methods and structures for programming Non-Volatile Memory (NVM) cells using highly efficient Hot Carrier Injection (HCI).BACKGROUND OF INVENTION[0002]As shown in FIG. 1, metal oxide semiconductor field effect transistor 10 (MOSFET) includes a source 13 and a drain 14 (connected respectively to source electrode 13a and drain electrode 14a) each with an impurity type opposite to the impurity type of the substrate 15. The source 13 and drain 14 are separated by a channel region in the substrate 15 underlying a control gate 11 formed over a dielectric layer 12 on top of the silicon substrate 15. When the voltage applied to the gate electrode 11a electrically connected to control gate 11 exceeds the threshold voltage of the MOSFET 10, the channel region in the substrate 15 between the source 13 and the drain 14 and just below the dielectric 12 under the control gate 11 of the MOSFET device 10 is inverted to the same conductivity type as ...

AI Technical Summary

Benefits of technology

This approach significantly reduces programming current, simplifies bitline design, and enables efficient parallel programming of more NVM cells with improved uniformity, achieving faster and more reliable threshold voltage shifts with reduced power consumption.

Problems solved by technology

The programming efficiency is thus very low.

It becomes very challenging for charge pump circuit design to support a high current load while maintaining a constant higher drain 14 voltage bias during programming MOSFET 10 in an NVM cell.

For parallel programming an array of NVM cells, the programming uniformity can also be compromised from the high voltage supply dropout due to high current load.

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