767results about "Semiconductor operation lifetime testing" patented technology

The invention discloses a power semiconductor device aging on-line diagnosis method, which relates to the field of power electronics, and comprises the following steps: integrating an intelligent sensor and an aging test circuit, and establishing a multi-physics field coupling simulation model; based on the multi-physics field coupling simulation model, evaluating the aging state of the current device to obtain the health index of the device; based on the multi-dimensional data matrix, constructing an anomaly detection model, and outputting an anomaly detection result; predicting the failure probability and the remaining service life of the semiconductor device according to an abnormal detection result; generating a maintenance suggestion based on the predicted failure probability and remaining useful life of the semiconductor device; according to the method, the maintenance suggestion is generated according to the prediction result, the user is guided to take preventive maintenance measures in time, the accuracy of aging state evaluation is improved, the timeliness of fault early warning is enhanced, and economic losses and technical risks caused by sudden faults are reduced.

The invention relates to the technical field of semiconductor device testing, in particular to a SiC MOSFET power cycle testing method which comprises the following steps: S1, building a composite environment testing platform, configuring dynamic testing parameters, automatically calculating a physical boundary and collecting sensor data in real time; s2, establishing a finite element simulation model based on the physical boundary and sensor data, and outputting optimized dynamic test parameters and a simulated stress distribution diagram; s3, synchronously applying composite stress according to the dynamic test parameters and the stress distribution diagram, and collecting multi-dimensional test data in real time; when the system is used, through dynamic boundary calculation and real-time data acquisition, the intelligent degree and reliability of the test are improved, the test period is shortened, the failure prediction accuracy is improved, the system is suitable for reliability evaluation of SiC MOSFET devices in the fields of new energy, aerospace and the like, a large number of physical tests are avoided through virtual simulation, and the reliability of the SiC MOSFET devices is improved. And reduction of device loss and resource waste is facilitated.

The invention discloses a SiC MOSFET gate oxide layer degradation monitoring method based on turn-off oscillation, and the method comprises the steps: measuring the drain-source current change rate diDS / dt when a SiC MOSFET is turned off through the source stray inductance voltage vcir, and carrying out the measurement of the gate oxide layer degradation of the SiC MOSFET based on the offset of the negative temperature sensitivity of the threshold voltage VTH in the diDS / dt and the positive temperature sensitivity of the electron mobility mu. Zero temperature sensitivity of a source stray inductance voltage negative peak value vcircmin is realized by adjusting a driving resistor RG and a negative voltage VEE during turn-off, and the gate oxide layer degradation degree of the SiC MOSFET is monitored under a selected monitoring driving resistor RGM and a turn-off gate voltage VEEM. The monitoring method is high in universality and has a good monitoring effect on degradation of gate oxide layers of SiC MOSFETs of different models; the temperature influence is extremely small, so that the device can work in an environment with large temperature fluctuation; a pin of a monitored device does not need to be used as a measurement interface, so that the system invasiveness is small; the parameter measurement methods are many and mature; and the method has great online application potential.

The invention discloses a nanosecond-order delay transistor reliability test system and method, and belongs to the technical field of transistor test. The test system is divided into three parts, namely a voltage stress value and stress duration control module, a current control module and a hard switch transient and on-resistance test module. The drain voltage stresses are respectively used for controlling the drain voltage stress value and the drain voltage stress duration of the transistor to be tested; the current during hard switch testing is determined; and the conduction time is long. The test system processes signals through a hardware circuit, can convert an input single-path pulse signal into two paths of inverted pulse signals with dead time, and improves the safety of the test system. The voltage stress duration, the current and the conduction duration of the drain electrode of the transistor to be tested can be flexibly regulated and controlled only by inputting a pulse signal to each of the three modules. Simulation and experiments prove that the measurement delay of switching to the test state after the drain electrode voltage stress is ended is nanosecond magnitude, and the method has important significance for monitoring performance degradation after the transistor drain electrode voltage stress is monitored in real time.

Lateral III-N devices such as AlGaN / GaN HEMTs can have structures which serve to improve performance and reduce current degradation. The III-N device can include a conductive substrate and a III-N material structure that includes a III-N buffer layer, a III-N channel layer and a III-N barrier layer where a compositional difference induces a 2DEG channel therein. The first portion is in ohmic contact with the 2DEG channel and the second portion extends over a top surface of the III-N barrier layer and is in direct contact with the top surface of the III-N barrier layer. The device further includes a drain-to-substrate pinch-off voltage and a maximum rated drain-to-source operating voltage which is greater than the drain-to-substrate pinch-off voltage, and the 2DEG channel is fully depleted of charge below the second portion of the drain electrode when the III-N device is biased at or above the maximum rated drain-to-source operating voltage.

The present disclosure concerns a method for measuring a degradation of thermal characteristics of a power module comprising sequences of: - injecting current pulses (Pinj), having a voltage-clamped constant amplitude (Iinj), between an emitter and a gate of a power semiconductor of such power module, a duration of said voltage-clamped constant amplitude (Iinj) current pulses (Pinj) being modulated periodically with a modulation frequency (Fmod), said current pulses causing losses modulated with said modulation frequency (Fmod), - measuring a parameter (k Tj) dependent of a junction temperature (Tj) of such power semiconductor at the beginning of said current pulses, - measuring a phase shift (Δφ) between said modulation frequency (Fmod) and said parameter (k·Tj), said phase shift (Δφ) providing a health indicator for the power module.

The invention relates to the technical field of transistor detection, in particular to a quick test method and system for an MOSFET device. The method comprises the following steps: acquiring and integrating multi-source parallel data of the MOSFET device to obtain real-time I-V characteristic data of the device; performing MOSFET device performance prediction based on the real-time device I-V characteristic data to obtain MOSFET device performance prediction data; screening according to the performance prediction data of the MOSFET device to obtain performance data of a primarily screened qualified device; performing adjustment based on the performance data of the preliminarily screened qualified device to obtain an MOSFET device test scheme; acquiring real-time test data of the MOSFET device, and screening qualified devices to obtain performance data of re-screened qualified devices; and performing device test summarization based on the performance data of the primarily screened qualified device and the performance data of the secondarily screened qualified device to obtain an MOSFET device test report. According to the invention, the test period can be shortened.

The present application provides a method and system for predicting the remaining service life of an IGBT device, comprising: simulating an IGBT device power cycle aging experiment, collecting conduction voltage drop historical data on the basis of the experiment, and respectively obtaining a model parameter empirical value and a model parameter estimated value on the basis of the conduction voltage drop historical data; constructing a first state weight on the basis of the current operation state, and performing smooth adjustment on the model parameter estimated value on the basis of the model parameter empirical value and the first state weight to obtain a parameter correction result; and establishing a state transition equation on the basis of the parameter correction result, and predicting the remaining service life of an IGBT device on the basis of the state transition equation. Use of the present application can improve the accuracy of prediction of the remaining service life of the IGBT device.

The invention relates to the technical field of semiconductor device process reliability testing, and discloses a method, a device and equipment for predicting the time-dependent breakdown life of an insulating dielectric layer, and a medium, and the method comprises the steps: carrying out the ramp voltage testing of the insulating dielectric layer in a plurality of to-be-predicted devices; determining the breakdown electric field intensity of each to-be-predicted device according to the ramp voltage test result, the nominal insulation dielectric layer thickness and the specified voltage; determining the TDDB life of each insulating dielectric layer according to an electric field acceleration model corresponding to the TDDB and the breakdown electric field intensity of each to-be-predicted device; constants in the electric field acceleration model are determined according to TDDB test results obtained by carrying out TDDB tests on historical devices. According to the scheme disclosed by the invention, the slope voltage test is performed on the to-be-predicted device and the TDDB test result of the historical device is combined to predict the TDDB life of the insulating dielectric layer, so that the TDDB life prediction efficiency of the insulating dielectric layer is improved, and the TDDB life evaluation is quickly and effectively performed.

The invention discloses a WOA-BP-based SiC MOSFET life prediction method and device and a storage medium, and relates to the technical field of reliability prediction of power electronic equipment. The method comprises the following steps: selecting drain-source electrode voltage as an aging characteristic parameter of the SiC MOSFET, and acquiring voltage data in real time in an aging test process by using a sensor; the collected voltage data are preprocessed, abnormal values are eliminated, missing values are supplemented, and the data are smoothed; parameters of a back propagation neural network BP are optimized through a whale optimization algorithm WOA, and a WOA-BP prediction model is constructed; and initializing a WOA-BP model and inputting voltage data for training, and establishing a mapping relation between the service life of the SiC MOSFET and the voltage to realize prediction of the residual service life of the SiC MOSFET. The SiC MOSFET service life prediction model has the advantages of being high in adaptability, low in calculation complexity, high in prediction precision and the like, can be widely applied to the fields of the semiconductor industry, new energy automobiles, industrial automation and the like, and provides powerful support for health management and maintenance of equipment.

The invention discloses an IGBT residual life prediction method based on variational Bayes and a mixed Wiener process, and belongs to the technical field of IGBT residual life prediction, and the method comprises the following steps: S1, giving out the definition of the mixed Wiener process, and building a degradation model to describe the degradation track of an IGBT; s2, performing off-line parameter estimation based on a variational Bayesian algorithm by using a prior sample; s3, selecting an optimal model in the degradation models according to an automatic correlation determination method; s4, selecting a prior sample which is most similar to the test sample at the current moment; s5, updating the mean value and variance of the weight vector of the test sample on line; and S6, solving a probability density function of the residual life of the mixed Wiener process in the sense of the first arrival time, and estimating the residual life value of the IGBT at each moment. According to the IGBT residual life prediction method based on the variational Bayes and the mixed Wiener process, the degradation mode can be automatically determined, the fitting precision of an IGBT degradation track is improved, the requirement for specialty is reduced, and the universality of the model is improved.

Disclosed is a power metal-oxide-semiconductor field-effect transistor (MOSFET) diagnostic and lifetime estimation system and method, including the steps of: acquiring degradation data by conducting a degradation test; measuring potential failure precursors to provide early warning of failure; inspecting and diagnosing health condition of internal structure of the power MOSFET device using thermal transient measurement and scanning acoustic microscopy (SAM) images; repeating power cycling test and the measurements of potential failure precursors until the precursors reach a corresponding failure threshold; and estimating remaining lifetime of the power MOSFET device using an artificial intelligence (AI) algorithm.

The invention discloses an electronic component quality control method and system, and relates to the technical field of transistor performance quality control. The quality control method for the electronic component comprises the following steps: evaluating transistor switch abnormity; switching speed delay regulation and control; and evaluating the input signal response control accuracy. Transistor switching abnormality evaluation is carried out in the transistor switching process, then whether switching speed delay optimization is carried out or not is judged based on a quantization result, if switching speed delay optimization is carried out, switching speed delay regulation and control are carried out, and if switching speed delay optimization is not carried out, input signal response control accuracy evaluation is carried out. And finally, judging whether to carry out input signal response control optimization or not based on a quantification result of the input signal response control accuracy evaluation, thereby achieving the effect of improving the response control sufficiency of the transistor on the input signal in the switching process. The problem that the switch response difference is not fully considered in the response control process of a transistor to an input signal in the prior art is solved.

The invention relates to the technical field of photoelectric detection, in particular to a laser diode state monitoring method and system based on multi-parameter fusion, and the method comprises the steps: carrying out the laying and collection of a plurality of parameters based on the working condition of a laser diode, including current, temperature and optical feedback signals, and carrying out the dynamic fusion to construct a damage index; establishing a grading early warning mechanism, correspondingly setting a judgment threshold value, and triggering early warning in combination with the damage index; the temperature is detected periodically, parameter drift influenced by the temperature is corrected based on a damage index, and state monitoring of the laser diode is achieved; by dynamically fusing a plurality of parameters of current, temperature and optical feedback signals, a multi-dimensional damage index is established, so that the influence of a plurality of indexes on laser diode damage is synthesized, and the recognition rate of early damage is improved; and establishing a grading early warning mechanism from a slight state to a serious state, making a corresponding early warning response, and advancing fault recognition of the laser diode to a reversible stage.

The invention discloses a method for preventing needle burning during testing of breakdown voltage of a discrete device. According to the method, in a test loop comprising a probe card and a test source, a voltage-withstanding module is connected in series between the probe card and a low-potential end of the test source. The voltage-withstanding module comprises a detection resistor Rx and a voltage-withstanding switching device connected with the detection resistor Rx in parallel. When the test current I is applied, if the current is increased abnormally due to poor contact and the like, and the voltage drop on the detection resistor Rx is greater than or equal to the starting voltage VT of the voltage-withstanding switching device, the voltage-withstanding switching device is switched on, the test current I is shunted, and the current flowing through the probe card is reduced, so that the probe is prevented from being burnt. The breakdown voltage of the tested device is calculated by measuring the total voltage V at the two ends of the test source and subtracting the voltage drop (I * Rx) on the detection resistor Rx, and the test accuracy is ensured. The method can effectively protect the probe card and improve the test reliability and efficiency.

The present disclosure concerns a method for measuring a degradation of thermal characteristics of a power module comprising sequences of: - injecting current pulses (Pinj), having a voltage-clamped constant amplitude (IInj), between an emitter and a gate of a power semiconductor of such power module, a duration of said voltage-clamped constant amplitude (Iinj) current pulses (Pinj) being modulated periodically with a modulation frequency (Fmod), said current pulses causing losses modulated with said modulation frequency (Fmod), - measuring a parameter (k.Tj) dependent of a junction temperature (Tj) of such power semiconductor at the beginning of said current pulses, - measuring a phase shift (Δφ) between said modulation frequency (Fmod) and said parameter (k.Tj), said phase shift (Δφ) providing a health indicator for the power module.　

The invention discloses a service life evaluation method and system for a power semiconductor device, and belongs to the technical field of semiconductors, and the method specifically comprises the steps: obtaining a to-be-evaluated device, carrying out the power cycle test under different single junction temperature fluctuations, and recording the failure data, including the cycle index, the junction temperature fluctuation range and the electrical performance parameters; thirdly, performing statistical analysis on failure data, calculating a junction temperature fluctuation amplitude correlation fatigue factor and a power cycle frequency accumulation fatigue factor, and combining the junction temperature fluctuation mode factor to obtain a composite fatigue factor; calculating an accumulated fatigue factor according to the composite fatigue factor and the dynamic weight by adopting a weighted accumulation method; inputting the accumulated fatigue factor into a pre-constructed service life evaluation model, and calculating the service life of the device; when the accumulated fatigue factor exceeds a threshold value, triggering an early warning mechanism, outputting early warning information, and prompting that the service life of the device is about to expire or expired; accurate evaluation and early warning of the service life of the power semiconductor device are realized.

The present disclosure provides an automated repair of LED substrates system in which an automated repair inspection module is used to determine the quality of incoming processing material an automated repair process module is used to process the processing material, an automated repair post-process module is used to inspect the resultant process material for acceptability, and an automated repair historical module is used to analyze the post process results of the most recent process, against all historical data to find enhanced process changes in the automated repair process module, and an automated repair integration module to update the automated repair process module based upon the results of the automated repair historical module.

The invention provides a reliability test system and method, and relates to the field of power devices, the reliability test system can carry out a high-temperature gate bias test and a high-temperature reverse bias test, multiple test modes are realized in one reliability test system, and the test efficiency is improved. Moreover, the reliability test system can apply an alternating signal to the to-be-tested device, thereby truly restoring an actual application scene, and enabling the reliability test system provided by the invention to accurately test the reliability of the power device. After the stress is applied, detection can be carried out immediately, and the relaxation effect of the power device is prevented from influencing the test result. Besides, in the high-temperature gate offset test, the pulse frequency or duty ratio of the electric stress pulse signal can be controlled through the half-bridge circuit, the parameters of the pulse signal can be flexibly changed by the reliability test system for different power devices, and the test applicability is improved.

The invention discloses a WOA-LSTM-based SiC MOSFET life prediction method and device, and a storage medium, and relates to the technical field of reliability prediction of power electronic equipment. The method comprises the following steps: selecting drain-source electrode voltage as an aging characteristic parameter of the SiC MOSFET, and acquiring voltage data in real time in an aging test process by using a sensor; the collected voltage data are preprocessed, abnormal values are eliminated, missing values are supplemented, and the data are smoothed; the method comprises the following steps: optimizing parameters of a long short-term memory network LSTM through a whale optimization algorithm WOA, and constructing a WOA-LSTM prediction model; and initializing a WOA-LSTM model, inputting voltage data for training, and establishing a mapping relation between the service life of the SiC MOSFET and the voltage to realize prediction of the residual service life of the SiC MOSFET. The SiC MOSFET service life prediction model has the advantages of being high in adaptability, low in calculation complexity, high in prediction precision and the like, can be widely applied to the fields of the semiconductor industry, new energy automobiles, industrial automation and the like, and provides powerful support for health management and maintenance of equipment.

The invention provides a fault detection method and system for a gallium nitride power device, and relates to the technical field of fault detection, and the method comprises the steps: determining the safe operation parameters of the gallium nitride power device under a preset working condition according to the rated electrical parameters, chip structure parameters and packaging characteristics of the gallium nitride power device; extracting state response characteristics of the gallium nitride power device under a preset working condition; constructing a fault evidence matrix of the gallium nitride power device under a preset working condition based on the safe operation parameters and the state response characteristics; and performing fault state evaluation on the gallium nitride power device according to the fault evidence matrix to obtain a fault state factor of the gallium nitride power device, and further determining the fault probability of grid degradation of the gallium nitride power device based on the fault state factor. According to the scheme, the operation safety and the state response of the gallium nitride power device under the high-frequency switching working condition can be comprehensively analyzed, so that the evaluation accuracy of the device fault state is improved.

The invention discloses a power electronic device fault early warning method based on multi-physics field coupling, and the method comprises the steps: (1) collecting aging data of a power electronic device under the condition of electric field and thermal field coupling, and dividing the aging data into a source domain data set and a target domain data set; (2) establishing a power electronic device aging parameter screening method, selecting a parameter which can best represent an aging rule as an aging precursor, and converting discrete voltage and current signals into time sequence signals which can be accepted by a neural network; (3) compressing the time sequence signal set into sliding window graph nodes, calculating a distance relationship between the graph nodes, and obtaining a graph matrix containing data structure information; (4) building a space-time fusion fault predictor, wherein the space-time fusion fault predictor comprises a feature extractor, a time sequence predictor and a domain discriminator; and (5) a weak supervision adversarial learning strategy is adopted, a small amount of target domain label data participates in the model training process, and the source domain prediction loss, the target domain prediction loss and the discrimination loss are combined for training.

The invention relates to the technical field of semiconductor testing, in particular to a method and a system for testing avalanche tolerance of a semiconductor diode. The method comprises the following steps: in the process of peak voltage stimulation and recovery to a stable state, obtaining a thermal imaging image of a semiconductor diode, and determining a peak value region of local temperature; determining a heat dissipation insufficiency index according to the temperature change and the area of the peak region; determining a local overheating factor of the thermal imaging image in combination with the heat dissipation insufficiency index and the distances of all peak regions; determining the dissipation rate of the local overheating phenomenon of the diode according to the numerical change of the local overheating factors of all thermal imaging images on the time sequence; determining the possibility of thermal breakdown by combining the local overheating factor and the dissipation rate; and determining the avalanche tolerance according to the numerical change of all thermal breakdown possibilities of the diode at different peak voltages. The avalanche tolerance can be specifically analyzed according to the temperature change, so that the accuracy of the avalanche tolerance is higher.

The invention discloses a method for monitoring a packaging aging mode of a power module in real time and a related device, and belongs to the technical field of power electronic devices. According to the method, thermal network models corresponding to different packaging aging modes are established according to the structure of the power module, and frequency separation points corresponding to the different packaging aging modes are found; setting a test frequency, and collecting the conduction voltage drop of the power module and the load current of the inverter circuit; and analyzing the difference of the conduction voltage drop hysteretic curve according to the deviation or rotation of the conduction voltage drop hysteretic curve caused by different aging modes such as bonding wire falling, welding layer fatigue and heat dissipation system aging, and determining the packaging aging mode of the power module. By adopting the method, the packaging aging mode of the power module can be monitored in real time, aging reasons can be effectively distinguished, maintenance measures can be accurately taken, serious faults can be avoided, and the maintenance cost can be reduced; and meanwhile, the reliability and the stability of the whole system can be improved by monitoring and repairing the packaging aging problem in time.

The invention discloses a passive DHTRB test circuit, method and product with optimized performance. The test circuit comprises a power supply, a first test accompanying tube S1, a second test accompanying tube S2, a tested device DUT, a positive overshoot circuit and a negative overshoot circuit. The positive electrode of the power supply is connected to the input end of the positive electrode overshoot circuit, the output end of the positive electrode overshoot circuit is connected with the drain electrode of the first test accompanying tube S1, the source electrode of the first test accompanying tube S1 is connected with the second test accompanying tube S2 and the drain electrode of the tested device DUT, the source electrode of the second test accompanying tube S2 is connected with the input end of the negative electrode overshoot circuit, and the output end of the negative electrode overshoot circuit is connected with the source electrode of the tested device DUT and is connected to the negative electrode of the power supply; when the first test accompanying tube S1 is switched on and the second test accompanying tube S2 is switched off, the positive overshoot circuit outputs forward overshoot voltage to the outside; when the first test accompanying tube S1 is turned off and the second test accompanying tube S2 is turned on, the negative overshoot circuit outputs a reverse overshoot voltage to the outside. According to the invention, the dV / dt performance of the passive DHTRB test can be improved.

The embodiment of the invention discloses a semiconductor device service life evaluation method based on a power cycle test and related equipment, and the method comprises the steps: dividing semiconductor devices produced by the same factory in the same batch into two parts, and executing a second-level power cycle test on one part, a millisecond-level power cycle test is firstly executed on the other part, and then a second-level power cycle test is executed on the other part; establishing a first life model according to one test result, and establishing a second life model according to the other test result; and calculating a third life model corresponding to the millisecond power cycle test according to the first life model and the second life model, and performing life evaluation on the semiconductor device according to the third life model. By adopting the embodiment of the invention, the reliability assessment requirement of the power semiconductor device in the future can be met, and the aims of accelerating aging and meeting the actual working condition can be fulfilled, so that an important reference significance is provided for the research of the reliability test of the device and the assessment of the actual life.

The invention provides a silicon carbide chip performance evaluation method and evaluation system, and relates to the field of semiconductor testing. Nonlinear disturbance components are separated from dynamic response data; constructing a link transmission compensation function based on the nonlinear disturbance component, and determining dynamic characteristic parameters through the link transmission compensation function and the dynamic response data; performing multi-dimensional spectrum analysis on the dynamic characteristic parameters to obtain high-frequency performance parameters, and further performing thermal energy efficiency derivation on the silicon carbide chip according to the high-frequency performance parameters to obtain an energy efficiency trend and energy efficiency thermal coupling characteristics; performing multi-working-condition pulse excitation on the silicon carbide chip according to the deviation abnormal value to obtain a multi-dimensional compensation matrix; adaptive coupling compensation is carried out on the energy efficiency trend and the energy efficiency thermal coupling characteristics based on the multi-dimensional compensation matrix, then a performance evaluation data set of the silicon carbide chip is obtained, multi-dimensional adaptive coupling compensation based on abnormal value driving can be achieved, and the reliability of performance evaluation of the silicon carbide chip is improved.

The invention belongs to the technical field of semiconductor testing, and discloses a thermistor performance monitoring method and system based on a power module reliability test. The method comprises the following steps: configuring a pin connection structure electrically connected with a thermistor lead on a test burn-in board for a high-temperature, high-humidity and high-voltage reverse bias test; in the process of executing a high-temperature, high-humidity and high-voltage reverse bias test on the power module comprising the thermistor, a lead of the thermistor is electrically connected with a preset current detection loop through the pin connection structure, so that monitoring current flowing through the thermistor is received by the current detection loop, and thermistor performance monitoring is executed. According to the application, the problem that the self degradation risk of the thermistor cannot be monitored in real time in the H3TRB test process to cause a monitoring blind area can be solved, the whole-process monitoring of the performance fluctuation of the thermistor in the strong electric field and high humidity coupling environment is realized, and the integrity of the reliability evaluation of the power module and the safety of the test system are remarkably improved.

The invention provides semiconductor device thermal resistance measuring equipment, which is applied to the technical field of electrical variable measurement and comprises a case, a workbench fixed at the top of the case, a constant-temperature base arranged in the middle of the workbench, a rack arranged on one side of the workbench and erected above the constant-temperature base, a thermal resistance detector matched with the rack, and a temperature sensor arranged on the thermal resistance detector. The top of the rack is provided with a pressing mechanism which can press and abut against the semiconductor device to be tested towards the upper end face of the constant-temperature base. The middle part of the upper end surface of the constant-temperature base is provided with a flexible heat-conducting contact pad used for self-adapting to the shape of a semiconductor device to be tested, and the flexible heat-conducting contact pad is internally provided with a temperature control assembly; and an environment simulation mechanism is matched on the pressing mechanism. The thermal resistance testing device has a high-adaptability and high-precision thermal resistance testing structure, can adapt to semiconductor devices in various shapes for testing, can simulate the actual application environment of the semiconductor devices, can provide reliable data support for thermal management design of the semiconductor devices, and is good in overall use effect.

The invention discloses a wafer aging test system and a wafer aging test method. The wafer aging test system comprises wafer transportation equipment; the wafer loading and unloading equipment is arranged on one side of the wafer transportation equipment; the wafer aging test equipment comprises at least one wafer aging test device, and the at least one wafer aging test device is arranged on at least one side of the wafer transportation equipment; any one wafer aging test device is opposite to the wafer transportation equipment to form a first transportation channel; the wafer conveying device comprises a wafer taking and placing device, a second conveying channel is formed in the wafer conveying device, any first conveying channel is communicated with the second conveying channel, and the wafer taking and placing device bears wafers and is controlled to move in the second conveying channel or any first conveying channel so as to achieve feeding or discharging of the wafers. According to the embodiment of the invention, parallel testing of a plurality of test positions can be expanded, the testing efficiency is improved, and the flexibility and rationality of equipment layout are improved at the same time.