344results about "Semiconductor operation lifetime testing" patented technology

The present application provides a method and system for predicting the remaining service life of an IGBT device, comprising: simulating an IGBT device power cycle aging experiment, collecting conduction voltage drop historical data on the basis of the experiment, and respectively obtaining a model parameter empirical value and a model parameter estimated value on the basis of the conduction voltage drop historical data; constructing a first state weight on the basis of the current operation state, and performing smooth adjustment on the model parameter estimated value on the basis of the model parameter empirical value and the first state weight to obtain a parameter correction result; and establishing a state transition equation on the basis of the parameter correction result, and predicting the remaining service life of an IGBT device on the basis of the state transition equation. Use of the present application can improve the accuracy of prediction of the remaining service life of the IGBT device.

The invention relates to the technical field of photoelectric detection, in particular to a laser diode state monitoring method and system based on multi-parameter fusion, and the method comprises the steps: carrying out the laying and collection of a plurality of parameters based on the working condition of a laser diode, including current, temperature and optical feedback signals, and carrying out the dynamic fusion to construct a damage index; establishing a grading early warning mechanism, correspondingly setting a judgment threshold value, and triggering early warning in combination with the damage index; the temperature is detected periodically, parameter drift influenced by the temperature is corrected based on a damage index, and state monitoring of the laser diode is achieved; by dynamically fusing a plurality of parameters of current, temperature and optical feedback signals, a multi-dimensional damage index is established, so that the influence of a plurality of indexes on laser diode damage is synthesized, and the recognition rate of early damage is improved; and establishing a grading early warning mechanism from a slight state to a serious state, making a corresponding early warning response, and advancing fault recognition of the laser diode to a reversible stage.

The present disclosure provides an automated repair of LED substrates system in which an automated repair inspection module is used to determine the quality of incoming processing material an automated repair process module is used to process the processing material, an automated repair post-process module is used to inspect the resultant process material for acceptability, and an automated repair historical module is used to analyze the post process results of the most recent process, against all historical data to find enhanced process changes in the automated repair process module, and an automated repair integration module to update the automated repair process module based upon the results of the automated repair historical module.

The invention provides a fault detection method and system for a gallium nitride power device, and relates to the technical field of fault detection, and the method comprises the steps: determining the safe operation parameters of the gallium nitride power device under a preset working condition according to the rated electrical parameters, chip structure parameters and packaging characteristics of the gallium nitride power device; extracting state response characteristics of the gallium nitride power device under a preset working condition; constructing a fault evidence matrix of the gallium nitride power device under a preset working condition based on the safe operation parameters and the state response characteristics; and performing fault state evaluation on the gallium nitride power device according to the fault evidence matrix to obtain a fault state factor of the gallium nitride power device, and further determining the fault probability of grid degradation of the gallium nitride power device based on the fault state factor. According to the scheme, the operation safety and the state response of the gallium nitride power device under the high-frequency switching working condition can be comprehensively analyzed, so that the evaluation accuracy of the device fault state is improved.

The invention discloses a passive DHTRB test circuit, method and product with optimized performance. The test circuit comprises a power supply, a first test accompanying tube S1, a second test accompanying tube S2, a tested device DUT, a positive overshoot circuit and a negative overshoot circuit. The positive electrode of the power supply is connected to the input end of the positive electrode overshoot circuit, the output end of the positive electrode overshoot circuit is connected with the drain electrode of the first test accompanying tube S1, the source electrode of the first test accompanying tube S1 is connected with the second test accompanying tube S2 and the drain electrode of the tested device DUT, the source electrode of the second test accompanying tube S2 is connected with the input end of the negative electrode overshoot circuit, and the output end of the negative electrode overshoot circuit is connected with the source electrode of the tested device DUT and is connected to the negative electrode of the power supply; when the first test accompanying tube S1 is switched on and the second test accompanying tube S2 is switched off, the positive overshoot circuit outputs forward overshoot voltage to the outside; when the first test accompanying tube S1 is turned off and the second test accompanying tube S2 is turned on, the negative overshoot circuit outputs a reverse overshoot voltage to the outside. According to the invention, the dV / dt performance of the passive DHTRB test can be improved.

The embodiment of the invention discloses a semiconductor device service life evaluation method based on a power cycle test and related equipment, and the method comprises the steps: dividing semiconductor devices produced by the same factory in the same batch into two parts, and executing a second-level power cycle test on one part, a millisecond-level power cycle test is firstly executed on the other part, and then a second-level power cycle test is executed on the other part; establishing a first life model according to one test result, and establishing a second life model according to the other test result; and calculating a third life model corresponding to the millisecond power cycle test according to the first life model and the second life model, and performing life evaluation on the semiconductor device according to the third life model. By adopting the embodiment of the invention, the reliability assessment requirement of the power semiconductor device in the future can be met, and the aims of accelerating aging and meeting the actual working condition can be fulfilled, so that an important reference significance is provided for the research of the reliability test of the device and the assessment of the actual life.

The invention provides a silicon carbide chip performance evaluation method and evaluation system, and relates to the field of semiconductor testing. Nonlinear disturbance components are separated from dynamic response data; constructing a link transmission compensation function based on the nonlinear disturbance component, and determining dynamic characteristic parameters through the link transmission compensation function and the dynamic response data; performing multi-dimensional spectrum analysis on the dynamic characteristic parameters to obtain high-frequency performance parameters, and further performing thermal energy efficiency derivation on the silicon carbide chip according to the high-frequency performance parameters to obtain an energy efficiency trend and energy efficiency thermal coupling characteristics; performing multi-working-condition pulse excitation on the silicon carbide chip according to the deviation abnormal value to obtain a multi-dimensional compensation matrix; adaptive coupling compensation is carried out on the energy efficiency trend and the energy efficiency thermal coupling characteristics based on the multi-dimensional compensation matrix, then a performance evaluation data set of the silicon carbide chip is obtained, multi-dimensional adaptive coupling compensation based on abnormal value driving can be achieved, and the reliability of performance evaluation of the silicon carbide chip is improved.

The invention belongs to the technical field of semiconductor testing, and discloses a thermistor performance monitoring method and system based on a power module reliability test. The method comprises the following steps: configuring a pin connection structure electrically connected with a thermistor lead on a test burn-in board for a high-temperature, high-humidity and high-voltage reverse bias test; in the process of executing a high-temperature, high-humidity and high-voltage reverse bias test on the power module comprising the thermistor, a lead of the thermistor is electrically connected with a preset current detection loop through the pin connection structure, so that monitoring current flowing through the thermistor is received by the current detection loop, and thermistor performance monitoring is executed. According to the application, the problem that the self degradation risk of the thermistor cannot be monitored in real time in the H3TRB test process to cause a monitoring blind area can be solved, the whole-process monitoring of the performance fluctuation of the thermistor in the strong electric field and high humidity coupling environment is realized, and the integrity of the reliability evaluation of the power module and the safety of the test system are remarkably improved.

A first voltage supply is coupled to a first terminal of a test transistor. A first terminal of a probe circuit is coupled to the first terminal of the test transistor. A second terminal of the probe circuit is coupled to a second terminal of the test transistor. A third terminal of the probe circuit is coupled to a control terminal of the test transistor. A first terminal of the first resistor is coupled to the second terminal of the test transistor. A second terminal of the first resistor is coupled to a second voltage supply. A first input terminal of an amplifier is coupled to a third voltage supply. A second input terminal of an amplifier is coupled to the first terminal of the first resistor. An output terminal of an amplifier is coupled to the control terminal of the test transistor.

An electrical circuit arrangement includes a first diode and a semiconductor switching device electrically connected in series between a first node and a second node. The semiconductor switching device controls a switch current that includes a forward current through the first diode and a load current. A second diode and a calibration switching element are electrically connected in series between the first node and the second node. A voltage acquisition circuit obtains a voltage difference between a first voltage between the first node and the second node when the semiconductor switching device is on and the calibration switching element is off and a second voltage between the first node and the second node when the calibration switching element is on and the semiconductor switching device is off.

A semiconductor device apparatus is provided. The apparatus includes a packaged semiconductor device mounted on a substrate. The packaged semiconductor device includes a semiconductor die having a controller configured to obtain a measured capacitance of a sensor capacitor, an encapsulant encapsulating the semiconductor die, and a first plate of the sensor capacitor formed at a bottom side of the packaged semiconductor device. A second plate of the sensor capacitor is formed at a top side of the substrate.

The invention relates to the technical field of reliability testing of semiconductor power devices, and discloses a short-circuit robustness testing method and system based on grid stress degradation of a silicon carbide device, and the method comprises the steps of pre-testing short circuit, grid stress application and post-testing short circuit are continuously executed under the same physical connection by configuring a coupling testing time sequence. The control unit cooperates with the driving unit to generate a static positive and negative bias and dynamic switch stress mode, and cooperates with the power loop auxiliary switch action to simulate different short circuit faults. A dynamic and static index correlation model is established to quantitatively evaluate robustness by collecting transient waveforms and measuring static parameters and calculating short-circuit energy integral, threshold voltage and drift distance of on resistance. According to the invention, the in-situ test of the aging and short-circuit characteristics of the device is realized, the contact resistance change and the loop parasitic parameter difference caused by the repeated disassembly and assembly of the device in the traditional discrete test are eliminated, and the change of the two short-circuit waveforms completely corresponds to the internal degradation of the device caused by the grid stress.

The invention relates to the technical field of wafer testing, and discloses a wafer aging test system and method with a dynamic gate bias and reverse bias test function, and the system comprises a main control board, an industrial control computer, a high-voltage source, a source meter, a high-voltage switching board, a test switching board, and a needle card board. Dynamic high-temperature reverse bias and dynamic high-temperature gate bias tests can be added on the basis of static high-temperature reverse bias and reverse bias tests, higher requirements for SiC power device reliability testing equipment in the industry are met, stress borne by a chip under the actual working condition can be simulated, and the reliability of the SiC power device is improved. And the threshold voltage is monitored on line in real time while the pulse voltage is implemented, so that the reliability of the chip can be better evaluated.

The invention discloses a multichannel clock buffer test system and method, and relates to the technical field of semiconductor testing, and the method comprises the steps: calibrating the delay of an optical clock signal of each time-to-digital converter node to a preset precision threshold value; a standard clock signal is injected into the clock buffer input channel, and the clock buffer is driven to enter a working state; triggering a time-to-digital converter array by using the calibrated optical clock signal, collecting timestamp data of each output channel of a clock buffer, and generating an original time data set; inputting the original time data set into a double-mixing processor, and outputting a multi-channel skew parameter and a three-dimensional cloud picture; the multi-channel skew parameter is converted to a life indicator value for each output channel of the clock buffer based on the multi-channel skew parameter invoking a material model. According to the invention, the original time data set is subjected to two times of frequency mixing processing through the double frequency mixing processors, and phase detection and spectrum analysis are combined, so that high-precision extraction of the time deviation value of each output channel of the clock buffer is realized.

The invention discloses a component bidirectional aging tool based on aging equipment and a testing method. The component bidirectional aging tool comprises an aging plate; station needles are arranged on the aging plate and used for aging different types of devices and installing aging sockets, golden fingers are arranged at the two ends of the aging plate, polarity conversion slots are formed in the positions close to the golden fingers, and the polarity conversion slots are connected with the golden fingers; an electrode connecting line is arranged on the aging plate, one end of the electrode connecting line is connected with an aging test device electrode, and the other end of the electrode connecting line is correspondingly connected with the polarity conversion slot; and a polarity conversion plate is arranged on the polarity conversion slot. By applying the technical scheme of the invention, the problems of device appearance damage and low production efficiency caused by manual reversing operation in the aging process of a non-polar capacitor and a bidirectional TVS (Transient Voltage Suppressor) in the prior art can be effectively solved, and the problem of high cost during aging of devices such as transistors with different polarities, JFETs (Junction Field Effect Transistor) and the like can be effectively solved, and an aging tool does not need to be manufactured again.

A test method and apparatus for bipolar degradation of a diode, and a device. The method comprises: respectively performing static characteristic tests on a first diode and a second diode, so as to obtain a first static characteristic test result and a second static characteristic test result; setting a pulse test current, a pulse test time and a pulse cycle time, so that, on the basis of the pulse test current, the pulse test time and the pulse cycle time, a power semiconductor pulse current test device performs repeated short pulse current power cycle tests on the first diode under normal temperature conditions, and performs repeated short pulse current power cycle tests on the second diode under high temperature conditions; then, performing static tests, so as to obtain a plurality of static characteristic test results; and on the basis of the static characteristic test results, obtaining a bipolar degradation test result of a diode. By means of the method, bipolar degradation of the diode is tested, and the accuracy and reliability of the test result are improved.

The invention discloses a method and equipment for determining the aging degree of a power semiconductor device and a medium, and relates to the technical field of semiconductor device reliability detection, and the method comprises the steps: taking a composite data sequence as input, constructing an electrothermal bidirectional recurrent neural network model, carrying out the temperature compensation of electrical characteristic data, and generating a pure aging signal; performing time domain and frequency domain analysis on the pure aging signal, extracting a drift rate, a drift acceleration and a stable drift value, and performing vectorization processing to form an aging feature vector; comparing the aging feature vector with the multi-dimensional threshold interval one by one, and judging a corresponding aging degree grade according to a comparison result; and displaying the aging degree grade in real time, storing and generating an aging degree grade historical record, calculating an aging trend value, comparing the aging trend value with an aging warning threshold value, and triggering an early warning signal when the aging trend value exceeds the aging warning threshold value. According to the invention, the accuracy, stability and credibility of the whole aging degree determination process are improved.

The invention relates to the technical field of power semiconductor devices, and discloses a power cycle test circuit and method for a SiC power semiconductor device, and the circuit is characterized in that the AC side of a rectification circuit is connected with an AC power supply, and the DC side of the rectification circuit is connected with the first end of a DC boost circuit; the second end of the direct-current booster circuit is connected with the direct-current side of the inverter circuit; the alternating-current side of the inverter circuit is connected with an alternating-current power supply; part of power semiconductor devices in the rectifying circuit, the direct-current booster circuit and the inverter circuit are SiC power semiconductor devices to be tested. The active power cycle test circuit comprises a rectification circuit, a direct current boost circuit and an inversion circuit which are connected in series. The AC power supply provides energy for the test circuit. No load exists in the test loop, a power circulation loop is formed, and a circuit is provided for characteristic test of the SiC power semiconductor device. In the working process of the circuit, the power supply loop only needs to provide loss energy of the test loop.

A method of estimating a breakdown voltage of a silicon dioxide film includes; generating breakdown voltage information associated with first test dies selected from among test dies, generating a breakdown voltage estimation model by updating a parameter of a neural network model based on the breakdown voltage information, applying test voltages to second test die selected from among the test dies and distinct from the first dies and receiving currents levels for current generated by the second test dies in response to the test voltages, wherein the test voltages have respective levels lower than levels of breakdown voltages for the first test dies, and estimating breakdown voltages of the second test dies using the breakdown voltage estimation model in relation to the currents levels.

A method of monitoring health of a power semiconductor device includes: determining a steady state loading of the power semiconductor device; when it is determined that the power semiconductor device is under a steady state loading, monitoring a case temperature parameter relating to a temperature of the case of the power semiconductor device over a predetermined period, derive a normalised parameter from the monitored case temperature parameter and determine the health of the power semiconductor device based on the normalised parameter.

The invention relates to the technical field of flexible thin film device testing, and particularly provides a flexible thin film device testing device and system, and the device comprises a case which is internally provided with a circulating ventilation channel and an experiment cavity; the heating assembly is arranged in the circulating ventilation channel and located below the experiment cavity; the cooling assembly is arranged in the circulating ventilation channel and located above the experiment cavity; the objective table is rotationally mounted in the experiment cavity; when the actual temperature in the experiment cavity is smaller than a first preset temperature, the heating assembly heats the gas in the circulating ventilation channel until the actual temperature in the experiment cavity rises to a first preset target temperature; or when the actual temperature in the experimental cavity is higher than a second preset temperature, the cooling assembly cools the gas in the circulating ventilation channel until the actual temperature in the experimental cavity is reduced to a second preset target temperature; the device can effectively improve the temperature uniformity and the air characteristic uniformity in the experiment cavity.

The invention relates to a device (1) for determining the aging state of at least one power semiconductor switch (2), wherein the device (1) comprises at least one evaluation unit (4) and a device (5) for detecting or determining a temperature (T) of the power semiconductor switch (2), wherein the evaluation unit (4) is configured to access characteristic curves of a contact resistance (Ron) over the aging state, wherein the characteristic curves are parameterized with different temperatures (T) of the power semiconductor switch (2), wherein the evaluation unit (4) is further configured to detect a voltage value (U) across the power semiconductor switch (2) at a predetermined current value (I) through the power semiconductor switch (2) in a switched-on state and to calculate a contact resistance (Ron) from this.wherein the evaluation unit (4) then assigns an aging state to the power semiconductor switch (2) by means of a characteristic curve, taking into account the temperature (T) of the power semiconductor switch (2) detected or determined by the device (5), wherein the device (1) has at least one further device (11) for detecting or determining the temperature (T) of the power semiconductor (2), wherein the evaluation unit (4) is configured to validate and / or adjust the temperature values ​​of the power semiconductor switch (2) detected or determined by the device (5) by means of the temperature values ​​of the power semiconductor switch (2) detected or determined by the at least one further device (11), and an associated method.

The invention relates to the field of semiconductor device and integrated circuit research, in particular to a semiconductor device dose rate effect laser simulation system. Multiple wavelengths and a wide energy range are achieved through the optical fiber laser pulse seed source assembly and the solid laser amplifier assembly, the pulse width can range from 1 ns to 100 microseconds, variable complex waveforms such as square waves, rectangular waves, sine waves and pulse strings are achieved, and pulse laser with the energy range from the nanojoule level to the joule level and adjustable wavelengths and waveforms can be output according to requirements. The high-low energy laser adopts a common-path design, so that the system integration degree is improved; light spots are adjustable from centimeter level to micron level, and global irradiation and micro-area positioning and scanning of an irradiation sample can be realized. According to the invention, dose rate effects under different conditions can be accurately and flexibly simulated, the blank of a high-energy, variable-waveform and multi-wavelength dose rate effect laser simulation system is filled up, and an efficient solution is provided for the reliability research of devices under a complex irradiation environment.

The invention discloses a method, a circuit, a system and a medium for testing a total ionizing radiation dose and an electromagnetic pulse coordination effect, and relates to the technical field of anti-nuclear and radiation hardening, and the method comprises the steps: obtaining an electrical characteristic curve of a to-be-tested transistor before irradiation and a response waveform under the action of a single electromagnetic pulse; performing at least one preset dose of irradiation on the to-be-tested transistor until the accumulated irradiation dose of the to-be-tested transistor reaches the preset total dose, and obtaining an electrical characteristic curve of the to-be-tested transistor and a response waveform of the to-be-tested transistor under the action of a single electromagnetic pulse after each irradiation, obtaining an electrical characteristic curve and a response waveform of the transistor to be detected under each accumulated irradiation dose; and based on the obtained electrical characteristic curve and the response waveform, analyzing the total ionizing radiation dose of the transistor to be detected and the electromagnetic pulse coordination effect.

To provide power converters.SOLUTION: The present disclosure provides examples of methods and systems for estimating an operational state of a semiconductor chip of a power semiconductor device which are based on determining a parameter indicative of an operational state of the semiconductor chip including an indication of uncertainty of the operational state based on the received operational data. The present disclosure further provides examples of methods and systems for predicting a remaining useful life of a semiconductor chip.SELECTED DRAWING: Figure 3A

An aging board for use in aging testing semiconductor devices includes a strip socket mounted to a PCB. The strip socket includes a socket base configured to receive a device strip including a series of semiconductor devices and a socket cover including at least one heating block. The socket cover is movable between (a) an open position allowing installation of the device strip on the socket base and (b) a closed position in which the socket cover, including the heating block, is closed down on the installed device strip. The strip socket includes conductive contacts configured to contact individual semiconductor devices on the device strip to allow selective monitoring of individual semiconductor devices during an aging test process. The aging board can also include heating control circuitry to control the heating block during the aging test process.

The invention discloses a gallium oxide device electrical performance analysis method and system, relates to the field of electronic components, solves the problem of poor monitoring effect of the gallium oxide device electrical performance analysis method, and comprises the following steps: S1, carrying out multi-scene voltage performance monitoring on a sample gallium oxide device, and obtaining scene voltage monitoring data according to a monitoring result; s2, dividing the selected and analyzed gallium oxide device into a first type of electrical device and a second type of electrical device according to the scene voltage monitoring data, carrying out breakdown voltage monitoring on the first type of electrical device, and obtaining device type preliminary analysis data according to a monitoring result; and S3, performing electrical property early warning on the selected and analyzed gallium oxide device according to the device type preliminary analysis data. The comprehensiveness and pertinence of the electrical property analysis method of the gallium oxide device can be improved.

The invention discloses a continuous current pulse generation circuit for power device testing and a control method thereof, and relates to the technical field of power electronics, the continuous current pulse generation circuit comprises a power supply, a control unit, a switch unit, an energy storage unit, an inductive load and a current absorption unit; the switch unit comprises a first relay, a second relay, a third relay, n first switches and one second switch; the energy storage unit comprises n capacitors; the control unit is used for respectively controlling the on-off of the first relay, the second relay, the third relay, the n first switches and the n second switches, carrying out different-stage control on each capacitor, and providing continuous current pulse for the test of the power device; the different stages comprise a capacitor charging stage, a capacitor discharging stage according to a time sequence and a capacitor residual charge releasing stage. According to the invention, more real continuous current pulse can be provided for the power device, and the reliability test requirement of the device under the impact of the continuous current pulse is met.

The invention provides a test method for testing a semiconductor device, which comprises the following steps of: executing at least one test item in a group of test items on the semiconductor device under a first environment condition; generating, by the machine learning model, an identification result based on the test results of the at least one test item, the identification result predicting at least one test result of performing one or more test items of the set of test items on the semiconductor device under a second environmental condition; and determining whether to perform one or more test items in the set of test items on the semiconductor device under a second environmental condition based on the identification result. According to the invention, based on the test result under the first environment condition, the machine learning model is utilized to predict and obtain the corresponding identification result, so that whether the test needs to be executed again under the second environment or not is determined according to the identification result.

The invention belongs to the technical field of component measurement, and particularly relates to a device capable of switching components in a closed box body outside the box body to carry out an electrical test, which comprises a measurement button, a controller, a relay, a driving module of the relay and a component fixing clamp, the measuring button, the controller, the relay and the driving module of the relay are sequentially connected, and the controller receives a control instruction sent by the measuring button and drives the relay and the driving module of the relay to switch electrical connection of components in the closed box body according to the control instruction; the component fixing clamp is used for installing a component to be tested, and a port is reserved in the component fixing clamp and used for being connected with a test power source. According to the invention, components in the closed box body are switched to carry out an electrical test under the condition that the closed box body is not opened, and the change of a test environment caused by opening the closed box body to replace the components is avoided, so that the influence on an electrical test result of the components is avoided, and the time for readjusting the test environment to be stable is saved.