566results about "Semiconductor operation lifetime testing" patented technology

The invention relates to the technical field of semiconductor device testing, in particular to a SiC MOSFET power cycle testing method which comprises the following steps: S1, building a composite environment testing platform, configuring dynamic testing parameters, automatically calculating a physical boundary and collecting sensor data in real time; s2, establishing a finite element simulation model based on the physical boundary and sensor data, and outputting optimized dynamic test parameters and a simulated stress distribution diagram; s3, synchronously applying composite stress according to the dynamic test parameters and the stress distribution diagram, and collecting multi-dimensional test data in real time; when the system is used, through dynamic boundary calculation and real-time data acquisition, the intelligent degree and reliability of the test are improved, the test period is shortened, the failure prediction accuracy is improved, the system is suitable for reliability evaluation of SiC MOSFET devices in the fields of new energy, aerospace and the like, a large number of physical tests are avoided through virtual simulation, and the reliability of the SiC MOSFET devices is improved. And reduction of device loss and resource waste is facilitated.

The invention discloses a nanosecond-order delay transistor reliability test system and method, and belongs to the technical field of transistor test. The test system is divided into three parts, namely a voltage stress value and stress duration control module, a current control module and a hard switch transient and on-resistance test module. The drain voltage stresses are respectively used for controlling the drain voltage stress value and the drain voltage stress duration of the transistor to be tested; the current during hard switch testing is determined; and the conduction time is long. The test system processes signals through a hardware circuit, can convert an input single-path pulse signal into two paths of inverted pulse signals with dead time, and improves the safety of the test system. The voltage stress duration, the current and the conduction duration of the drain electrode of the transistor to be tested can be flexibly regulated and controlled only by inputting a pulse signal to each of the three modules. Simulation and experiments prove that the measurement delay of switching to the test state after the drain electrode voltage stress is ended is nanosecond magnitude, and the method has important significance for monitoring performance degradation after the transistor drain electrode voltage stress is monitored in real time.

The present disclosure concerns a method for measuring a degradation of thermal characteristics of a power module comprising sequences of: - injecting current pulses (Pinj), having a voltage-clamped constant amplitude (Iinj), between an emitter and a gate of a power semiconductor of such power module, a duration of said voltage-clamped constant amplitude (Iinj) current pulses (Pinj) being modulated periodically with a modulation frequency (Fmod), said current pulses causing losses modulated with said modulation frequency (Fmod), - measuring a parameter (k Tj) dependent of a junction temperature (Tj) of such power semiconductor at the beginning of said current pulses, - measuring a phase shift (Δφ) between said modulation frequency (Fmod) and said parameter (k·Tj), said phase shift (Δφ) providing a health indicator for the power module.

The present application provides a method and system for predicting the remaining service life of an IGBT device, comprising: simulating an IGBT device power cycle aging experiment, collecting conduction voltage drop historical data on the basis of the experiment, and respectively obtaining a model parameter empirical value and a model parameter estimated value on the basis of the conduction voltage drop historical data; constructing a first state weight on the basis of the current operation state, and performing smooth adjustment on the model parameter estimated value on the basis of the model parameter empirical value and the first state weight to obtain a parameter correction result; and establishing a state transition equation on the basis of the parameter correction result, and predicting the remaining service life of an IGBT device on the basis of the state transition equation. Use of the present application can improve the accuracy of prediction of the remaining service life of the IGBT device.

The invention discloses an electronic component quality control method and system, and relates to the technical field of transistor performance quality control. The quality control method for the electronic component comprises the following steps: evaluating transistor switch abnormity; switching speed delay regulation and control; and evaluating the input signal response control accuracy. Transistor switching abnormality evaluation is carried out in the transistor switching process, then whether switching speed delay optimization is carried out or not is judged based on a quantization result, if switching speed delay optimization is carried out, switching speed delay regulation and control are carried out, and if switching speed delay optimization is not carried out, input signal response control accuracy evaluation is carried out. And finally, judging whether to carry out input signal response control optimization or not based on a quantification result of the input signal response control accuracy evaluation, thereby achieving the effect of improving the response control sufficiency of the transistor on the input signal in the switching process. The problem that the switch response difference is not fully considered in the response control process of a transistor to an input signal in the prior art is solved.

The invention relates to the technical field of photoelectric detection, in particular to a laser diode state monitoring method and system based on multi-parameter fusion, and the method comprises the steps: carrying out the laying and collection of a plurality of parameters based on the working condition of a laser diode, including current, temperature and optical feedback signals, and carrying out the dynamic fusion to construct a damage index; establishing a grading early warning mechanism, correspondingly setting a judgment threshold value, and triggering early warning in combination with the damage index; the temperature is detected periodically, parameter drift influenced by the temperature is corrected based on a damage index, and state monitoring of the laser diode is achieved; by dynamically fusing a plurality of parameters of current, temperature and optical feedback signals, a multi-dimensional damage index is established, so that the influence of a plurality of indexes on laser diode damage is synthesized, and the recognition rate of early damage is improved; and establishing a grading early warning mechanism from a slight state to a serious state, making a corresponding early warning response, and advancing fault recognition of the laser diode to a reversible stage.

The invention discloses a method for preventing needle burning during testing of breakdown voltage of a discrete device. According to the method, in a test loop comprising a probe card and a test source, a voltage-withstanding module is connected in series between the probe card and a low-potential end of the test source. The voltage-withstanding module comprises a detection resistor Rx and a voltage-withstanding switching device connected with the detection resistor Rx in parallel. When the test current I is applied, if the current is increased abnormally due to poor contact and the like, and the voltage drop on the detection resistor Rx is greater than or equal to the starting voltage VT of the voltage-withstanding switching device, the voltage-withstanding switching device is switched on, the test current I is shunted, and the current flowing through the probe card is reduced, so that the probe is prevented from being burnt. The breakdown voltage of the tested device is calculated by measuring the total voltage V at the two ends of the test source and subtracting the voltage drop (I * Rx) on the detection resistor Rx, and the test accuracy is ensured. The method can effectively protect the probe card and improve the test reliability and efficiency.

The present disclosure concerns a method for measuring a degradation of thermal characteristics of a power module comprising sequences of: - injecting current pulses (Pinj), having a voltage-clamped constant amplitude (IInj), between an emitter and a gate of a power semiconductor of such power module, a duration of said voltage-clamped constant amplitude (Iinj) current pulses (Pinj) being modulated periodically with a modulation frequency (Fmod), said current pulses causing losses modulated with said modulation frequency (Fmod), - measuring a parameter (k.Tj) dependent of a junction temperature (Tj) of such power semiconductor at the beginning of said current pulses, - measuring a phase shift (Δφ) between said modulation frequency (Fmod) and said parameter (k.Tj), said phase shift (Δφ) providing a health indicator for the power module.　

The present disclosure provides an automated repair of LED substrates system in which an automated repair inspection module is used to determine the quality of incoming processing material an automated repair process module is used to process the processing material, an automated repair post-process module is used to inspect the resultant process material for acceptability, and an automated repair historical module is used to analyze the post process results of the most recent process, against all historical data to find enhanced process changes in the automated repair process module, and an automated repair integration module to update the automated repair process module based upon the results of the automated repair historical module.

The invention discloses a WOA-LSTM-based SiC MOSFET life prediction method and device, and a storage medium, and relates to the technical field of reliability prediction of power electronic equipment. The method comprises the following steps: selecting drain-source electrode voltage as an aging characteristic parameter of the SiC MOSFET, and acquiring voltage data in real time in an aging test process by using a sensor; the collected voltage data are preprocessed, abnormal values are eliminated, missing values are supplemented, and the data are smoothed; the method comprises the following steps: optimizing parameters of a long short-term memory network LSTM through a whale optimization algorithm WOA, and constructing a WOA-LSTM prediction model; and initializing a WOA-LSTM model, inputting voltage data for training, and establishing a mapping relation between the service life of the SiC MOSFET and the voltage to realize prediction of the residual service life of the SiC MOSFET. The SiC MOSFET service life prediction model has the advantages of being high in adaptability, low in calculation complexity, high in prediction precision and the like, can be widely applied to the fields of the semiconductor industry, new energy automobiles, industrial automation and the like, and provides powerful support for health management and maintenance of equipment.

The invention provides a fault detection method and system for a gallium nitride power device, and relates to the technical field of fault detection, and the method comprises the steps: determining the safe operation parameters of the gallium nitride power device under a preset working condition according to the rated electrical parameters, chip structure parameters and packaging characteristics of the gallium nitride power device; extracting state response characteristics of the gallium nitride power device under a preset working condition; constructing a fault evidence matrix of the gallium nitride power device under a preset working condition based on the safe operation parameters and the state response characteristics; and performing fault state evaluation on the gallium nitride power device according to the fault evidence matrix to obtain a fault state factor of the gallium nitride power device, and further determining the fault probability of grid degradation of the gallium nitride power device based on the fault state factor. According to the scheme, the operation safety and the state response of the gallium nitride power device under the high-frequency switching working condition can be comprehensively analyzed, so that the evaluation accuracy of the device fault state is improved.

The invention discloses a power electronic device fault early warning method based on multi-physics field coupling, and the method comprises the steps: (1) collecting aging data of a power electronic device under the condition of electric field and thermal field coupling, and dividing the aging data into a source domain data set and a target domain data set; (2) establishing a power electronic device aging parameter screening method, selecting a parameter which can best represent an aging rule as an aging precursor, and converting discrete voltage and current signals into time sequence signals which can be accepted by a neural network; (3) compressing the time sequence signal set into sliding window graph nodes, calculating a distance relationship between the graph nodes, and obtaining a graph matrix containing data structure information; (4) building a space-time fusion fault predictor, wherein the space-time fusion fault predictor comprises a feature extractor, a time sequence predictor and a domain discriminator; and (5) a weak supervision adversarial learning strategy is adopted, a small amount of target domain label data participates in the model training process, and the source domain prediction loss, the target domain prediction loss and the discrimination loss are combined for training.

The invention relates to the technical field of semiconductor testing, in particular to a method and a system for testing avalanche tolerance of a semiconductor diode. The method comprises the following steps: in the process of peak voltage stimulation and recovery to a stable state, obtaining a thermal imaging image of a semiconductor diode, and determining a peak value region of local temperature; determining a heat dissipation insufficiency index according to the temperature change and the area of the peak region; determining a local overheating factor of the thermal imaging image in combination with the heat dissipation insufficiency index and the distances of all peak regions; determining the dissipation rate of the local overheating phenomenon of the diode according to the numerical change of the local overheating factors of all thermal imaging images on the time sequence; determining the possibility of thermal breakdown by combining the local overheating factor and the dissipation rate; and determining the avalanche tolerance according to the numerical change of all thermal breakdown possibilities of the diode at different peak voltages. The avalanche tolerance can be specifically analyzed according to the temperature change, so that the accuracy of the avalanche tolerance is higher.

The invention discloses a passive DHTRB test circuit, method and product with optimized performance. The test circuit comprises a power supply, a first test accompanying tube S1, a second test accompanying tube S2, a tested device DUT, a positive overshoot circuit and a negative overshoot circuit. The positive electrode of the power supply is connected to the input end of the positive electrode overshoot circuit, the output end of the positive electrode overshoot circuit is connected with the drain electrode of the first test accompanying tube S1, the source electrode of the first test accompanying tube S1 is connected with the second test accompanying tube S2 and the drain electrode of the tested device DUT, the source electrode of the second test accompanying tube S2 is connected with the input end of the negative electrode overshoot circuit, and the output end of the negative electrode overshoot circuit is connected with the source electrode of the tested device DUT and is connected to the negative electrode of the power supply; when the first test accompanying tube S1 is switched on and the second test accompanying tube S2 is switched off, the positive overshoot circuit outputs forward overshoot voltage to the outside; when the first test accompanying tube S1 is turned off and the second test accompanying tube S2 is turned on, the negative overshoot circuit outputs a reverse overshoot voltage to the outside. According to the invention, the dV / dt performance of the passive DHTRB test can be improved.

The embodiment of the invention discloses a semiconductor device service life evaluation method based on a power cycle test and related equipment, and the method comprises the steps: dividing semiconductor devices produced by the same factory in the same batch into two parts, and executing a second-level power cycle test on one part, a millisecond-level power cycle test is firstly executed on the other part, and then a second-level power cycle test is executed on the other part; establishing a first life model according to one test result, and establishing a second life model according to the other test result; and calculating a third life model corresponding to the millisecond power cycle test according to the first life model and the second life model, and performing life evaluation on the semiconductor device according to the third life model. By adopting the embodiment of the invention, the reliability assessment requirement of the power semiconductor device in the future can be met, and the aims of accelerating aging and meeting the actual working condition can be fulfilled, so that an important reference significance is provided for the research of the reliability test of the device and the assessment of the actual life.

The invention provides a silicon carbide chip performance evaluation method and evaluation system, and relates to the field of semiconductor testing. Nonlinear disturbance components are separated from dynamic response data; constructing a link transmission compensation function based on the nonlinear disturbance component, and determining dynamic characteristic parameters through the link transmission compensation function and the dynamic response data; performing multi-dimensional spectrum analysis on the dynamic characteristic parameters to obtain high-frequency performance parameters, and further performing thermal energy efficiency derivation on the silicon carbide chip according to the high-frequency performance parameters to obtain an energy efficiency trend and energy efficiency thermal coupling characteristics; performing multi-working-condition pulse excitation on the silicon carbide chip according to the deviation abnormal value to obtain a multi-dimensional compensation matrix; adaptive coupling compensation is carried out on the energy efficiency trend and the energy efficiency thermal coupling characteristics based on the multi-dimensional compensation matrix, then a performance evaluation data set of the silicon carbide chip is obtained, multi-dimensional adaptive coupling compensation based on abnormal value driving can be achieved, and the reliability of performance evaluation of the silicon carbide chip is improved.

The invention belongs to the technical field of semiconductor testing, and discloses a thermistor performance monitoring method and system based on a power module reliability test. The method comprises the following steps: configuring a pin connection structure electrically connected with a thermistor lead on a test burn-in board for a high-temperature, high-humidity and high-voltage reverse bias test; in the process of executing a high-temperature, high-humidity and high-voltage reverse bias test on the power module comprising the thermistor, a lead of the thermistor is electrically connected with a preset current detection loop through the pin connection structure, so that monitoring current flowing through the thermistor is received by the current detection loop, and thermistor performance monitoring is executed. According to the application, the problem that the self degradation risk of the thermistor cannot be monitored in real time in the H3TRB test process to cause a monitoring blind area can be solved, the whole-process monitoring of the performance fluctuation of the thermistor in the strong electric field and high humidity coupling environment is realized, and the integrity of the reliability evaluation of the power module and the safety of the test system are remarkably improved.

The invention provides semiconductor device thermal resistance measuring equipment, which is applied to the technical field of electrical variable measurement and comprises a case, a workbench fixed at the top of the case, a constant-temperature base arranged in the middle of the workbench, a rack arranged on one side of the workbench and erected above the constant-temperature base, a thermal resistance detector matched with the rack, and a temperature sensor arranged on the thermal resistance detector. The top of the rack is provided with a pressing mechanism which can press and abut against the semiconductor device to be tested towards the upper end face of the constant-temperature base. The middle part of the upper end surface of the constant-temperature base is provided with a flexible heat-conducting contact pad used for self-adapting to the shape of a semiconductor device to be tested, and the flexible heat-conducting contact pad is internally provided with a temperature control assembly; and an environment simulation mechanism is matched on the pressing mechanism. The thermal resistance testing device has a high-adaptability and high-precision thermal resistance testing structure, can adapt to semiconductor devices in various shapes for testing, can simulate the actual application environment of the semiconductor devices, can provide reliable data support for thermal management design of the semiconductor devices, and is good in overall use effect.

The invention discloses a wafer aging test system and a wafer aging test method. The wafer aging test system comprises wafer transportation equipment; the wafer loading and unloading equipment is arranged on one side of the wafer transportation equipment; the wafer aging test equipment comprises at least one wafer aging test device, and the at least one wafer aging test device is arranged on at least one side of the wafer transportation equipment; any one wafer aging test device is opposite to the wafer transportation equipment to form a first transportation channel; the wafer conveying device comprises a wafer taking and placing device, a second conveying channel is formed in the wafer conveying device, any first conveying channel is communicated with the second conveying channel, and the wafer taking and placing device bears wafers and is controlled to move in the second conveying channel or any first conveying channel so as to achieve feeding or discharging of the wafers. According to the embodiment of the invention, parallel testing of a plurality of test positions can be expanded, the testing efficiency is improved, and the flexibility and rationality of equipment layout are improved at the same time.

A first voltage supply is coupled to a first terminal of a test transistor. A first terminal of a probe circuit is coupled to the first terminal of the test transistor. A second terminal of the probe circuit is coupled to a second terminal of the test transistor. A third terminal of the probe circuit is coupled to a control terminal of the test transistor. A first terminal of the first resistor is coupled to the second terminal of the test transistor. A second terminal of the first resistor is coupled to a second voltage supply. A first input terminal of an amplifier is coupled to a third voltage supply. A second input terminal of an amplifier is coupled to the first terminal of the first resistor. An output terminal of an amplifier is coupled to the control terminal of the test transistor.

The present invention discloses an experimental apparatus and a test method for a pulse laser irradiation wide bandgap power device. The apparatus includes an optical path coupling system, a circuit test system, a temperature control system, and an interaction control system. According to the present invention, irradiation sensitive region locating, irradiation transient current tests, irradiation sensitive condition tests, and irradiation degradation tests for the wide bandgap power device are implemented, and advantages of convenience in experiments, simple operation, automated tests, comprehensive and accurate test results, and the like are achieved.

An electrical circuit arrangement includes a first diode and a semiconductor switching device electrically connected in series between a first node and a second node. The semiconductor switching device controls a switch current that includes a forward current through the first diode and a load current. A second diode and a calibration switching element are electrically connected in series between the first node and the second node. A voltage acquisition circuit obtains a voltage difference between a first voltage between the first node and the second node when the semiconductor switching device is on and the calibration switching element is off and a second voltage between the first node and the second node when the calibration switching element is on and the semiconductor switching device is off.

The invention discloses a semiconductor device acceleration reliability test method and device based on stress superposition, and relates to the technical field of power semiconductor device testing, and the method comprises the steps: obtaining acceleration factors of key stress factors of different failure types in a current practical application scene, and interaction coefficients between the key stress factors; obtaining an optimal stress factor superposition sequence of each failure type, and constructing a test content flow sequence of each failure type; testing the current type of power semiconductor device according to the test content flow sequence of each failure type to obtain a performance index; constructing a failure database, constructing feature matrix vectors according to the performance indexes, and storing the feature matrix vectors into the failure database; statistical analysis is carried out on each feature matrix vector in the failure database, the reliability level associated with each feature matrix is obtained, reliability evaluation is carried out on the performance index according to the failure database, the reliability level of the current type of power semiconductor device is obtained, and the test efficiency and the accuracy of a test result are remarkably improved.

Various example embodiments relate to a burn-in board and / or a burn-in test method using the burn-in board. A burn-in board according to various example embodiments includes a substrate having a first surface and a second surface opposite each other, and a slot configured to receive a semiconductor device on or at the first surface of the substrate. The first surface of the substrate defines an extension portion extending in a first direction and having an interior space on or at the first surface of the substrate.

A semiconductor device apparatus is provided. The apparatus includes a packaged semiconductor device mounted on a substrate. The packaged semiconductor device includes a semiconductor die having a controller configured to obtain a measured capacitance of a sensor capacitor, an encapsulant encapsulating the semiconductor die, and a first plate of the sensor capacitor formed at a bottom side of the packaged semiconductor device. A second plate of the sensor capacitor is formed at a top side of the substrate.

The invention relates to the technical field of temperature change testing, and provides a rapid temperature change test box for wafer testing, which comprises an experimental device, a test box is installed on one side of the experimental device, a partition device is installed in the middle of the middle of the interior of the test box, and a sliding assembly is sleeved with the partition device. The upper end of the sliding assembly is fixedly connected with a driving device, and the driving device penetrates through the top of the test box and is installed above the test box. The wafer clamp flexibly clamps the wafer, stacking of the wafer during testing is avoided, the wafer is connected with the clamping block through the rotating disc, and the rotating fan rotates along with cold air or hot air, so that hot air or cold air swollen in a temperature change experiment can be conveniently gathered around the wafer and fully and comprehensively contacted with the wafer, the accuracy of the experiment is ensured, and the test efficiency is improved. And meanwhile, the rotating fan drives the wafer clamped by the rotating disc to rotate in the wafer clamp, so that water drops generated by heat release and condensation of air on the surface of the wafer are wiped by the brush strip, and the phenomenon that the test result is easily influenced due to corrosion of the wafer is prevented.

The present application relates to a dynamic stress aging test method and system for GaN power devices, comprising: obtaining dynamic pulse voltage stress data and temperature stress data corresponding to the GaN power device under test; wherein the dynamic pulse voltage stress data is used to periodically switch the on / off state of the GaN power device under test; obtaining test conditions based on the dynamic pulse voltage stress data and the temperature stress data; performing a dynamic stress aging test on the GaN power device under test according to the test conditions, and collecting electrical parameters of the GaN power device under test during the stress process; obtaining test results based on comparison of the electrical parameters with preset failure thresholds, and reflecting the reliability of the GaN power device in a more realistic and rigorous manner by applying a dynamic pulse voltage stress that is closer to the actual operating conditions of the GaN power device under test, while simultaneously rapidly monitoring the actual degradation of the electrical parameters online during the stress application process, thereby avoiding the problem of inaccurate measurement caused by offline testing and the rapid recovery characteristics of the device.

The invention relates to the technical field of reliability testing of semiconductor power devices, and discloses a short-circuit robustness testing method and system based on grid stress degradation of a silicon carbide device, and the method comprises the steps of pre-testing short circuit, grid stress application and post-testing short circuit are continuously executed under the same physical connection by configuring a coupling testing time sequence. The control unit cooperates with the driving unit to generate a static positive and negative bias and dynamic switch stress mode, and cooperates with the power loop auxiliary switch action to simulate different short circuit faults. A dynamic and static index correlation model is established to quantitatively evaluate robustness by collecting transient waveforms and measuring static parameters and calculating short-circuit energy integral, threshold voltage and drift distance of on resistance. According to the invention, the in-situ test of the aging and short-circuit characteristics of the device is realized, the contact resistance change and the loop parasitic parameter difference caused by the repeated disassembly and assembly of the device in the traditional discrete test are eliminated, and the change of the two short-circuit waveforms completely corresponds to the internal degradation of the device caused by the grid stress.

The invention relates to the technical field of wafer testing, and discloses a wafer aging test system and method with a dynamic gate bias and reverse bias test function, and the system comprises a main control board, an industrial control computer, a high-voltage source, a source meter, a high-voltage switching board, a test switching board, and a needle card board. Dynamic high-temperature reverse bias and dynamic high-temperature gate bias tests can be added on the basis of static high-temperature reverse bias and reverse bias tests, higher requirements for SiC power device reliability testing equipment in the industry are met, stress borne by a chip under the actual working condition can be simulated, and the reliability of the SiC power device is improved. And the threshold voltage is monitored on line in real time while the pulse voltage is implemented, so that the reliability of the chip can be better evaluated.

The invention provides an electronic device aging test apparatus, including a box body, a test chamber provided in the box body and provided with an air inlet and an air return inlet, a circulating air duct provided on a periphery of the test chamber and in fluid communication with the air inlet and the air return inlet, and a circulating fan. A fresh air port and an air outlet are provided on a wall of the circulating air duct. The air outlet is provided downstream of the air return inlet, and the fresh air port is provided upstream of the circulating fan. The fresh air port is located between the air outlet and the circulating fan, and a baffle device is provided between the fresh air port and the air outlet. The baffle device has at least two working states.