202results about "Semiconductor operation lifetime testing" patented technology

The invention belongs to the technical field of semiconductor testing, and discloses a thermistor performance monitoring method and system based on a power module reliability test. The method comprises the following steps: configuring a pin connection structure electrically connected with a thermistor lead on a test burn-in board for a high-temperature, high-humidity and high-voltage reverse bias test; in the process of executing a high-temperature, high-humidity and high-voltage reverse bias test on the power module comprising the thermistor, a lead of the thermistor is electrically connected with a preset current detection loop through the pin connection structure, so that monitoring current flowing through the thermistor is received by the current detection loop, and thermistor performance monitoring is executed. According to the application, the problem that the self degradation risk of the thermistor cannot be monitored in real time in the H3TRB test process to cause a monitoring blind area can be solved, the whole-process monitoring of the performance fluctuation of the thermistor in the strong electric field and high humidity coupling environment is realized, and the integrity of the reliability evaluation of the power module and the safety of the test system are remarkably improved.

An electrical circuit arrangement includes a first diode and a semiconductor switching device electrically connected in series between a first node and a second node. The semiconductor switching device controls a switch current that includes a forward current through the first diode and a load current. A second diode and a calibration switching element are electrically connected in series between the first node and the second node. A voltage acquisition circuit obtains a voltage difference between a first voltage between the first node and the second node when the semiconductor switching device is on and the calibration switching element is off and a second voltage between the first node and the second node when the calibration switching element is on and the semiconductor switching device is off.

A semiconductor device apparatus is provided. The apparatus includes a packaged semiconductor device mounted on a substrate. The packaged semiconductor device includes a semiconductor die having a controller configured to obtain a measured capacitance of a sensor capacitor, an encapsulant encapsulating the semiconductor die, and a first plate of the sensor capacitor formed at a bottom side of the packaged semiconductor device. A second plate of the sensor capacitor is formed at a top side of the substrate.

The invention relates to the technical field of reliability testing of semiconductor power devices, and discloses a short-circuit robustness testing method and system based on grid stress degradation of a silicon carbide device, and the method comprises the steps of pre-testing short circuit, grid stress application and post-testing short circuit are continuously executed under the same physical connection by configuring a coupling testing time sequence. The control unit cooperates with the driving unit to generate a static positive and negative bias and dynamic switch stress mode, and cooperates with the power loop auxiliary switch action to simulate different short circuit faults. A dynamic and static index correlation model is established to quantitatively evaluate robustness by collecting transient waveforms and measuring static parameters and calculating short-circuit energy integral, threshold voltage and drift distance of on resistance. According to the invention, the in-situ test of the aging and short-circuit characteristics of the device is realized, the contact resistance change and the loop parasitic parameter difference caused by the repeated disassembly and assembly of the device in the traditional discrete test are eliminated, and the change of the two short-circuit waveforms completely corresponds to the internal degradation of the device caused by the grid stress.

The invention discloses a method and equipment for determining the aging degree of a power semiconductor device and a medium, and relates to the technical field of semiconductor device reliability detection, and the method comprises the steps: taking a composite data sequence as input, constructing an electrothermal bidirectional recurrent neural network model, carrying out the temperature compensation of electrical characteristic data, and generating a pure aging signal; performing time domain and frequency domain analysis on the pure aging signal, extracting a drift rate, a drift acceleration and a stable drift value, and performing vectorization processing to form an aging feature vector; comparing the aging feature vector with the multi-dimensional threshold interval one by one, and judging a corresponding aging degree grade according to a comparison result; and displaying the aging degree grade in real time, storing and generating an aging degree grade historical record, calculating an aging trend value, comparing the aging trend value with an aging warning threshold value, and triggering an early warning signal when the aging trend value exceeds the aging warning threshold value. According to the invention, the accuracy, stability and credibility of the whole aging degree determination process are improved.

A method of monitoring health of a power semiconductor device includes: determining a steady state loading of the power semiconductor device; when it is determined that the power semiconductor device is under a steady state loading, monitoring a case temperature parameter relating to a temperature of the case of the power semiconductor device over a predetermined period, derive a normalised parameter from the monitored case temperature parameter and determine the health of the power semiconductor device based on the normalised parameter.

The invention relates to a device (1) for determining the aging state of at least one power semiconductor switch (2), wherein the device (1) comprises at least one evaluation unit (4) and a device (5) for detecting or determining a temperature (T) of the power semiconductor switch (2), wherein the evaluation unit (4) is configured to access characteristic curves of a contact resistance (Ron) over the aging state, wherein the characteristic curves are parameterized with different temperatures (T) of the power semiconductor switch (2), wherein the evaluation unit (4) is further configured to detect a voltage value (U) across the power semiconductor switch (2) at a predetermined current value (I) through the power semiconductor switch (2) in a switched-on state and to calculate a contact resistance (Ron) from this.wherein the evaluation unit (4) then assigns an aging state to the power semiconductor switch (2) by means of a characteristic curve, taking into account the temperature (T) of the power semiconductor switch (2) detected or determined by the device (5), wherein the device (1) has at least one further device (11) for detecting or determining the temperature (T) of the power semiconductor (2), wherein the evaluation unit (4) is configured to validate and / or adjust the temperature values ​​of the power semiconductor switch (2) detected or determined by the device (5) by means of the temperature values ​​of the power semiconductor switch (2) detected or determined by the at least one further device (11), and an associated method.

The invention relates to the field of semiconductor device and integrated circuit research, in particular to a semiconductor device dose rate effect laser simulation system. Multiple wavelengths and a wide energy range are achieved through the optical fiber laser pulse seed source assembly and the solid laser amplifier assembly, the pulse width can range from 1 ns to 100 microseconds, variable complex waveforms such as square waves, rectangular waves, sine waves and pulse strings are achieved, and pulse laser with the energy range from the nanojoule level to the joule level and adjustable wavelengths and waveforms can be output according to requirements. The high-low energy laser adopts a common-path design, so that the system integration degree is improved; light spots are adjustable from centimeter level to micron level, and global irradiation and micro-area positioning and scanning of an irradiation sample can be realized. According to the invention, dose rate effects under different conditions can be accurately and flexibly simulated, the blank of a high-energy, variable-waveform and multi-wavelength dose rate effect laser simulation system is filled up, and an efficient solution is provided for the reliability research of devices under a complex irradiation environment.

The invention discloses a method, a circuit, a system and a medium for testing a total ionizing radiation dose and an electromagnetic pulse coordination effect, and relates to the technical field of anti-nuclear and radiation hardening, and the method comprises the steps: obtaining an electrical characteristic curve of a to-be-tested transistor before irradiation and a response waveform under the action of a single electromagnetic pulse; performing at least one preset dose of irradiation on the to-be-tested transistor until the accumulated irradiation dose of the to-be-tested transistor reaches the preset total dose, and obtaining an electrical characteristic curve of the to-be-tested transistor and a response waveform of the to-be-tested transistor under the action of a single electromagnetic pulse after each irradiation, obtaining an electrical characteristic curve and a response waveform of the transistor to be detected under each accumulated irradiation dose; and based on the obtained electrical characteristic curve and the response waveform, analyzing the total ionizing radiation dose of the transistor to be detected and the electromagnetic pulse coordination effect.

An aging board for use in aging testing semiconductor devices includes a strip socket mounted to a PCB. The strip socket includes a socket base configured to receive a device strip including a series of semiconductor devices and a socket cover including at least one heating block. The socket cover is movable between (a) an open position allowing installation of the device strip on the socket base and (b) a closed position in which the socket cover, including the heating block, is closed down on the installed device strip. The strip socket includes conductive contacts configured to contact individual semiconductor devices on the device strip to allow selective monitoring of individual semiconductor devices during an aging test process. The aging board can also include heating control circuitry to control the heating block during the aging test process.

The invention provides a test method for testing a semiconductor device, which comprises the following steps of: executing at least one test item in a group of test items on the semiconductor device under a first environment condition; generating, by the machine learning model, an identification result based on the test results of the at least one test item, the identification result predicting at least one test result of performing one or more test items of the set of test items on the semiconductor device under a second environmental condition; and determining whether to perform one or more test items in the set of test items on the semiconductor device under a second environmental condition based on the identification result. According to the invention, based on the test result under the first environment condition, the machine learning model is utilized to predict and obtain the corresponding identification result, so that whether the test needs to be executed again under the second environment or not is determined according to the identification result.

The invention belongs to the technical field of component measurement, and particularly relates to a device capable of switching components in a closed box body outside the box body to carry out an electrical test, which comprises a measurement button, a controller, a relay, a driving module of the relay and a component fixing clamp, the measuring button, the controller, the relay and the driving module of the relay are sequentially connected, and the controller receives a control instruction sent by the measuring button and drives the relay and the driving module of the relay to switch electrical connection of components in the closed box body according to the control instruction; the component fixing clamp is used for installing a component to be tested, and a port is reserved in the component fixing clamp and used for being connected with a test power source. According to the invention, components in the closed box body are switched to carry out an electrical test under the condition that the closed box body is not opened, and the change of a test environment caused by opening the closed box body to replace the components is avoided, so that the influence on an electrical test result of the components is avoided, and the time for readjusting the test environment to be stable is saved.

The present invention related to the field of degradation and / or failure prediction, and more specifically to the field of prediction of degradation and / or failure of power devices and assemblies comprising power devices. The method according to the invention comprises a pre-phase creating a data model for determining the degradation level of a power device; a calibration phase wherein the data model is used to provide a set of power devices with known degradation levels which are used to create a database of behavior signatures of power device assemblies; and a run-time phase determining the remaining lifetime of an installed power device assembly in use. A system suitable for executing the method is provided.

The invention provides a cartridge comprising a socket of insulative material and having upper and lower sides and a formation on the upper side to hold an electronic device; a set of contacts held in the socket to connect to the electronic device; a set of terminals connected to the set of contacts held by the socket; a circuit board, the set of terminals connected to the set of contacts being connected to a set of contacts on the circuit board; a lid; a detector mounted to the lid, the lid being movable to be positioned over the socket with the detector located in a position to detect a feature of the electronic device when and due to power being supplied through at least one of the set of terminals held by the socket to the electronic device; and a measurement channel connecting the detector to an interface on the circuit board.

The invention discloses an IGBT aging monitoring method and apparatus, and an electronic device. The method comprises the steps of obtaining a pre-established first junction temperature expression, a first shell temperature expression and a model parameter conversion model of a to-be-monitored IGBT; the actually measured junction temperature and the actually measured shell temperature of the IGBT to be monitored and initial values of model parameters of the four-order Cauer thermal network model are obtained; fitting the first junction temperature expression in combination with the actually measured junction temperature to obtain a junction temperature initial value coefficient and a time constant; inputting different values of the junction temperature initial value coefficient, the time constant and the model parameter into a model parameter conversion model to obtain a shell temperature initial value coefficient corresponding to each value; inputting each value of the model parameter and the initial value coefficient of the shell temperature into a first shell temperature expression to obtain the shell temperature corresponding to each value; and evaluating the aging state of the to-be-monitored IGBT according to the model parameter corresponding to the shell temperature closest to the actually measured shell temperature. According to the invention, the aging state can be accurately evaluated in real time in different states.

The invention provides a cartridge comprising a socket made of insulative material and having upper and lower sides, the upper side having a first formation for releasably holding a first electronic device, the socket having a first socket thermal opening formed from the lower side to the upper side through the socket, an interface connected to the socket to connect the first electronic device to an electric tester, a chuck of a thermally conductive material, a first thermal post attached to the chuck, the first thermal post being inserted into the first socket thermal opening, an end of the first thermal post being thermally connected to and in contact with the first electronic device, such that heat transfers primarily through the first thermal post as opposed to the insulative material of the socket between the chuck and the first electronic device, and a first set of contacts held in the socket and connecting terminals of the first electronic device to the interface, the first set of contacts being resiliently depressible to bring the first electronic device into contact with the end forming a first thermal surface of the first thermal post.

The invention relates to the technical field of semiconductor device testing, in particular to a method and a system for quickly predicting the service life of a GaN device. The method comprises the following steps: acquiring physical structure attributes and use scene information of a GaN device to be tested; determining key working condition parameters and corresponding target stress conditions based on the physical structure attributes and the use scene information; based on the target stress condition, performing an adaptive composite accelerated stress test on the to-be-tested GaN device to obtain a degradation fingerprint vector; constructing joint probability distribution of the key working condition parameters based on use scene information; and constructing a life prediction model, and obtaining life distribution of the to-be-tested GaN device by using the life prediction model based on the degradation fingerprint vector and the joint probability distribution. The problem that in the prior art, rapid prediction of the service life of a GaN device is not accurate enough is solved. Through combination of the device structure and scene information, self-adaptive acceleration testing and modeling, the testing time is reduced, and the accuracy of GaN device life prediction is improved at the same time.

The application provides a performance evaluation method and evaluation system of a silicon carbide chip, relates to the field of semiconductor testing, separates a nonlinear disturbance component from dynamic response data; constructs a link transmission compensation function based on the nonlinear disturbance component, determines dynamic characteristic parameters through the link transmission compensation function and the dynamic response data; performs multi-dimensional spectrum analysis on the dynamic characteristic parameters to obtain high-frequency performance parameters, and then derives energy efficiency of the silicon carbide chip according to the high-frequency performance parameters to obtain energy efficiency trend and energy efficiency thermal coupling characteristics; deviates from abnormal values to perform multi-working-condition pulse excitation on the silicon carbide chip to obtain a multi-dimensional compensation matrix; and performs adaptive coupling compensation on the energy efficiency trend and the energy efficiency thermal coupling characteristics based on the multi-dimensional compensation matrix, and then obtains a performance evaluation data set of the silicon carbide chip. The application can realize multi-dimensional adaptive coupling compensation driven by abnormal values to improve the reliability of performance evaluation of the silicon carbide chip.

A method for controlling temperature in a temperature control system. The method includes providing a temperature control system including a controller, a first contactor assembly having a first channel system, a plurality of first contacts, each of the first contacts including a portion that is disposed within the first channel system, and one or more of a first exhaust valve or a first inlet valve, and a second contactor assembly having a second channel system, a plurality of second contacts, each of the second contacts including a portion that is disposed within the second channel system, and one or more of a second exhaust valve or a second inlet valve. The method also includes receiving, by the first contactor assembly, a fluid at a first temperature. The method also includes receiving, by the second contactor assembly, the fluid at the first temperature.

The application relates to the technical field of testing and application of power semiconductors, in particular to a SiC MOSFET gate oxide layer reliability testing device and method. The device is provided with a high-voltage direct-current voltage power supply, an auxiliary direct-current voltage source, a signal generating device, a half-bridge testing circuit, a gate driving circuit, a load inductor, a load resistor and a measuring device, can significantly shorten the stress time required for device reliability evaluation, can more accurately describe the device threshold voltage drift characteristics under different drain-source voltage stresses, compared with the traditional static bias and gate switching stress test method, effectively introduces the influence of dynamic drain-source voltage and current, improves the accuracy of the model test result, and has certain application value for SiC MOSFET gate oxide layer reliability evaluation.

An inspection is performed to a semiconductor device including a source region formed on an upper surface side of a semiconductor substrate, a drain region formed on a lower surface side of the semiconductor substrate, a trench formed on an upper surface, and a gate electrode and a field plate electrode that are formed in the trench. In the inspection, the source electrode and the drain electrode are fixed to a ground potential, an offset voltage is applied to the field plate electrode, and a screening voltage is applied to the gate electrode. Consequently, insulation properties between the source region and the gate electrode and insulation properties between the gate electrode and the field plate electrode are inspected.

The invention discloses an OLED module aging life test system, and relates to the technical field of OLEDs, and the system comprises the following steps: carrying out OLED module stress condition division and equivalent stress dose modeling; calculating the equivalent life of the OLED module on different stress paths; performing multi-dimensional quantitative characterization to obtain a color shift coupling degradation index; carrying out life threshold mapping and dynamic life calculation to obtain equivalent residual life; performing degradation path inversion to obtain a mechanism sensitive factor; and constructing an evaluation model, and rating a test result. According to the invention, complete chain type parameter transmission from stress application, optical measurement and degradation quantification to life prediction and mechanism discrimination is realized; the system not only can form a unified degradation evaluation dimension under different voltage, current and temperature conditions, but also can integrate brightness, color cast and life indexes into a multi-dimensional evaluation system, and greatly improves the precision and stability of OLED module life prediction.

A power device system comprising: a power device and a controller, the power device comprising: a power switch; and a control terminal driver, and wherein the power device is configured to operate in both a ramp-up and ramp-down diagnostic mode in which the control terminal driver is respectively configured to: apply a test current at the first node of the conduction channel of the power switch; apply a first driver voltage that is less than or greater than the threshold voltage at control terminal of the power switch; increase or decrease, respectively, the first driver voltage until a voltage drop or voltage increase, respectively is detected; and measure the first driver voltage at which the voltage drop is detected as a ramp-up threshold voltage or ramp-down threshold voltage, respectively, wherein the controller is configured to determine a state of health of the power switch based on the ramp-up threshold voltage and the ramp-down threshold voltage.

The present invention relates to a semiconductor package test device using a Peltier element, the device comprising a Peltier chamber unit in which a thermoelectric block located at a lower portion of a first Peltier block comprising a Peltier element comes into contact with an upper portion of a semiconductor package and changes the temperature of the upper portion of the semiconductor package, a socket guide that guides the semiconductor package and is located on a test board, and a pad part on an upper portion of which an electrical connection part coupled to an input / output terminal of a lower portion of the semiconductor package is provided, and which is located on the test board.

The invention discloses a system and method for detecting the junction temperature of LD chips in batches in real time, the system comprises aging and testing equipment, an MEMS optical switch, an acousto-optic tunable filter and a PD, the aging and testing equipment comprises a plurality of aging testing modules, the system further comprises a real-time operation, processing and control unit RTOPCU, and the real-time operation, processing and control unit RTOPCU is connected with the MEMS optical switch, the acousto-optic tunable filter and the PD. The control module is also used for controlling the COS unit of each aging test module to output laser, controlling the switching from the multi-path optical fiber input of the MEMS optical switch to the single-path optical fiber output of the MEMS optical switch, and controlling the input voltage of the acousto-optic tunable filter; filtering the multi-wavelength laser output of the MEMS optical switch to obtain a single-wavelength laser output signal corresponding to the input voltage of the MEMS optical switch; synchronously receiving a PD output voltage value obtained by detecting, amplifying and converting the laser signal output by the tunable filter converted by the PD; and calculating the junction temperature of the current COS unit under the condition that the PD output voltage value is not less than the threshold voltage value.

The invention relates to a high-temperature reverse bias test method and a cooling method, and relates to the technical field of semiconductors. The high-temperature reverse bias test method comprises the following steps: firstly, heating a to-be-tested module to a preset temperature T, keeping the temperature for a preset time, enabling the junction temperature Tj to be the same as the shell temperature Tc, applying a preset pulse voltage to the to-be-tested module, and collecting leakage current IR data at different temperatures T; performing linear fitting on the obtained leakage current IR and temperature T data to obtain a function relationship between ln (IR) and 1 / T; heating the to-be-tested module to a temperature close to a target test temperature, applying a test voltage VR to the to-be-tested module, collecting leakage current IR data and a reference point temperature Tref, and after the leakage current IR is stable, calculating a junction temperature Tj according to the fitting curve so as to obtain a thermal resistance value Rth of the system; and finally starting the test, and adjusting the temperature of the to-be-tested module by using the temperature control device, so that the junction temperature Tj of the to-be-tested module reaches the highest junction temperature and is kept constant. Thermal resistance calibration is carried out based on a temperature-sensitive electrical parameter method, the problem of thermal resistance calibration is solved, and accurate measurement of junction temperature is realized.

This improves the reliability of semiconductor devices equipped with MOSFETs having a double-gate structure including a gate electrode and a field plate electrode within a trench. [Solution] An inspection is performed on a semiconductor device comprising a source region SR formed on the upper side of a semiconductor substrate SB1, a drain region formed on the lower side of the semiconductor substrate SB1, a trench TR formed on the upper surface, and a gate electrode GE and a field plate electrode FG formed within the trench TR. In this inspection, the source electrode and drain electrode are fixed at ground potential, an offset voltage is applied to the field plate electrode FG, and a screening voltage is applied to the gate electrode GE. This allows for the inspection of the insulation between the source region SR and the gate electrode GE, and the insulation between the gate electrode GE and the field plate electrode FG.

The invention relates to an aging parameter determination method and device of a physical model, equipment and a medium. The method comprises the following steps: acquiring a voltage characteristic curve of a target device in a physical model at a constant temperature and different voltage stresses; determining electric field acceleration data of the target device according to the voltage characteristic curve; the electric field acceleration data is used for representing the influence degree of voltage stress on the aging speed of the target device; acquiring a temperature characteristic curve of the target device under the last voltage stress and different temperature values; the temperature characteristic curve is used for representing the incidence relation between the application time of different temperatures and the corresponding temperature values; determining target activation energy of the target device according to the temperature characteristic curve; the target activation energy is used for representing an energy upper limit value required by aging of the target device; and determining the aging time of the target device according to the target activation energy and the electric field acceleration data. By adopting the method, the aging parameters of the physical model can be accurately determined.

The invention provides a cartridge comprising a socket made of insulative material and having upper and lower sides, the upper side having a first formation for releasably holding a first electronic device, the socket having a first socket thermal opening formed from the lower side to the upper side through the socket, an interface connected to the socket to connect the first electronic device to an electric tester, a chuck of a thermally conductive material, a first thermal post attached to the chuck, the first thermal post being inserted into the first socket thermal opening, an end of the first thermal post being thermally connected to and in contact with the first electronic device, such that heat transfers primarily through the first thermal post as opposed to the insulative material of the socket between the chuck and the first electronic device, and a first set of contacts held in the socket and connecting terminals of the first electronic device to the interface, the first set of contacts being resiliently depressible to bring the first electronic device into contact with the end forming a first thermal surface of the first thermal post.

The application belongs to the technical field of space traveling wave tubes, and specifically provides a radiation cooling type space traveling wave tube aging method and system, which comprises a radiation radiator heating aging step. In the radiation radiator heating aging step, the radiation cooling type space traveling wave tube is first powered and heated; then the radiation radiator is heated and the surface temperature thereof is raised to a set value; and then the surface temperature of the radiation radiator is kept at the set value, the input signal power state and / or the working voltage pull-off value of the space traveling wave tube are adjusted, and the aging of the radiation cooling type space traveling wave tube under different working states is sequentially completed. The aging method and system only need to heat the radiation radiator, and can reduce the cost of the aging of the radiation cooling type space traveling wave tube.