217 results about "Stress mode" patented technology

A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.

The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NBTI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test (DUT). The inverter assures the proper 180 degree phase relationship between the test device source and gate voltage while the imbedded electronic switches provide isolation of the test device during DC characterization testing. Another embodiment of the invention enables the testing of multiple devices under test (DUT's).

A bending fracture limit stress [sigma]cr is calculated for each bending radius R at plate thickness center / initial plate thickness t0 of a metal plate. A fracture limit stress [sigma]1_pl under plane strain deformation is calculated, as is a fracture limit line L1 in a uniform deformation state in a stress space for which a static strain rate is assumed from work hardening characteristics obtained from uniaxial tensile testing of the material constituting the metal plate. A determination is made of the ratio [gamma] between the bending fracture critical stress [sigma]cr and the plane strain fracture limit stress [sigma]1_pl in a uniform deformation state that corresponds to the R / t0 of a determination subject element in the metal plate. The ratio [gamma] is multiplied by the stress component of the fracture limit line L1, whereby a fracture limit line L2 corresponding to R / t0 is calculated. The maximum principal stress [sigma]OBcr of the determination subject element is calculated from the maximum principal stress [sigma]OR of the determination subject element and the fracture limit line L2 corresponding to R / t0 in a stress mode. A risk ratio [sigma]OR / [sigma]OBcr, which is the risk ratio for tensile bending fracture, is calculated from the sizes of the stress [sigma]OR and the fracture limit stress [sigma]OBcr. Fracture is determined for the determination subject element on the basis of the risk ratio [sigma]OR / [sigma]OBcr.