33 results about "Positive bias temperature instability" patented technology

A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.

The invention discloses a forming method of a metal gate, a forming method of an MOS (metal oxide semiconductor) transistor and a forming method of a CMOS (complementary metal oxide semiconductor) structure. The forming method of the metal gate comprises the following steps: after removing a pseudo polycrystalline silicon gate and forming a groove, forming high-K gate medium layers at the bottom and on the side wall of the groove, fluoridizing the high-K gate medium layers, and forming a function layer and a metal layer on the surfaces of the high-K gate medium layers. As fluorine bonds such as fluorine-silicon bonds and fluorine-hafnium bonds can be formed among the high-K gate medium layers and a semiconductor substrate after fluoridization and the bond energy of the fluorine bonds is higher than that of original hydrogen bonds, the instability of the negative bias temperature of a device is reduced; as fluorine is strong in oxidability, oxygen vacancies can be prevented from generating donor level in a band gap and becoming positively charged oxygen vacancies, the oxygen vacancies are passivated, and the instability of the positive bias temperature of the device is reduced.

A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.

The invention belongs to the technical field of integrated circuit test, and in particular relates to a circuit and a method for testing reliability of an integrated circuit. According to the core circuit of the testing circuit, auxiliary p-type metal oxide semiconductor field effect transistors (pMOSFETs) and n-type metal oxide semiconductor field effect transistors (nMOSFETs) are connected between every two stages of inverters of a ring oscillator (RO) and between a high level Vdd and low potential Vss, and a switch transistor is plugged in an input and output connecting line. By controlling the grid voltages of the auxiliary transistors and the switch transistor, normal oscillation of the RO can be realized in the core circuit, dynamic stress is applied to complementary metal oxide semiconductor field effect transistors (CMOSFETs) of the RO, and negative bias temperature instability (NBTI), positive bias temperature instability (PBTI) and hot carrier injection (HCI) stresses are respectively applied to the pMOSFETs or the nMOSFETs of the RO. The testing circuit has the functions of: degradation measurement of the pMOSFETs in the RO under the NBTI stress, degradation measurement of the nMOSFETs under the PBTI stress, degradation measurement of the pMOSFETs under the HCI stress, degradation measurement of the nMOSFETs under the HCI stress, and comparison with degradation measurement of the CMOSFETs under the dynamic stress.

A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and / or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and / or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line / ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.

A logic circuit is operated in a normal mode, with a supply voltage coupled to a supply rail of the logic circuit, and with a ground rail of the logic circuit grounded; It is determined that at least a portion of the logic circuit has experienced degradation due to bias temperature instability. Responsive to the determining, the logic circuit is operated in a power napping mode, with the supply voltage coupled to the ground rail of the circuit, with the supply rail of the circuit grounded, and with primary inputs of the circuit toggled between logical zero and logical one at low frequency. A logic circuit and corresponding design structures are also provided.

A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (Vtrip) screens are provided. Each of the n-channel transistors in the CMOS SRAM cells are formed within p-wells that are isolated from p-type semiconductor material in peripheral circuitry of the memory and other functions in the integrated circuit. Forward and reverse body node bias voltages are applied to the isolated p-wells of the SRAM cells under test to determine whether such operations as read disturb, or write cycles, disrupt the cells under such bias. Cells that are vulnerable to threshold voltage shift over time can thus be identified.

A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying Negative / Positive Bias Temperature Instability (N / PBTI) compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N / PBTI compensation margins applied to the delay values. The method further includes identifying at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage, and applying reduced N / PBTI compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.

The invention discloses a testing device and a testing method used for an NMOS (n-channel metal oxide semiconductor) transistor in a high-k metal gate. The testing device comprises a resistor and a diode. The resistor is connected between an input end and an output end of the testing device, a positive pole of the diode is used for being connected with a bias voltage source, a negative pole of the diode is connected to the output end of the testing device, the input end of the testing device is used for receiving testing signals, and the output end of the testing device is used for connecting the gate of a to-be-tested NMOS transistor. The testing device is capable of exerting stress upon the to-be-tested NMOS transistor continuously and automatically during the PBTI (positive bias temperature instability) testing process, so that the problem of restoration effect during the PBTI testing process can be effectively solved; besides, the testing device is easy to operate and basically free of additional hardware, thereby being low in cost.

The invention belongs to a integrated circuit reliability test technology field and especially relates to a multifunctional test circuit of integrated circuit stress degradation and a test method thereof. A core part of the test circuit takes an annular oscillator as a basis. Several auxiliary transistors, switch transistors and control terminals are added. By using the circuit and the method of the invention, a negative bias temperature instability, a positive bias temperature instability, hot hole injection or hot electron injection stress can be applied to pMOSFETs or nMOSFETs in a ring vibration inverter respectively; a ring oscillator is in a normal oscillation and stress oscillation state; the pMOSFETs or nMOSFETs of the inverter in the ring oscillator is in a measuring state of a charge pump. The degradation of the MOSFETs in the ring vibration inverter can be shown through changes of a ring oscillator oscillation frequency after the stress and can be shown through the changes of a CP current (Icpp or Icpn) of the pMOSFETs or nMOSFETs in the ring oscillator.

Provided are a restoring circuit and restoring method against positive bias temperature instability. The restoring circuit comprises a to-be-restored N-channel metal oxide semiconductor (NMOS) transistor and a restoring unit. A grid electrode of the to-be-restored NMOS transistor is connected with the restoring unit. According to the restoring unit, a grid electrode of a switch transistor is connected with a signal input end, a drain electrode of the switch transistor is connected with a first voltage end, the first voltage end provides a negative first working voltage, a substrate of the switch transistor is connected with a second voltage end, a source electrode of the switch transistor is connected with one end of a second resistor, the other end of the second resistor is connected with a signal output end, one end of a first resistor is connected with a signal input end, and the other end of the first resistor is connected with the signal output end. Due to the fact that the voltage of the first voltage end is negative, by adjusting resistance values of the first resistor and the second resistor, grid electrode voltage applied to the to-be-restored NMOS transistor can be negative pressure, and good positive bias temperature instability (PBTI) characteristic restoration effect can be achieved.

A method and apparatus for calculating delay timing values for at least a part of an integrated circuit design. The method comprises applying a first Negative / Positive Bias Temperature Instability compensation margin to delay values for elements within the at least part of the IC design, identifying at least one lower-rate switching element within the at least part of the IC design, and applying at least one further, increased N / PBTI compensation margin to the delay value(s) for the at least one identified lower-rate switching element.