5 results about "Negative-bias temperature instability" patented technology

The invention relates to a test method for a total dose irradiation and negative bias temperature instability coordination effect of a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor), which comprises the steps of test sample selection and parameter test, superposition test, comprehensive test and data processing. The method comprises a total dose and negative bias temperature instability sequential superposition test and a comprehensive test, and test data comparison is provided in data processing. According to the method provided by the invention, the influence of the total dose irradiation on the negative bias temperature instability, the influence of the negative bias temperature instability on the total dose effect and the characteristic change of the device under the comprehensive action condition can be obtained. The interaction rule and mechanism of the total dose effect and the negative bias temperature instability are obtained, and a basis is provided for performance evaluation and reliable application of small-size devices in a radiation environment.

The invention provides a method for improving negative bias temperature instability of a PMOS (P-channel Metal Oxide Semiconductor) device, which is characterized in that a silicon nitride thin film layer with tensile stress is prepared by adopting a furnace tube deposition process, the silicon nitride furnace tube deposition process is characterized in that a reaction gas source is heated and decomposed at high temperature to carry out chemical reaction, and ions in the process belong to thermal motion; therefore, the surface of the substrate does not have large acceleration, bombardment of reaction source ions to the gate dielectric layer of the PMOS device in the chemical reaction process can be effectively reduced or even avoided, the risk of damage to the gate dielectric layer of the PMOS device is reduced, and the effect of improving NBTI of the PMOS device is achieved.

This application discloses a test execution method for negative bias temperature instability testing, belonging to the field of semiconductor technology. Addressing the technical problem of long test times and the need for extrapolation in negative bias temperature instability testing of semiconductor devices, this application, based on the power-law lifetime model of semiconductor devices, maps the standard test conditions for negative bias temperature instability testing to rapid test conditions with faster decay rates and no need for heating by increasing the gate voltage amplitude. This reduces the test time and heating time for semiconductor devices in negative bias temperature instability testing, thereby accelerating the testing process. Furthermore, in the equivalent process, the degradation degree of the semiconductor device under rapid test conditions and the rapid test time is equivalent to the degradation degree that occurs when operating under standard test conditions to the target lifetime. This allows the test results to be directly used as the evaluation index of the device at the target lifetime after the test is completed, without the need for further derivation.

A method for forming a semiconductor structure, comprising: providing a substrate; forming a gate oxide layer and a gate dielectric layer on the substrate, the gate dielectric layer and the gate oxide layer having a first interface therebetween, incorporating a modifying ion at the first interface, the modifying ion being bonded with an ion in the gate dielectric layer or the gate oxide layer, forming a first chemical bond at the first interface, the first chemical bond having a stronger bond strength than before the modifying ion is incorporated, the first chemical bond formed by a defect ion and an ion in the gate dielectric layer (or the gate oxide layer) at the first interface being less likely to be broken, reducing the probability of interface trap charge, thereby reducing the interface state density, reducing the threshold voltage and the saturated drain current of the device from drifting, and improving the negative bias temperature instability.

The invention discloses a test execution method for a negative bias temperature instability test, and belongs to the technical field of semiconductors. The method aims at solving the technical problems that the testing time of a semiconductor device is long and calculation is needed in a negative bias temperature instability test. According to the power law life model based on the semiconductor device, a standard test condition of a negative bias temperature instability test is mapped into a rapid test condition which can be faster in attenuation rate and does not need temperature rise by improving the grid voltage amplitude, so that the test time and the temperature rise time of the semiconductor device in the negative bias temperature instability test are shortened; and the test process of the semiconductor device is accelerated. Besides, during equivalence, the degeneration degree of the semiconductor device generated by the fast test time based on the fast test condition is equivalent to the degeneration degree generated when the semiconductor device runs to the target service life under the standard test condition; therefore, after the test of the semiconductor device is completed, the test result can be directly used as the evaluation index of the device during the target life, and secondary derivation is not needed.