17 results about "Negative-bias temperature instability" patented technology

The invention relates to a test method for a total dose irradiation and negative bias temperature instability coordination effect of a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor), which comprises the steps of test sample selection and parameter test, superposition test, comprehensive test and data processing. The method comprises a total dose and negative bias temperature instability sequential superposition test and a comprehensive test, and test data comparison is provided in data processing. According to the method provided by the invention, the influence of the total dose irradiation on the negative bias temperature instability, the influence of the negative bias temperature instability on the total dose effect and the characteristic change of the device under the comprehensive action condition can be obtained. The interaction rule and mechanism of the total dose effect and the negative bias temperature instability are obtained, and a basis is provided for performance evaluation and reliable application of small-size devices in a radiation environment.

The invention relates to a threshold voltage initial value determination method and device, computer equipment and a medium. The method comprises the following steps: acquiring a plurality of initial transfer characteristics when an initial bidirectional voltage waveform is applied to a target transistor, and under the condition that hysteresis of each initial transfer characteristic is in an unstable state, adjusting a termination input voltage of the target transistor to obtain an adjusted termination input voltage, determining an adjusted bidirectional voltage waveform of the target transistor according to the adjusted termination input voltage and the initial input voltage, obtaining a plurality of adjusted transfer characteristics when the adjusted bidirectional voltage waveform is applied to the target transistor, and adjusting the target transistor when the hysteresis of each adjusted transfer characteristic is in a stable state. And determining the threshold voltage initial value of the target transistor according to each adjusted transfer characteristic. By adopting the method, the initial value of the threshold voltage of the target transistor with relatively high precision can be determined through the transfer characteristic of the stable state so as to support the research on the negative bias temperature instability of the target transistor.

The invention provides a method for improving negative bias temperature instability of a PMOS (P-channel Metal Oxide Semiconductor) device, which is characterized in that a silicon nitride thin film layer with tensile stress is prepared by adopting a furnace tube deposition process, the silicon nitride furnace tube deposition process is characterized in that a reaction gas source is heated and decomposed at high temperature to carry out chemical reaction, and ions in the process belong to thermal motion; therefore, the surface of the substrate does not have large acceleration, bombardment of reaction source ions to the gate dielectric layer of the PMOS device in the chemical reaction process can be effectively reduced or even avoided, the risk of damage to the gate dielectric layer of the PMOS device is reduced, and the effect of improving NBTI of the PMOS device is achieved.

The invention relates to a manufacturing method of a CMOS (Complementary Metal Oxide Semiconductor) device, which optimizes the manufacturing process of a tensile stress film and a compressive stress film and ensures that an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor) can adopt a stress technology at the same time. The stress films (the tensile stress film and the pressure stress film) corresponding to the NMOS area and the PMOS area are subjected to ultraviolet curing treatment, H in the films is removed, the H is prevented from entering the device during subsequent annealing, the short-channel effect is weakened, the negative bias temperature instability is relieved, the device performance is improved, and the reliability of the device during working is guaranteed.

The invention belongs to the technical field of integrated circuits, and particularly relates to a high-cardinal-number on-chip interconnection reliability optimization method. According to the method, the port combination problem of the multi-stage on-chip interconnection is abstracted into the combination optimization problem of boxing distribution, port redistribution is carried out through the genetic evolutionary algorithm to balance the flow in the multi-stage on-chip interconnection, and the reliability bottleneck caused by flow imbalance is effectively avoided. According to the method, a multi-stage on-chip interconnection physical model is established to evaluate the key path, a multi-stage on-chip interconnection port utilization rate calculation method is combined, gate delay offset on the key path caused by a negative bias temperature instability (NBTI) effect can be analyzed, the service life of a key gate is prolonged by scaling the size of the key gate on the key path, and the method is suitable for the multi-stage on-chip interconnection port utilization rate calculation. And the reliability of the whole circuit is optimized.

This application discloses a test execution method for negative bias temperature instability testing, belonging to the field of semiconductor technology. Addressing the technical problem of long test times and the need for extrapolation in negative bias temperature instability testing of semiconductor devices, this application, based on the power-law lifetime model of semiconductor devices, maps the standard test conditions for negative bias temperature instability testing to rapid test conditions with faster decay rates and no need for heating by increasing the gate voltage amplitude. This reduces the test time and heating time for semiconductor devices in negative bias temperature instability testing, thereby accelerating the testing process. Furthermore, in the equivalent process, the degradation degree of the semiconductor device under rapid test conditions and the rapid test time is equivalent to the degradation degree that occurs when operating under standard test conditions to the target lifetime. This allows the test results to be directly used as the evaluation index of the device at the target lifetime after the test is completed, without the need for further derivation.

The present application relates to a semiconductor structure and a method for preparing the same, including a first passivation layer and a stacked structure; the stacked structure is located on the upper surface of the first passivation layer and includes a second passivation layer and a hydrogen absorption layer stacked in sequence from bottom to top; wherein hydrogen elements are generated during the formation of the second passivation layer, and the hydrogen absorption layer adsorbs the hydrogen elements generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment. In the semiconductor structure of the present application, the hydrogen absorption layer adsorbs the hydrogen elements generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment, avoiding the problem of negative bias temperature instability caused by a large number of unstable covalent bonds formed due to the entry of hydrogen elements into the device interface, and improving the stability and reliability of the semiconductor structure performance.

The voltage at the input of an electronic device is regulated by performing at least the following: receiving a monitoring voltage corresponding to a power system at a voltage monitoring circuit (210), determining at the voltage monitoring circuit whether the monitoring voltage is equal to or exceeds a monitoring threshold voltage, (204) receiving an output at the voltage monitoring circuit indicating whether an input reference voltage at a comparator circuit is different from an input feedback voltage, (218) adjusting a feedback voltage at the voltage monitoring circuit to match the input reference voltage, (204), and providing the feedback voltage from the voltage monitoring circuit to the comparator circuit (220) as an updated input feedback voltage.

A p-channel metal oxide semiconductor (pMOS) transistor includes a gate stack, the gate stack including: a dielectric interlayer containing silicon oxide on a substrate, wherein the thickness of the dielectric interlayer is less than 1 nm; a high-k dielectric layer having a higher dielectric constant than the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting the high-k bandgap of the high-k dielectric layer downward relative to the valence band of the substrate, wherein the thickness of the first dipole-forming capping layer is less than 2 nm; and at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and high reliability without the use of reliability annealing, which makes the pMOS transistor suitable for use as a back-end-of-line (BEOL) device.

The embodiment of the present disclosure provides a protection circuit, a protection method and a semiconductor memory, the protection circuit comprising a power supply module, a switch module and a delay phase-locked loop module, wherein: one end of the switch module is connected with the power supply module, the other end of the switch module is connected with the delay phase-locked loop module, and the control end of the switch module receives a mode control signal, and the mode control signal is used for controlling the switch module to be in an off state in an aging mode, so that the power supply module is disconnected with the delay phase-locked loop module. In this way, by receiving the mode control signal at the control end of the switch module, the switch module is in the off state in the aging mode, so that the power supply module is disconnected with the delay phase-locked loop module, so that the delay phase-locked loop module can be prevented from accelerating voltage, the protection of the delay phase-locked loop module under the negative bias temperature instability effect can be realized, and the test power consumption can be reduced.

The application relates to a threshold voltage initial value determination method and device, computer equipment and a medium. The method comprises the following steps: obtaining multiple preliminary transfer characteristics of a target transistor when an initial bidirectional voltage waveform is applied to the target transistor; in the case that the hysteresis of each preliminary transfer characteristic is in an unstable state, adjusting the terminal input voltage of the target transistor to obtain an adjusted terminal input voltage, and determining an adjusted bidirectional voltage waveform of the target transistor according to the adjusted terminal input voltage and a starting input voltage; obtaining multiple adjusted transfer characteristics of the target transistor when the adjusted bidirectional voltage waveform is applied to the target transistor; and in the case that the hysteresis of each adjusted transfer characteristic is in a stable state, determining the threshold voltage initial value of the target transistor according to each adjusted transfer characteristic. The threshold voltage initial value of the target transistor with high precision can be determined through the stable-state transfer characteristic, so as to support the research on the negative bias temperature instability of the target transistor.

The invention provides a preparation method of a metal oxide semiconductor (MOS) device, which comprises the following steps of: firstly, providing a substrate, forming a gate oxide layer on one side of the substrate, then injecting deuterium plasma or fluorine plasma between the substrate and the gate oxide layer by adopting a decoupling plasma injection method, and finally, carrying out annealing treatment. The deuterium plasma or the fluorine plasma is bonded with silicon between the substrate and the gate oxide layer to generate a silicon-deuterium bond or a silicon-fluorine bond with higher bond energy; according to the decoupling plasma injection method, the injection depth and the injection amount of the deuterium plasma or the fluorine plasma can be well controlled, annealing treatment is performed after the deuterium plasma or the fluorine plasma is injected, and deuterium or fluorine can replace hydrogen to form a silicon-deuterium bond or a silicon-fluorine bond with the silicon between the substrate and the gate oxide layer, and the bond energy of the silicon-deuterium bond or the silicon-fluorine bond is larger than that of a silicon-hydrogen bond. And silicon-hydrogen bond fracture and hydrogen diffusion at the interface of the gate oxide layer and the substrate are improved, so that the negative bias temperature instability effect of the MOS device is improved.

A method for forming a semiconductor structure, comprising: providing a substrate; forming a gate oxide layer and a gate dielectric layer on the substrate, the gate dielectric layer and the gate oxide layer having a first interface therebetween, incorporating a modifying ion at the first interface, the modifying ion being bonded with an ion in the gate dielectric layer or the gate oxide layer, forming a first chemical bond at the first interface, the first chemical bond having a stronger bond strength than before the modifying ion is incorporated, the first chemical bond formed by a defect ion and an ion in the gate dielectric layer (or the gate oxide layer) at the first interface being less likely to be broken, reducing the probability of interface trap charge, thereby reducing the interface state density, reducing the threshold voltage and the saturated drain current of the device from drifting, and improving the negative bias temperature instability.

Examples of input stages of circuits are configured to reduce both negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) in PMOS transistors therein. Current-switched PMOS source follower transistors and a low-side NMOS differential pair is used to process a lower range of a rail-to-rail input signal range of a circuit. A PMOS source follower is disposed between the positive input of the circuit and the positive input of the low-side NMOS differential pair. Another PMOS source follower is disposed between the negative input of the circuit and the negative input of the low-side NMOS differential pair. Various arrangements are provided for generating and maintaining the bias currents of the two PMOS source followers to be approximately the same through the entire lower input signal range.

The invention provides a threshold voltage adjusting method and manufacturing method of a semiconductor device and the semiconductor device, and the adjusting method comprises the steps: providing a substrate, and forming a gate oxide layer in the semiconductor device on the substrate; and performing hydrogen plasma treatment on the gate oxide layer to adjust the effective work function of the semiconductor device. The effective work function of the semiconductor device is adjusted by performing hydrogen ion treatment on the gate oxide layer, so that the threshold voltage of the semiconductor device is adjusted, meanwhile, the negative bias temperature instability can be improved, and compared with the prior art, the threshold voltage adjusting efficiency is improved, the performance of the semiconductor device is improved, and the manufacturing cost of the semiconductor device is reduced. And the service life of the semiconductor device is prolonged.

The invention relates to the technical field of semiconductor detection, in particular to a threshold voltage variation determination method and device, computer equipment and a storage medium. The method comprises the following steps: increasing the gate voltage of a target device from a discharge voltage to a candidate voltage, determining a corresponding detection current value after the gate voltage of the target device reaches the candidate voltage, and recovering the gate voltage of the target device from the candidate voltage to the discharge voltage; and determining a threshold voltage variation corresponding to the target equipment according to the detected current value. When the current value corresponding to the stress voltage is obtained, the influence of defective charging is reduced, the detection current value determination accuracy is improved, the situation that the detection current value is underestimated is prevented, an accurate data basis is provided for subsequent determination of the threshold voltage variation, and the detection accuracy is improved. Therefore, the threshold voltage variation can accurately reflect the degradation condition of the negative bias temperature instability effect, and NBTI degradation better conforms to the actual condition of target equipment.

The invention discloses a test execution method for a negative bias temperature instability test, and belongs to the technical field of semiconductors. The method aims at solving the technical problems that the testing time of a semiconductor device is long and calculation is needed in a negative bias temperature instability test. According to the power law life model based on the semiconductor device, a standard test condition of a negative bias temperature instability test is mapped into a rapid test condition which can be faster in attenuation rate and does not need temperature rise by improving the grid voltage amplitude, so that the test time and the temperature rise time of the semiconductor device in the negative bias temperature instability test are shortened; and the test process of the semiconductor device is accelerated. Besides, during equivalence, the degeneration degree of the semiconductor device generated by the fast test time based on the fast test condition is equivalent to the degeneration degree generated when the semiconductor device runs to the target service life under the standard test condition; therefore, after the test of the semiconductor device is completed, the test result can be directly used as the evaluation index of the device during the target life, and secondary derivation is not needed.