Method for testing reliability of semiconductor devices

A semiconductor and reliability technology, applied in the field of non-destructive rapid testing of pMOSFET negative bias temperature instability, can solve problems such as time-consuming workload of NBTI testing, degradation of electrical parameters of device samples, and inability to continue to use, etc. Achieve the effect of reducing test time, significant efficiency, and improving efficiency

Inactive Publication Date: 2011-05-25
PEKING UNIV
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  • Application Information

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Problems solved by technology

[0007] As a result, routine NBTI testing is a time-consuming and labor-intensive endeavor
Moreover, the electrical parameters of the device samples after the NBTI stress test have undergone serious degradation and cannot be used any longer.

Method used

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  • Method for testing reliability of semiconductor devices
  • Method for testing reliability of semiconductor devices
  • Method for testing reliability of semiconductor devices

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Embodiment Construction

[0019] The inventor found and established the initial stage V of the NBTI curve of pMOSFET th The correlation between the degradation value and the amplitude of the power spectral density of 1 / f noise, and based on this, a new method for testing the reliability of semiconductor devices is proposed.

[0020] Research on the NBTI mechanism has been going on for more than 40 years. At present, it is generally believed that the physical mechanism of NBTI is the interface state N it And filled near-interface bulk charge trap N t The combined effect of For the generation of the interface state, the more recognized reaction-diffusion model and its modified model believe that the fracture reaction of the Si-H bond at the interface and the subsequent dimerization and diffusion of H particles in the dielectric layer work together to cause the threshold voltage to drift. The index changes with time; since the interface reaction and dimerization are rapid, the subsequent degradation will be ...

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Abstract

The invention discloses a method for testing reliability of semiconductor devices which have negative bias temperature instability (NBTI). The method comprises the following steps: measuring the NBTI curve of a first set of semiconductor devices; measuring the 1 / f noise power spectral density and drain current of the first set of semiconductor devices at a predetermined frequency under the condition that the first set of semiconductor devices is biased in a gate electric field; measuring the equivalent oxide layer thickness of the gate dielectric of the first set of semiconductor devices; measuring the 1 / f noise power spectral density and drain current of a second set of semiconductor devices at the predetermined frequency under the condition that the second set of semiconductor devices is biased in the gate electric field; measuring the equivalent oxide layer thickness of the gate dielectric of the second set of semiconductor devices; and evaluating the deterioration characteristic of the second set of semiconductor devices by using the NBTI curve of the first set of semiconductor devices. The method disclosed by the invention saves the time required for testing the reliability of a large number of semiconductor devices, and can not damage the second set of semiconductor devices.

Description

Technical field [0001] The present invention relates to a method for testing the reliability of semiconductor devices and circuits, in particular to a method for non-destructive and rapid testing of the negative bias temperature instability (NBTI) of pMOSFET. Background technique [0002] The reliability test of semiconductor devices is a key technical issue in the field of integrated circuit technology. The negative bias temperature instability (NBTI) of the p-type field effect transistor (pMOSFET) in CMOS circuits is one of the main reliability problems in semiconductor devices. Its performance is that the p-type field effect transistor (pMOSFET) is in the negative gate The threshold voltage V of the device under voltage and temperature stress conditions th And leakage current I d Isoelectric parameters will continue to degrade over time, eventually making the device unable to work normally. [0003] With the continuous reduction of device size and the continuous thinning of the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/26
Inventor 刘晓彦杨佳琦康晋锋杨竞峰韩汝琦陈冰
Owner PEKING UNIV
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