53 results about "Negative bias" patented technology

The invention discloses a preparation method of a thin film transistor. The core of the preparation method is to construct a quasi-double-channel structure. Taking an insulating layer of the thin film transistor as a first metal oxide, and processing the surface of the insulating layer to obtain an oxygen-deficient surface; depositing a second metal oxide on the anoxic surface as a channel layer; a metal-oxygen bond of the insulating layer is higher than a metal-oxygen bond of the channel layer; and after the deposition of the second metal oxide is finished, a two-dimensional oxygen-deficient surface is spontaneously formed on the contact surface of the insulating layer and the channel layer through annealing treatment, so that the thin film transistor with the quasi-double-channel structure is obtained. Compared with a traditional thin film transistor, the thin film transistor has the advantages that the positive bias voltage stability and the negative bias voltage stability are obviously improved, and meanwhile, the mobility is greatly improved. The invention has the characteristics of high carrier mobility, small threshold voltage drift and high long-term working reliability, and is simple in preparation process and low in cost. The quasi-double-channel structure is expected to be widely applied to oxide thin film transistors.

The invention relates to the technical field of direct-current power supply management and fault monitoring, and discloses a multi-dimensional abnormity early warning monitoring method and system in direct-current power supply management, and the method comprises the steps: configuring a passive induction sheet in a central region of the top end surface of an explosion-proof valve of an electrolytic capacitor in a direct-current power supply; determining a signal acquisition pair between the passive induction sheet and the cathode of the electrolytic capacitor, and connecting a negative bias ADC channel and a polarity ADC channel in parallel on the signal acquisition pair; respectively monitoring a negative DC bias voltage signal and a polarity inversion signal of the signal acquisition pair through a negative bias voltage ADC channel and a polarity ADC channel; respectively analyzing the monotone increasing trend of the negative direct current bias voltage signal and the relaxation time of the polarity reversal signal; and based on the monotone increasing trend and the relaxation time, early failure early warning of the electrolytic capacitor in the direct-current power supply is realized. According to the invention, long-term, on-line and interference-free early warning of the early failure phenomenon of the electrolytic capacitor of the direct-current power supply can be realized under real working conditions.

The embodiment of the invention provides an array substrate, a preparation method of the array substrate and a display panel, and relates to the technical field of display, the array substrate comprises a substrate and a driving wiring layer, the driving wiring layer is located on one side of the substrate, and the driving wiring layer comprises a transistor; the driving wiring layer comprises a first active layer located on one side of the substrate, a first conductive layer located on the side, away from the substrate, of the first active layer and a first barrier layer located on the side, away from the substrate, of the first conductive layer, the first barrier layer comprises a first barrier part, the transistor comprises a first grid electrode and a first active part, and the first grid electrode is located on the first conductive layer; the first active part is located on the first active layer, and the orthographic projection of the first blocking part on the substrate is at least partially overlapped with the orthographic projection of the first active part on the substrate. The risk that the transistor generates channel negative bias can be reduced, so that the convergence of the transistor can be improved.

The application discloses a high-extraction-efficiency ion source structure and sealed neutron tube structure; a TiT thin film target is tightly attached to the inner wall of a closed shell; a target grid is tightly attached to the TiT thin film target, and a negative bias voltage is generated by loading a voltage between the target grid and the closed shell; plasma is generated after a voltage is loaded between a discharge anode and a discharge cathode; the scheme is based on the existing vacuum arc discharge ion source structure and is improved in structure; space is reserved between the discharge cathode and the anode grid for free expansion of the plasma, an open expansion space is provided for the plasma, most of the plasma generated by the discharge can expand into the acceleration zone to obtain energy and bombard the target surface, so that the arc current utilization rate can be increased to about 1%, and the neutron yield can be broken through 1*10 10 n / s.

The invention relates to a preparation method of a high-hardness ultra-smooth TiN coating, which comprises the following steps: putting a workpiece into a vacuum chamber, vacuumizing the vacuum chamber, and then introducing Ar to carry out ion cleaning on the surface of the workpiece; sequentially depositing a Cr layer and a Ti layer on the surface of the workpiece by adopting a radio frequency sputtering technology; a TiN layer is prepared on the surface of a workpiece by adopting a pure ion plating technology, when pure ion plating is carried out, mixed gas of Ar and N is introduced into a vacuum chamber, auxiliary ionization is carried out on the mixed gas in the vacuum chamber, negative bias voltage is applied to the workpiece, the ionization rate of a Ti target is improved by adopting a radio-frequency pulse power supply, and an ion beam is filtered by using a bent pipe magnetic filter. According to the TiN coating prepared through the method, the hardness can be stably higher than 3000 HV, the binding force on a high-speed steel base material is larger than 50 N, and the binding force with the base material is remarkably improved; the N content in the prepared TiN coating is larger than 45%, the ionization degree is very high, compactness is good, and the surface roughness Ra is smaller than 10 nm.

The carrier concentration of the drift region (87) is controlled in the semiconductor substrate in response to a voltage applied to the gate electrode (81) of the gate-controlled diode (203). In the reverse recovery state, a voltage signal of zero bias or positive bias that causes an electron layer at the interface of the gate electrode (81) is applied between the gate electrode (81) and the anode electrode (86). In the forward recovery state, a voltage signal of negative bias that causes a hole layer at the interface of the gate electrode (81) is applied between the gate electrode (81) and the anode electrode (86). After the forward recovery state, the voltage signal of zero bias or positive bias is switched from the negative bias. The gate-controlled diode (203) variably controls the period during which the voltage signal of zero bias or positive bias is applied in accordance with the non-conduction period of the IGBT connected in series therewith.

Embodiments of the present disclosure are directed to an isolation housing for an electro-hydrodynamic (EHD) air mover device. The isolation housing includes the EHD air mover device, a shield placed on top of the EHD air mover device forming an upper wall of the isolation housing, a printed circuit board (PCB) assembly forming a bottom wall of the isolation housing, and a chassis made of one or more non-conductive materials and forming side walls of the isolation housing. The PCB assembly carries signal connections for a positive bias voltage signal, a negative bias voltage signal, and / or a ground signal. The chassis is shaped to hold the EHD air mover device in a defined position within the isolation housing. A first surface of the chassis is affixed to the shield, and a second surface of the chassis opposite to the first surface is affixed to the PCB assembly.

An image sensor includes a photodiode that generates electric charges in response to light, a transfer transistor connected to the photodiode and a floating diffusion, a reset transistor connected between the floating diffusion and a power node, a boost capacitor connected to the floating diffusion and adjusting a capacity of the floating diffusion in response to a boost control signal, and a bias circuit having a first current circuit and a second current circuit for supplying different bias currents to an output node to which a voltage signal corresponding to electric charges accumulated in the floating diffusion is output. After the transfer transistor is turned off, the boost control signal is lowered from a high level to a low level, and the reset transistor is switched from an on state to an off state when the bias currents of the first current circuit and the second current circuit are simultaneously supplied to the output node.

The application provides a screening method, device, medium and equipment for an abnormal Flash chip. The method comprises the following steps: performing data abnormal voltage criticality test on a to-be-tested chip to determine a critical voltage value of the to-be-tested chip, wherein the to-be-tested chip is a to-be-tested Flash chip; determining whether the critical voltage value is greater than a voltage threshold value, wherein the voltage threshold value corresponds to a target gear of a negative bias voltage of the to-be-tested chip; and determining that the negative bias voltage of the to-be-tested chip is abnormal if the critical voltage value is greater than the voltage threshold value. In the case that the negative bias voltage cannot be directly measured, the safety of the negative bias voltage of the to-be-tested chip is evaluated from the side through the critical voltage value of the to-be-tested chip, so that the screening of the abnormal Flash chip is realized, and the accuracy of the screening result is ensured.

The application discloses a gate drive circuit and a driving method thereof. The gate drive circuit comprises an output control module, a first output module, a second output module and a threshold adjusting module. The threshold adjusting module is used for turning on in response to a first adjusting signal in a threshold adjusting stage, so as to transmit a first potential signal to a control end of the second output module. The second output module comprises a transistor. The threshold adjusting module transmits the first potential signal to the control end of the second output module in the threshold adjusting stage, so as to partially offset the positive or negative bias of the threshold voltage of the second output module caused by a high-temperature environment, and ensure the normal output of the output signal of the gate drive circuit.

The application discloses a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a light-emitting module, a driving module, a coupling module, a second voltage transmission unit and a voltage interval unit. The second voltage transmission unit is connected between a first power supply and a first end of the driving module, and is used for transmitting a voltage of the first power supply to the first end of the driving module in a compensation stage. A first end of the coupling module is connected with a control end of the driving module. The voltage interval unit is connected between a second end of the driving module and a second end of the coupling module, and is used for being turned on in the compensation stage, so that the first power supply charges the coupling module, and a threshold voltage of the driving module is written to the second end of the coupling module. Through the charging compensation mode, the dispersion of the threshold voltage of the driving module is compensated, the compensation of the positive or negative bias of the threshold voltage is realized, the display uniformity is improved, and the display effect is improved.

A first embodiment relates to an amplifier circuit including a positive bias circuit having a driving PMOS biased in subthreshold mode, a negative bias circuit having a driving NMOS biased in subthreshold mode, and an amplification circuit coupled to the bias circuit. The amplification circuit includes a first stage having a first boost stage, a second stage having a second boost stage, and a resistive element coupled between the first and second stages. A second embodiment relates to a folded cascaded operational amplifier, wherein the value of the resistive element is selected to place at least one of the driving MOS in subthreshold mode. A third embodiment relates to an integrated circuit having a resistive region adjacent to a first boost region and a second boost region, the resistive region including a resistive element directly connected to the driving PMOS and the driving NMOS. Embodiments of this application also relate to a folded cascaded operational amplifier and a method of operating the amplifier circuit.

The invention discloses a method and a system for deducting a hydrogen background of a helium mass spectrometer leak detector, and belongs to the technical field of helium mass spectrometer leak detectors. The positive and negative bias voltages are applied to the original acceleration voltage, so that the maximum value and the minimum value of the hydrogen ion signal are obtained, and the background value of the hydrogen ion signal at the peak value of the helium ion signal when the bias voltage is not applied can be estimated through the maximum value and the minimum value of the hydrogen ion signal. And the total ion signal is deducted from the total ion signal when the bias voltage is not applied, so that the detection result of the helium ion signal is more accurate.

The following disclosure relates to mitigating issues related to semi-circular drain side gate (SC-SGD) memory holes in a memory structure. When a memory hole is cut, the channel and charge trapping layer of the memory hole are cut. In addition, the outer dielectric layer (used to shield the channel and the charge trapping layer) is cut and partially removed. When a selected SC-SGD is selected for operation (e.g., programming), the channel and the charge trapping layer are exposed to an adjacent electric field from a bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electric field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, the present disclosure relates to a self-compensation technique for SC-SGDs. For example, the memory structure can utilize the adjacent electric field during verify, program, and read operations regardless of whether the adjacent electric field is relatively strong or weak.

The invention discloses a direct-current solid-state circuit breaker, a direct-current load and an electrically-driven remote-control submersible, belongs to the field of direct-current power systems, and aims to form a relatively high off-state resistance value through the off-state of a plurality of controllable sub-switches connected in series and to form a relatively high off-state resistance value through a voltage-sharing circuit arranged between the control ends of the adjacent controllable sub-switches. And negative bias voltage can be generated between'control ends and second ends' of the adjacent controllable sub-switches at the rear stage when the adjacent controllable sub-switches at the front stage are disconnected, so that a first switch module comprising a plurality of cascaded controllable sub-switches and voltage equalizing circuits in one-to-one correspondence with the controllable sub-switches is arranged; the driving module sends the driving voltage to the control ends of the controllable sub-switches of the first sequence in the first switch module when the circuit breaking requirement exists, so that the controllable sub-switches in the first switch module can be turned off, namely, the direct-current solid-state circuit breaker not only has high voltage endurance capability, but also is simple in driving mode.

The invention relates to the technical field of gas detectors, in particular to a microneedle array type gas detector. The microneedle array type gas detector comprises: a cathode plate, one side of which is provided with a boss in the central area and is used as a cathode; the anode plate and the cathode plate are arranged at an interval, and a plurality of microneedles are inserted into one side, facing the cathode plate, of the anode plate and are used as positive electrodes; the boss is loaded with a first negative bias voltage, and the micro-needle is kept at a zero potential, so that a drift electric field is formed between the boss and the micro-needle. According to the gas detector, the microneedle with the large curvature radius is adopted as the positive electrode, so that the intensity of an electric field near the needle tip is rapidly weakened along with the increase of the distance, the gas detector can stably operate under high gain, the counting rate performance of the gas detector can be improved, and the gas detector can be flexibly matched with electronics to expand the dynamic range of the gas detector.

This invention provides a pixel structure and its operating method for a radiation-hardened 4T CMOS image sensor. The pixel structure includes a transmission transistor, a reset transistor, a source follower, a row select transistor, an STI bias gate, a photodiode, a floating node, a shallow trench isolation region, and a P-type substrate. The photodiode is surrounded by a P-type substrate, which is enclosed by the shallow trench isolation region. A portion of the shallow trench isolation region is covered by an STI bias gate. The lower right corner of the photodiode is connected to one side of the transmission transistor, and the other side of the transmission transistor is connected to the floating node. The reset transistor, row select transistor, and source follower are sequentially connected after the floating node. The negative bias V of the STIX designed in this invention... STI negative bias V with TX TX The shutdown voltage effectively improves the radiation resistance of the device by suppressing the generation of interface state trap charges at the STI-pixel interface and the generation of dark current in the TX-PD overlap region under the TID effect.

The present application relates to the technical field of circuit fault diagnosis, and particularly relates to an inverter open circuit diagnosis method, system and device based on current dynamic scaling. The method comprises the following steps: collecting three-phase stator currents of a three-phase inverter drive system in real time, constructing current characteristic information, and obtaining three-phase stator currents after scaling processing; integrating the three-phase stator currents after scaling processing to obtain positive bias of phase current and negative bias of phase current; setting a judgment threshold, and converting the positive bias of phase current and the negative bias of phase current into current bias state parameters; calculating a fault identification variable according to the dynamic scaling current bias state parameters; matching the fault identification variable with a fault diagnosis judgment rule to locate a specific switch tube position where an open circuit fault occurs. The present application uses the idea of dynamic scaling, overcomes the interference of control factor uncertainty on the diagnosis criterion, completes online fault diagnosis, and provides a solid basis for fault-tolerant control and safety protection of the drive system.

An amplifier system for radio frequency hot switching of a power amplifier can include a field-effect transistor, a forward biasing network, and a reverse biasing network. The forward biasing network is configured to provide a positive bias voltage to a gate terminal of the field-effect transistor, and the reverse biasing network is configured to provide a negative bias voltage to the gate terminal, with resistance of both biasing networks selected to independently control an on and off-switching time of the field-effect transistor. The independent on and off-switching time can allow for rapid “hot switching” in a connected power amplifier while the power amplifier is energized, while reducing spurious emissions of radio frequency signals by the power amplifier.

The invention discloses a two-dimensional transistor and a preparation method thereof.The two bottom bias gates are arranged on the upper surface of an insulating substrate in a spaced mode, the upper surfaces of the bottom bias gates are completely covered with a dielectric layer, the upper surface of the dielectric layer is completely covered with a two-dimensional semiconductor material, and the two-dimensional semiconductor material is arranged on the upper surface of the insulating substrate. The drain electrode and the source electrode are arranged on the upper surface of the two-dimensional semiconductor material in a spaced mode. When the device works, the drain electrode, the source electrode and the bottom gate form a three-terminal field effect transistor; when positive and negative bias voltages are applied to the drain-source electrode, a reverse potential difference is formed between the bias gate and the channel, so that a differentiated doping effect is generated on the channel, and the transistor presents different polarities. In addition, by applying specific wavelength light intensity, photon-generated carrier modulation is carried out on the channel, and polarity switching can also be achieved. Through the designed reconfigurable transistor, various reconfigurable logic gate circuits can be realized.

The invention discloses a high-repetition-frequency and high-power silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving system, which relates to the technical field of silicon carbide driving and comprises a signal isolating and processing module, a PWM (Pulse-Width Modulation) signal receiving and isolating module, a PWM signal receiving and processing module and a The high-temperature optimization power supply module is connected to the driving core module and is used for providing a stable driving power supply with positive and negative voltages for the whole driving system; the grid regulation network is used for being connected to the grid of the silicon carbide MOSFET to form an interface of the driving system and the power device so as to regulate the switching speed and suppress oscillation; according to the high-repetition-frequency and high-power silicon carbide MOSFET driving system, the high-temperature optimization power supply module provides stable negative voltage turn-off; a safe negative bias is established for the gate voltage, and when the Miller capacitance coupling current arrives, the gate voltage needs to be raised from the negative voltage to zero and then continues to be raised to reach the opening threshold value, so that a key first defense line and a precious safety margin are provided for suppressing mistaken opening.

The invention provides a time-resolved anisotropic ball probe measuring device and method. The device comprises an insulating component, a protecting component and a collecting component, the insulating member has a first insulating portion and a second insulating portion. The protection component comprises a protection pole and a first conductor; the protection electrode is arranged on the second end face of the first insulation part, and the protection electrode is used for being connected with a power supply through the first electric conductor; the collecting component comprises a second electric conductor and a collecting electrode with a preset radian; the collectors are respectively arranged in the radian spaces; one end of the second conductor is connected with the collector, and the other end passes through the protection member and is connected with the power supply. The second electric conductor in the collecting component adopts a mode of a printed circuit board and a conducting rod structure, so that the utilization rate of the internal space of the collecting component is increased, and the spatial resolution is improved. In addition, the arrangement of the protection electrodes ensures the consistency and flatness of the plasma sheath layers of the collectors under the fixed negative bias voltage, and ensures that the measured current signals are accurate and available.

The invention provides a photoelectric detector with an I-type heterojunction and a preparation method and application thereof, and belongs to the technical field of photoelectric detectors. According to the photoelectric detector, two layers of light absorption layer materials with matched energy levels are selected to form an I-type heterostructure, and FN tunneling occurs under positive bias voltage, so that the photoelectric detector has forward light current; due to the fact that dark currents under positive and negative bias voltages have different magnitudes of magnitude, a detector has different dynamic ranges under the positive and negative bias voltages, an optical communication encryption scheme based on light intensity modulation is designed according to the difference, and when light currents of a device under the positive and negative bias voltages have equivalent levels, the device is decoded into positive codes or negative codes; when the photocurrent of the device under positive and negative bias voltages has a difference of several orders of magnitude, the device is decoded into a reverse code or a positive code, thereby realizing communication encryption.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion / mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

The invention, which relates to the technical field of the test power supply, provides a high-voltage linear discharge circuit comprising at least two voltage-sharing units, at least two discharge units and a sampling resistor. The second end of the first voltage-sharing unit is connected with the output discharge negative port, the first end of the first voltage-sharing unit is connected with the second end of the second voltage-sharing unit, and the first ends and the second ends of all the voltage-sharing units are sequentially connected in series; the first end of the first discharge unit is used for inputting a control signal, the control signal is used for adjusting discharge current, the second end of the first discharge unit is connected with the third end of the second discharge unit, and the second ends and the third ends of all the discharge units are sequentially connected in series until the second end of the nth discharge unit is connected with an output discharge port; the first end of the sampling resistor is connected with the third end of the first discharging unit, and the second end of the sampling resistor is used for being connected with a negative bias power supply and used for constructing a linear discharging circuit suitable for a high voltage grade.

The present application relates to the technical field of direct current power management and fault monitoring, and discloses a multi-dimensional abnormal early warning monitoring method and system in direct current power management, comprising: configuring a passive induction sheet in the center area of the top surface of the explosion-proof valve of the electrolytic capacitor in the direct current power supply; determining a signal acquisition pair between the passive induction sheet and the cathode of the electrolytic capacitor, and connecting a negative bias ADC channel and a polarity ADC channel in parallel on the signal acquisition pair; monitoring the negative direct current bias signal and the polarity inversion signal of the signal acquisition pair through the negative bias ADC channel and the polarity ADC channel respectively; analyzing the monotone increasing trend of the negative direct current bias signal and the relaxation time of the polarity inversion signal respectively; and realizing early failure warning of the electrolytic capacitor in the direct current power supply based on the monotone increasing trend and the relaxation time. The present application can realize long-term, online and non-interference early warning of the early failure phenomenon of the electrolytic capacitor in the direct current power supply under real working conditions.

The application relates to a high-performance double-gate junction field effect transistor and a preparation method thereof, which comprises a double P-N junction composed of two-dimensional Te and two-dimensional MoS2 in a preferred embodiment, and is composed of a three-layer structure, the upper and lower layers are two-dimensional MoS2 layers, and the middle layer is a two-dimensional Te layer; the layers are in a cross structure, and the electrodes shared by the MoS2 layers are used as the gate; the Te layer is used as a carrier channel layer, and the two electrodes are used as the source and the drain. The device structure realizes the opening and closing of the JFET by regulating the positive and negative bias of the P-N junction and the width of the depletion region of the Te channel layer. Since the structure does not have a dielectric layer, an ideal subthreshold swing is realized, and the carrier concentration of the two-dimensional Te is high, so that a large current response can be realized under a small source-drain voltage. The JFET designed in the application has a small subthreshold swing and a large on-state current, and is crucial for devices requiring low power consumption and large current design.

The application relates to the technical field of vacuum thin film preparation, and particularly discloses a position closed-loop control and suspension uniform pressure deposition system of a wire rod evaporation source; the position closed-loop control device is composed of a high-frequency induction heating coil, a laser displacement sensor, a precision lifting driving mechanism and a controller, the relative position between the top end of the wire rod and the coil is kept constant by driving the wire rod to axially move through an incremental PID algorithm, the impedance matching network is automatically tuned by using a gradient descent method, the deposition side is provided with an edge chamfered negative bias electrode, a uniform pressure plate which is suspended below a substrate and is connected with an adjustable bias power supply, and a double-layer insulation protection ring which is composed of a PTFE inner layer ring and an alumina ceramic outer layer ring. The application solves the problems of thermal decomposition carbonization, rate fluctuation and large-area electric field edge distortion during evaporation of easily thermally decomposed organic materials, and realizes high raw material utilization, high stability and large-area uniform deposition.

The invention discloses a display panel and a display device, the display panel comprises a first transistor and a second transistor, a second active layer comprises an oxide semiconductor, and the carrier mobility of the second active layer is greater than that of the first active layer. The second active layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer which are stacked. The first oxide semiconductor layer comprises indium, gallium and zinc, the second oxide semiconductor layer comprises indium, gallium, tin and zinc, the first indium ratio is smaller than the second indium ratio, and the first gallium ratio is larger than the second gallium ratio. The first indium ratio is set to be smaller than the second indium ratio and the first gallium ratio is set to be larger than the second gallium ratio in the second active layer, so that the requirement for high mobility of the second transistor is met, the electrical stability of the first oxide semiconductor layer is higher, surrounding hydrogen can be prevented from invading the second oxide semiconductor layer, and the mobility of the second transistor is improved. Therefore, the risk of negative bias of the threshold voltage of the second transistor is reduced.

The application provides an adaptive equalization circuit and method based on approximate calculation, and relates to the technical field of approximate circuit.The application constructs a three-level technical architecture: an approximate positive / negative compressor with directional error characteristics is designed, probability optimization logic is used to make the output generate positive and negative bias errors respectively; a Wallace tree array integrated compressor is used to form an 8bit*8bit layered approximate multiplier, low weight bits are truncated, intermediate bits are configured with approximate compressors, high weight bits are configured with full precision, and a mixed adder is used for summation; the approximate equalizer adopts a 15-tap FFE architecture, is based on an LMS algorithm, and divides the taps into front, main and rear taps according to signal energy, the main tap is configured with a low-error approximate negative multiplier, and the front and rear taps are cross-arranged to realize error complementation by using approximate positive / negative multipliers.The design simplifies hardware, realizes system-level error self-cancellation, reduces area, power consumption and delay, guarantees equalization performance, and provides a scheme for breaking through the bottleneck of a high-speed optical interface.