121 results about "Negative bias" patented technology

The invention relates to a high-voltage level shift circuit and a layout structure thereof, and the high-voltage level shift circuit comprises a pulse generation module which is used for receiving an input signal and generating a double-path low-voltage domain narrow pulse signal; the level shift module is used for receiving the low-voltage domain narrow pulse signal and converting the low-voltage domain narrow pulse signal into a corresponding double-path high-voltage domain narrow pulse signal; the voltage transient noise detection module is used for detecting voltage transient noise and generating a transient noise intensity signal; the voltage transient noise filtering module is used for filtering voltage transient noise based on the received transient noise intensity signal to generate a double-path high-voltage domain filtering signal; and the RS trigger is used for converting the received high-voltage domain filtering signal into a high-side power device driving signal. The common-mode noise filtering capability and the VS negative bias resisting capability of the voltage transient noise filtering module can be enhanced, the transmission delay of a chip is effectively reduced, and the width of a narrow pulse signal is free of loss in the transmission process, so that the dynamic power consumption is reduced.

The invention relates to the field of mass spectrum equipment, in particular to a low-noise and high-sensitivity mass spectrometer Faraday cup. The Faraday cup comprises a rectangular housing, one side of which is open; the suppression grid is arranged in the shell and is close to the opening; the collector is arranged in the shell and is adjacent to the suppression grid; a slit baffle is arranged at the opening of the shell; the collector is fixed through the insulating lining, insulated from the shell, and used for receiving the ion beam and generating current; the suppression grid electrode is fixed through an insulating lining and a metal positioning block, and negative bias voltage is applied to suppress escape of secondary electrons; the top cover is assembled on the shell to form a sealed whole; the collector connecting piece is arranged on the lower portion of the collector, one end of the Faraday cup outgoing line is welded to the collector connecting piece, and the other end of the Faraday cup outgoing line is led out of the shell. Noise is remarkably reduced, and the detection sensitivity of a mass spectrometer is improved.

Provided in the present invention are a nanotwinned silver material and a preparation method therefor. The preparation method comprises the following steps: step S1, cleaning a substrate, and drying same; and S2, selecting a silver target as a target material, placing the substrate and the target material into a magnetron sputtering device, vacuumizing same, and then applying a negative bias voltage to the substrate to perform direct-current magnetron sputtering deposition, wherein the bias voltage of the substrate ranges from -50 V to -200 V, the temperature of the substrate is 25-50ºC, the argon flow is 30-50 sccm, the vacuum degree of a sputtering chamber is 0.3-1.0 Pa, and the deposition time is 15-90 min. By means of the technical solution of the present invention, the prepared nanotwinned silver material contains high-density nano-twins, the proportion of twin boundaries is greater than 90%, and the hardness, electromigration resistance and thermal stability of the material are improved while the material has both high conductivity and high heat conductivity; and the obtained nanotwinned silver material has good comprehensive performance.

Aspects of the disclosure relate to a negative bias circuit for power device driving. An apparatus may include a power source, a gate impedance path, a capacitor in series with the gate impedance path, and a clamping circuit for a transistor gate.

The invention provides a display panel and electronic equipment, and relates to the technical field of display driving. According to the technical scheme, the potential maintaining module electrically connected with the first node is arranged in the pixel driving circuit, the potential maintaining module can maintain the potential of the first node, and the problem that negative bias coupling of a threshold compensation transistor is enhanced after heating is solved. The pixel driving circuit solves the problem that charge of the first node is transmitted to the second node through coupling of the threshold compensation transistor due to the fact that the first node is connected with the second node, further avoids the problem that the potential of the second node is pulled down, ensures the accuracy of driving current generated by the driving transistor, improves the reliability of the pixel driving circuit, and ensures that the display effect of the display panel is high.

The invention discloses a preparation method of a thin film transistor. The core of the preparation method is to construct a quasi-double-channel structure. Taking an insulating layer of the thin film transistor as a first metal oxide, and processing the surface of the insulating layer to obtain an oxygen-deficient surface; depositing a second metal oxide on the anoxic surface as a channel layer; a metal-oxygen bond of the insulating layer is higher than a metal-oxygen bond of the channel layer; and after the deposition of the second metal oxide is finished, a two-dimensional oxygen-deficient surface is spontaneously formed on the contact surface of the insulating layer and the channel layer through annealing treatment, so that the thin film transistor with the quasi-double-channel structure is obtained. Compared with a traditional thin film transistor, the thin film transistor has the advantages that the positive bias voltage stability and the negative bias voltage stability are obviously improved, and meanwhile, the mobility is greatly improved. The invention has the characteristics of high carrier mobility, small threshold voltage drift and high long-term working reliability, and is simple in preparation process and low in cost. The quasi-double-channel structure is expected to be widely applied to oxide thin film transistors.

Disclosed herein is an electronic device, including a plurality of row decoders. Each row decoder includes decoder logic generating an initial word line signal and word line driver circuitry generating an inverse word line signal at an intermediate node from the initial word line signal, and generating a word line signal at a word line node from the inverse word line signal. A word line underdrive p-channel transistor has a source coupled to the intermediate node, a drain coupled to a word line underdrive sink, and a gate controlled based upon the inverse word line signal. Negative bias generation circuitry generates the negative bias voltage at a gate of the word line underdrive p-channel transistor when the initial word line signal is at a logic high, and couples the gate of the word line underdrive p-channel transistor to ground when the initial word line signal is at a logic low.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion / mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

The invention relates to the technical field of semiconductor photoelectric detectors, in particular to a gallium oxide-based ultraviolet detector with a vertical structure and a preparation method of the gallium oxide-based ultraviolet detector. The detector comprises a bottom electrode, a substrate, a buffer layer, an epsilon-phase gallium oxide layer and a top electrode which are arranged from bottom to top, the buffer layer is nickel oxide; the substrate is a silicon substrate; the top electrode and the bottom electrode are used for applying bias voltage to realize polarization deflection of the epsilon-phase gallium oxide layer; the buffer layer is nickel oxide (111), and the thickness of the buffer layer is 1-50 nm. The method has the advantages that technical means such as doping, surface treatment or high-temperature annealing do not need to be introduced into the epsilon-phase gallium oxide thin film; positive and negative bias voltages are applied to the ferroelectric thin film material, and the electric dipoles are arranged along the direction of an electric field, so that the current regulation of a depolarization field on the device is realized, and the performance of the detector is effectively improved.

The invention relates to the technical field of direct-current power supply management and fault monitoring, and discloses a multi-dimensional abnormity early warning monitoring method and system in direct-current power supply management, and the method comprises the steps: configuring a passive induction sheet in a central region of the top end surface of an explosion-proof valve of an electrolytic capacitor in a direct-current power supply; determining a signal acquisition pair between the passive induction sheet and the cathode of the electrolytic capacitor, and connecting a negative bias ADC channel and a polarity ADC channel in parallel on the signal acquisition pair; respectively monitoring a negative DC bias voltage signal and a polarity inversion signal of the signal acquisition pair through a negative bias voltage ADC channel and a polarity ADC channel; respectively analyzing the monotone increasing trend of the negative direct current bias voltage signal and the relaxation time of the polarity reversal signal; and based on the monotone increasing trend and the relaxation time, early failure early warning of the electrolytic capacitor in the direct-current power supply is realized. According to the invention, long-term, on-line and interference-free early warning of the early failure phenomenon of the electrolytic capacitor of the direct-current power supply can be realized under real working conditions.

The embodiment of the invention provides an array substrate, a preparation method of the array substrate and a display panel, and relates to the technical field of display, the array substrate comprises a substrate and a driving wiring layer, the driving wiring layer is located on one side of the substrate, and the driving wiring layer comprises a transistor; the driving wiring layer comprises a first active layer located on one side of the substrate, a first conductive layer located on the side, away from the substrate, of the first active layer and a first barrier layer located on the side, away from the substrate, of the first conductive layer, the first barrier layer comprises a first barrier part, the transistor comprises a first grid electrode and a first active part, and the first grid electrode is located on the first conductive layer; the first active part is located on the first active layer, and the orthographic projection of the first blocking part on the substrate is at least partially overlapped with the orthographic projection of the first active part on the substrate. The risk that the transistor generates channel negative bias can be reduced, so that the convergence of the transistor can be improved.

An electronic device and a board vibration regulating circuit relate to the field of power electronics technology. The screen of the electronic device is a liquid crystal display screen, and the electronic device includes: a bias power supply integrated circuit, a load branch, and a power supply capacitor; the bias power supply integrated circuit is used to provide a negative bias voltage for the liquid crystal display panel of the screen, and the first output port of the bias power supply integrated circuit is used to output the negative bias voltage; the first end of the power supply capacitor is connected to the first output port of the bias power supply integrated circuit, and the second end of the power supply capacitor is grounded; the first end of the load branch is connected to the first output port of the bias power supply integrated circuit, and the second end of the load branch is grounded; the load branch is used to increase the load current output by the first output port of the bias power supply integrated circuit. By using this solution, the board vibration frequency of the power supply capacitor can be prevented from being within the frequency range that can be heard by the human ear, thereby preventing the user from hearing the board vibration sound, improving the user experience, and ensuring the call quality.

The application discloses a high-extraction-efficiency ion source structure and sealed neutron tube structure; a TiT thin film target is tightly attached to the inner wall of a closed shell; a target grid is tightly attached to the TiT thin film target, and a negative bias voltage is generated by loading a voltage between the target grid and the closed shell; plasma is generated after a voltage is loaded between a discharge anode and a discharge cathode; the scheme is based on the existing vacuum arc discharge ion source structure and is improved in structure; space is reserved between the discharge cathode and the anode grid for free expansion of the plasma, an open expansion space is provided for the plasma, most of the plasma generated by the discharge can expand into the acceleration zone to obtain energy and bombard the target surface, so that the arc current utilization rate can be increased to about 1%, and the neutron yield can be broken through 1*10 10 n / s.

The invention relates to a preparation method of a high-hardness ultra-smooth TiN coating, which comprises the following steps: putting a workpiece into a vacuum chamber, vacuumizing the vacuum chamber, and then introducing Ar to carry out ion cleaning on the surface of the workpiece; sequentially depositing a Cr layer and a Ti layer on the surface of the workpiece by adopting a radio frequency sputtering technology; a TiN layer is prepared on the surface of a workpiece by adopting a pure ion plating technology, when pure ion plating is carried out, mixed gas of Ar and N is introduced into a vacuum chamber, auxiliary ionization is carried out on the mixed gas in the vacuum chamber, negative bias voltage is applied to the workpiece, the ionization rate of a Ti target is improved by adopting a radio-frequency pulse power supply, and an ion beam is filtered by using a bent pipe magnetic filter. According to the TiN coating prepared through the method, the hardness can be stably higher than 3000 HV, the binding force on a high-speed steel base material is larger than 50 N, and the binding force with the base material is remarkably improved; the N content in the prepared TiN coating is larger than 45%, the ionization degree is very high, compactness is good, and the surface roughness Ra is smaller than 10 nm.

The present invention relates to the field of diode technology, and in particular to a low-end ideal diode based on a differential amplifier: the circuit is composed of an NMOS tube, a differential amplifier circuit, a voltage comparator, a negative bias power supply, etc.; the tube type in the differential amplifier circuit can be one of NPN, NMOS, PNP, and PMOS, and the differential amplifier circuit is used to compare the drain and source voltages of the NMOS tube, and the output signal is loaded into the voltage comparator again for amplification, and the voltage comparator outputs a signal to control the conduction and cutoff of the NMOS tube. The advantages are complemented by taking advantage of each other to achieve complementary advantages, and four low-end ideal diode circuits are designed. Software simulation verification shows that the designed circuit can realize the anti-backflow function, can meet the use occasions with a wide current range, and the circuit is simple, the cost is very low, and the practicability is strong.

The present invention provides a DA conversion device and the like that use the range of low voltage dependency of a MOS capacitor to make it possible to reduce nonlinearity of an output voltage. A charge scaling type DA conversion device comprising a high-order bit side capacitor array and a low-order bit side capacitor array that are connected via an attenuation capacitor comprises a control circuit that applies a voltage, to a plurality of capacitors of the high-order bit side capacitor array and a plurality of capacitors of the low-order bit side capacitor array, so that all of the capacitors have a positive bias voltage or a negative bias voltage at the times of reset and conversion of the DA conversion device, wherein at least one of a reference voltage of the low-order bit side capacitor array and a reset voltage is set to a value different from a reference voltage of the high-order bit side capacitor array.

The carrier concentration of the drift region (87) is controlled in the semiconductor substrate in response to a voltage applied to the gate electrode (81) of the gate-controlled diode (203). In the reverse recovery state, a voltage signal of zero bias or positive bias that causes an electron layer at the interface of the gate electrode (81) is applied between the gate electrode (81) and the anode electrode (86). In the forward recovery state, a voltage signal of negative bias that causes a hole layer at the interface of the gate electrode (81) is applied between the gate electrode (81) and the anode electrode (86). After the forward recovery state, the voltage signal of zero bias or positive bias is switched from the negative bias. The gate-controlled diode (203) variably controls the period during which the voltage signal of zero bias or positive bias is applied in accordance with the non-conduction period of the IGBT connected in series therewith.

Embodiments of the present disclosure are directed to an isolation housing for an electro-hydrodynamic (EHD) air mover device. The isolation housing includes the EHD air mover device, a shield placed on top of the EHD air mover device forming an upper wall of the isolation housing, a printed circuit board (PCB) assembly forming a bottom wall of the isolation housing, and a chassis made of one or more non-conductive materials and forming side walls of the isolation housing. The PCB assembly carries signal connections for a positive bias voltage signal, a negative bias voltage signal, and / or a ground signal. The chassis is shaped to hold the EHD air mover device in a defined position within the isolation housing. A first surface of the chassis is affixed to the shield, and a second surface of the chassis opposite to the first surface is affixed to the PCB assembly.

The present invention relates to a test device for underwater potential induced attenuation of a photovoltaic module, comprising a shell and a water mist generating chamber and a test chamber arranged in the shell; the water mist generating chamber and the test chamber are separated by a porous partition; a water injection assembly, a water mist generating unit, and a water heating unit are arranged in the water mist generating chamber; a heating metal plate is arranged on the single-side lifting assembly, and the photovoltaic module is arranged on the heating metal plate; a test stand, a power module, and an electric meter unit are also arranged in the test chamber; the heating metal plate and the high voltage output unit are respectively connected to the power module, and the high voltage output unit is connected to the main grid line of the photovoltaic module to form a negative bias voltage application structure. Compared with the prior art, the present invention can simulate the specific operating conditions of the photovoltaic module, and only needs to monitor the change curve of the parallel resistance over time to analyze the attenuation of the battery cell, avoiding the complicated testing process in the prior art, and can efficiently adjust the humidity scene to meet the testing requirements.

The invention relates to a composite coating, a preparation method thereof and a sanitary product. The preparation method of the composite coating comprises the following steps: forming the metal base layer on the surface of the base material; n B layers and n C layers are formed on the surface of the metal base layer, and a composite coating is prepared; wherein n is larger than or equal to 1, the n B layers and the n C layers are alternately arranged in the thickness direction of the composite coating, the B layer closest to the metal base layer is closer to the metal base layer than the C layer closest to the metal base layer, the materials of the B layers comprise Ti and SiO, the materials of the C layers comprise TiOx and SiOy, the C layers are formed in a sputter coating mode, and the thickness of the C layers is smaller than that of the C layers. The negative bias voltage is switched between a first negative bias voltage and a second negative bias voltage once every 180-480 s, the first negative bias voltage is smaller than or equal to 100 V, and the second negative bias voltage is larger than or equal to 800 V. According to the preparation method of the composite coating, the scratch resistance of the coating is improved, the service life is prolonged, and the composite coating has excellent waterlogging resistance.

An image sensor includes a photodiode that generates electric charges in response to light, a transfer transistor connected to the photodiode and a floating diffusion, a reset transistor connected between the floating diffusion and a power node, a boost capacitor connected to the floating diffusion and adjusting a capacity of the floating diffusion in response to a boost control signal, and a bias circuit having a first current circuit and a second current circuit for supplying different bias currents to an output node to which a voltage signal corresponding to electric charges accumulated in the floating diffusion is output. After the transfer transistor is turned off, the boost control signal is lowered from a high level to a low level, and the reset transistor is switched from an on state to an off state when the bias currents of the first current circuit and the second current circuit are simultaneously supplied to the output node.

The invention belongs to the technical field of plasma and wall material interaction (PMI) assistance, and particularly discloses a multi-sample rotation experiment supporting system in a linear plasma device, which comprises a temperature inspection instrument, a bias power supply, a rotation sample table, a supporting seat, a rotation transmission shaft and a temperature measurement and negative bias loading shaft, a rotary driving unit and an automatic advancing and retreating unit are mounted outside the vacuum chamber; a plurality of sample mounting stations are circumferentially distributed on the rotary sample table; the rotary transmission shaft is coaxially and fixedly connected with the rotary sample table; one end of the temperature measurement and negative bias loading shaft is connected with a temperature measurement piece and a negative bias metal end, the temperature measurement piece and the negative bias metal end can penetrate through the rotary sample table to be in contact with a sample on the sample mounting station, the temperature measurement piece is connected with a temperature itinerant detector through a cable, and the negative bias metal end is connected with a bias power supply through a cable. According to the invention, PMI experiments of a plurality of samples can be completed in a single experiment, and the experiment period is shortened.

A disclosed structure includes a power amplifier and circuitry for implementing a biasing scheme that enables high power operation. The power amplifier includes parallel transistor chains connected to input and output transformers. Each chain includes series-connected first, second, and third n-type field effect transistors (NFETs) having front and back gates. The output transformer receives a variable positive power supply voltage generated using average power tracking. Front and back gates of each third NFET receive a positive bias voltage greater than or equal to the variable positive power supply voltage and a negative bias voltage, respectively. By negative back biasing the third NFETs, threshold voltages thereof are raised so a high positive bias voltage can be applied to the front gates to increase power output without violating reliability specifications. Optionally, by making the negative bias voltage temperature dependent, voltages at source regions of the third NFETs are held constant.

The application provides a screening method, device, medium and equipment for an abnormal Flash chip. The method comprises the following steps: performing data abnormal voltage criticality test on a to-be-tested chip to determine a critical voltage value of the to-be-tested chip, wherein the to-be-tested chip is a to-be-tested Flash chip; determining whether the critical voltage value is greater than a voltage threshold value, wherein the voltage threshold value corresponds to a target gear of a negative bias voltage of the to-be-tested chip; and determining that the negative bias voltage of the to-be-tested chip is abnormal if the critical voltage value is greater than the voltage threshold value. In the case that the negative bias voltage cannot be directly measured, the safety of the negative bias voltage of the to-be-tested chip is evaluated from the side through the critical voltage value of the to-be-tested chip, so that the screening of the abnormal Flash chip is realized, and the accuracy of the screening result is ensured.

The utility model proposes a laser receiving circuit and a laser radar, the laser receiving circuit comprises an avalanche photodiode, a bias voltage generation circuit, an amplification circuit and a compensation circuit, the avalanche photodiode is driven by a negative bias voltage to carry out photoelectric conversion on a received laser pulse and generate an avalanche current, and the avalanche current is transmitted to the amplification circuit. When interference of ambient light or strong reflected light emitted by the laser emission circuit is received, the compensation circuit generates compensation current opposite to avalanche current based on voltage echo signals output by the amplification circuit, input signals of the amplification circuit are reduced, saturation of the amplification circuit is avoided, the dynamic range of the amplification circuit is enlarged, and the receiving sensitivity of the amplification circuit is improved. And the ranging accuracy and the environmental adaptability of the laser radar are improved.

The application discloses a gate drive circuit and a driving method thereof. The gate drive circuit comprises an output control module, a first output module, a second output module and a threshold adjusting module. The threshold adjusting module is used for turning on in response to a first adjusting signal in a threshold adjusting stage, so as to transmit a first potential signal to a control end of the second output module. The second output module comprises a transistor. The threshold adjusting module transmits the first potential signal to the control end of the second output module in the threshold adjusting stage, so as to partially offset the positive or negative bias of the threshold voltage of the second output module caused by a high-temperature environment, and ensure the normal output of the output signal of the gate drive circuit.

The application discloses a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a light-emitting module, a driving module, a coupling module, a second voltage transmission unit and a voltage interval unit. The second voltage transmission unit is connected between a first power supply and a first end of the driving module, and is used for transmitting a voltage of the first power supply to the first end of the driving module in a compensation stage. A first end of the coupling module is connected with a control end of the driving module. The voltage interval unit is connected between a second end of the driving module and a second end of the coupling module, and is used for being turned on in the compensation stage, so that the first power supply charges the coupling module, and a threshold voltage of the driving module is written to the second end of the coupling module. Through the charging compensation mode, the dispersion of the threshold voltage of the driving module is compensated, the compensation of the positive or negative bias of the threshold voltage is realized, the display uniformity is improved, and the display effect is improved.

Methods and assemblies for diffusion-based boriding as provided. The methods include accounting for faster immersion of a sample by applying an additional power to heat the electrolyte prior to immersion and applying a negative bias voltage to the sample to mitigation or eliminate oxidation. A fixture including a sample holder to apply the negative bias voltage is also provided.

A first embodiment relates to an amplifier circuit including a positive bias circuit having a driving PMOS biased in subthreshold mode, a negative bias circuit having a driving NMOS biased in subthreshold mode, and an amplification circuit coupled to the bias circuit. The amplification circuit includes a first stage having a first boost stage, a second stage having a second boost stage, and a resistive element coupled between the first and second stages. A second embodiment relates to a folded cascaded operational amplifier, wherein the value of the resistive element is selected to place at least one of the driving MOS in subthreshold mode. A third embodiment relates to an integrated circuit having a resistive region adjacent to a first boost region and a second boost region, the resistive region including a resistive element directly connected to the driving PMOS and the driving NMOS. Embodiments of this application also relate to a folded cascaded operational amplifier and a method of operating the amplifier circuit.

The invention discloses a streamer sterilization device and a control method thereof, electronic equipment and a storage medium. The streamer sterilization device comprises a power supply driving circuit and a dielectric barrier discharge generator for carrying out dielectric barrier discharge based on a driving power supply output by the power supply driving circuit, the power supply driving circuit comprises a square wave circuit used for outputting a square wave signal and a bias voltage circuit used for outputting a negative bias voltage signal. Wherein a square wave signal output by the square wave circuit and a negative bias voltage signal output by the bias voltage circuit are superposed and then power is supplied to the dielectric barrier discharge generator, so that the dielectric barrier discharge generator generates positive ions and / or negative ions. Thus, the dielectric barrier discharge generator can generate positive ions and / or negative ions as required based on the combination of the bias voltage circuit and the square wave circuit, then sterilization can be carried out based on the positive ions and / or air purification can be carried out based on the adsorption effect of the negative ions, the working performance of the streamer sterilization device can be improved, and the cost is low.