672 results about "Negative bias" patented technology

The coating of internal surfaces of a workpiece is achieved by connecting a bias voltage such that the workpiece functions as a cathode and by connecting an anode at each opening of the workpiece. A source gas is introduced at an entrance opening, while a vacuum source is connected at an exit opening. Pressure within the workpiece is monitored and the resulting pressure information is used for maintaining a condition that exhibits the hollow cathode effect. Optionally, a pre-cleaning may be provided by introducing a hydrocarbon mixture and applying a negative bias to the workpiece, so as to sputter contaminants from the workpiece using argon gas. Argon gas may also be introduced during the coating processing to re-sputter the coating, thereby improving uniformity along the length of the workpiece. The coating may be a diamond-like carbon material having properties which are determined by controlling ion bombardment energy.

Methods of operating non-volatile memory devices are described. The memory devices comprise memory cells having an n-type semiconductor substrate and p-type source and drain regions disposed below a surface of the substrate and separated by a channel region. A tunneling dielectric layer is disposed above the channel region. A charge storage layer is disposed above the tunneling dielectric layer. An upper insulating layer is disposed above the charge storage layer, and a gate is disposed above the upper insulating multi-layer structure. A positive bias is applied to a word lines of the memory device in a selected memory cell and a negative bias is applied to a bit line in the selected cell.

A method of operating a NAND flash memory device that comprising a unit string comprising a string selection transistor connected to a bit line, a cell transistor connected to the string selection transistor, and a ground selection transistor connected to the cell transistor is provided. The method comprises applying a negative bias voltage to the string selection transistor and the ground selection transistor in a stand-by mode of the NAND flash memory device.

The invention discloses a forming method of a metal gate, a forming method of an MOS (metal oxide semiconductor) transistor and a forming method of a CMOS (complementary metal oxide semiconductor) structure. The forming method of the metal gate comprises the following steps: after removing a pseudo polycrystalline silicon gate and forming a groove, forming high-K gate medium layers at the bottom and on the side wall of the groove, fluoridizing the high-K gate medium layers, and forming a function layer and a metal layer on the surfaces of the high-K gate medium layers. As fluorine bonds such as fluorine-silicon bonds and fluorine-hafnium bonds can be formed among the high-K gate medium layers and a semiconductor substrate after fluoridization and the bond energy of the fluorine bonds is higher than that of original hydrogen bonds, the instability of the negative bias temperature of a device is reduced; as fluorine is strong in oxidability, oxygen vacancies can be prevented from generating donor level in a band gap and becoming positively charged oxygen vacancies, the oxygen vacancies are passivated, and the instability of the positive bias temperature of the device is reduced.

A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring.