5results about How to "Threshold Voltage Stability" patented technology

The application relates to a gallium nitride epitaxial structure forming method and a semiconductor device. The method comprises the following steps: sequentially forming a buffer layer, an intrinsic GaN layer and an AlGaN layer on a substrate; growing a P-type doped GaN epitaxial layer on the AlGaN layer, controlling the doping concentration and thickness of the P-type GaN layer, performing N-type ion implantation on the P-type GaN layer, controlling the implantation depth in the range of 20nm-30nm, and then performing annealing. In another mode, the AlGaN layer is subjected to P-type ion implantation before the P-type GaN layer is grown to form an asymmetric P-type doped area, and then annealing is performed, and the implantation area is still P-type after annealing by controlling the implantation dose. In the semiconductor device, the contact layer is obtained by patterning the P-type GaN layer, and the P-type doped area with the highest doping concentration or the largest doping area is arranged at the position of the contact layer. The gate breakdown voltage can be improved, the threshold voltage can be stabilized, the low on-resistance can be maintained, and the CMOS process compatibility can be realized.

The invention relates to a silicon carbide gate oxide layer, a preparation method thereof and a semiconductor device. The preparation method of the silicon carbide gate oxide layer comprises the following steps: performing oxidation treatment on a silicon carbide epitaxial wafer in a nitrogen-containing atmosphere, and preparing a gate oxide film on the surface of the silicon carbide epitaxial wafer to form a first structure; performing bias temperature stress treatment on the first structure to prepare a second structure; performing wet etching on the second structure to prepare a third structure; and carrying out annealing treatment on the third structure. According to the preparation method of the silicon carbide gate oxide layer, a gate oxide film with low effective charge density and high breakdown field strength can be obtained. The semiconductor device prepared by using the silicon carbide gate oxide layer can have more stable threshold voltage.

The invention relates to an array substrate and a preparation method thereof, and a display panel. The array substrate comprises a first transistor and a substrate; the buffer layer is positioned on one side of the substrate; the first metal layer is located on the side, away from the substrate, of the buffer layer, the first metal layer comprises a first grid electrode of the first transistor, the first grid electrode comprises a first surface, a convex body extending in the direction away from the substrate is formed on the first surface, the convex body has a first orthographic projection on the substrate, and the first surface located outside the convex body has a second orthographic projection on the substrate; the active layer is located on the side, away from the substrate, of the first metal layer, the active layer comprises an active structure, the active structure comprises a channel region, at least part of the channel region and at least part of the first grid electrode are oppositely arranged, and the orthographic projection of the first part of the active structure on the substrate at least partially covers the first orthographic projection; and a second metal layer comprising a first pole of the first transistor, the first pole of the first transistor comprising a second surface facing the substrate, the second surface being in contact with the second portion.

This application discloses an active display control device based on gallium arsenide (GaAs) optoelectronic devices. In this device, the GaAs heterojunction field-effect transistor used in the array driving unit, leveraging the material's high electron mobility and the two-dimensional electron gas structure formed by the heterojunction, can instantaneously control the luminous state of the display pixels. Furthermore, it is electrically connected to each display pixel in a one-to-one correspondence, eliminating signal lag caused by multiplexing. Additionally, the GaAs CMOS logic unit, utilizing the properties of GaAs material, can significantly reduce the signal transmission delay of logic gate circuits. Combined with the high-frequency modulation characteristics of pulse width modulation signals, it effectively improves the smoothness of dynamic image transitions. Regarding high-frequency power consumption control, the GaAs heterojunction field-effect transistor can significantly reduce Joule heat loss and static power consumption during high-frequency switching. The cascaded structure of the array driving unit and the GaAs CMOS logic unit can reduce signal attenuation and distortion at high frequencies, reducing the power consumption of the auxiliary amplifier circuit.

The invention relates to an array substrate and a preparation method thereof, and a display panel. The array substrate comprises a substrate; the spacing layer is located on one side of the substrate, the spacing layer comprises a first surface deviating from the substrate, at least one groove sunken towards the substrate is formed in the first surface, and the groove has a first orthographic projection on the substrate; the first metal layer is located on the first surface and comprises a first grid electrode of a first transistor; the active layer is insulated from the first metal layer and located on the side, away from the substrate, of the first metal layer, the active layer comprises an active structure, the active structure comprises a channel region, at least part of the channel region and at least part of the first grid electrode are oppositely arranged, and the active structure comprises a first part and a second part; the orthographic projection of the first part on the substrate at least partially covers the first orthographic projection; the second metal layer is located on the side, away from the substrate, of the active layer, the second metal layer comprises a first electrode of the first transistor, the first electrode of the first transistor comprises a second surface facing the substrate, and the second surface makes contact with the second part.