11results about How to "Threshold Voltage Stability" patented technology

The application relates to a gallium nitride epitaxial structure forming method and a semiconductor device. The method comprises the following steps: sequentially forming a buffer layer, an intrinsic GaN layer and an AlGaN layer on a substrate; growing a P-type doped GaN epitaxial layer on the AlGaN layer, controlling the doping concentration and thickness of the P-type GaN layer, performing N-type ion implantation on the P-type GaN layer, controlling the implantation depth in the range of 20nm-30nm, and then performing annealing. In another mode, the AlGaN layer is subjected to P-type ion implantation before the P-type GaN layer is grown to form an asymmetric P-type doped area, and then annealing is performed, and the implantation area is still P-type after annealing by controlling the implantation dose. In the semiconductor device, the contact layer is obtained by patterning the P-type GaN layer, and the P-type doped area with the highest doping concentration or the largest doping area is arranged at the position of the contact layer. The gate breakdown voltage can be improved, the threshold voltage can be stabilized, the low on-resistance can be maintained, and the CMOS process compatibility can be realized.

The invention provides thin film deposition equipment and a manufacturing method of an NMOS (N-channel metal oxide semiconductor) device, and belongs to the field of semiconductors. The thin film deposition apparatus includes a housing having a sputtering chamber. The target material is arranged opposite to the substrate, the target material comprises a first sputtering material and a second sputtering material, and the atomic weight of the first sputtering material is different from that of the second sputtering material. And the radio frequency power supply is used for generating plasma to bombard the target material and sputter the target material to the surface of the substrate to form a thin film. And the external member is arranged in the sputtering chamber, the external member is provided with a sputtering layer with a certain thickness, and the sputtering layer is made of the same material as the target material. Through the sputtering layer with a certain thickness deposited on the suite, the threshold voltage of the device is relatively stable, the performance of the product is improved, the process window of the product is also enlarged, the utilization rate of a machine table is improved, and the loss of a target material is reduced.

The invention provides a high-temperature-resistant successive approximation type analog-to-digital converter which can be applied to the technical field of analog-to-digital conversion. The analog-to-digital converter comprises a capacitor DAC module used for sampling an analog signal; the comparator module is used for comparing the signals output by the capacitor DAC module and outputting a comparison result; the time sequence and control unit module is used for generating a clock signal and a time sequence control signal; the voltage reference module is used for providing reference voltage for the interior of the chip; the successive approximation register module is used for successive approximation of a true value of an analog input signal and converting the true value into a digital parallel signal to be output; the output buffer module is used for buffering the parallel signals and outputting serial data; and the temperature zone regulation and control module is used for keeping the temperature zone regulation and control module relatively stable at different temperatures by regulating bias voltage signals of the comparator module and the voltage reference module. A serial output mode is adopted for data output, and the efficiency and reliability of data transmission are optimized through the sequential control module.

The present application discloses a method for realizing a recessed gate enhanced HEMT device by wet etching, which comprises: providing an epitaxial wafer for manufacturing a recessed gate enhanced HEMT device; setting a patterned etching mask on the epitaxial wafer, and exposing a selected area of ​​the surface of the epitaxial wafer from the etching mask; contacting the selected area of ​​the surface of the epitaxial wafer with a persulfate solution, and irradiating the selected area of ​​the surface of the epitaxial wafer with ultraviolet light, thereby etching a recessed structure in the barrier layer of the epitaxial wafer, and the recessed structure is used to cooperate with the gate. The present application avoids the problem of damage introduced by the dry etching process by performing low-damage wet etching on the area under the gate of the HEMT device. The process is simple and efficient, the etching is uniform, the repeatability is good, and there is no need to add a process for removing the etching product. The recessed gate threshold voltage of the obtained device is stable and the gate reliability is strong.

The invention relates to a silicon carbide gate oxide layer, a preparation method thereof and a semiconductor device. The preparation method of the silicon carbide gate oxide layer comprises the following steps: performing oxidation treatment on a silicon carbide epitaxial wafer in a nitrogen-containing atmosphere, and preparing a gate oxide film on the surface of the silicon carbide epitaxial wafer to form a first structure; performing bias temperature stress treatment on the first structure to prepare a second structure; performing wet etching on the second structure to prepare a third structure; and carrying out annealing treatment on the third structure. According to the preparation method of the silicon carbide gate oxide layer, a gate oxide film with low effective charge density and high breakdown field strength can be obtained. The semiconductor device prepared by using the silicon carbide gate oxide layer can have more stable threshold voltage.

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate; the first insulating layer is formed on the substrate; a first semiconductor layer formed on the first insulating layer; the side surface of the first semiconductor layer obliquely intersects with the upper surface of the first insulating layer; a second semiconductor layer formed on a side surface of the first semiconductor layer, a third semiconductor layer formed on a side surface of the second semiconductor layer, a fourth semiconductor layer formed on the first to third semiconductor layers, two-dimensional charge carrier gas is formed at the interfaces of the fourth semiconductor layer and the first to third semiconductor layers. One of the following effects of simple device structure, simple process, low cost and excellent electrical performance can be realized.

The invention relates to an array substrate and a preparation method thereof, and a display panel. The array substrate comprises a first transistor and a substrate; the buffer layer is positioned on one side of the substrate; the first metal layer is located on the side, away from the substrate, of the buffer layer, the first metal layer comprises a first grid electrode of the first transistor, the first grid electrode comprises a first surface, a convex body extending in the direction away from the substrate is formed on the first surface, the convex body has a first orthographic projection on the substrate, and the first surface located outside the convex body has a second orthographic projection on the substrate; the active layer is located on the side, away from the substrate, of the first metal layer, the active layer comprises an active structure, the active structure comprises a channel region, at least part of the channel region and at least part of the first grid electrode are oppositely arranged, and the orthographic projection of the first part of the active structure on the substrate at least partially covers the first orthographic projection; and a second metal layer comprising a first pole of the first transistor, the first pole of the first transistor comprising a second surface facing the substrate, the second surface being in contact with the second portion.

A gate drive stage has a first power transistor comprising a first drain connection and a first source connection, a second power transistor comprising a second drain connection and a second source connection, the first source connection being conductively connected to the second drain connection, and the second source connection being conductively connected to the second source connection. The first drain electrode connecting end is conductively connected with the first voltage connecting end, the second source electrode connecting end is conductively connected with the second voltage connecting end, the first voltage connecting end has a first voltage value, the second voltage connecting end has a second voltage value, and the second voltage value is smaller than the first voltage value; a node is arranged between the first power transistor and the second power transistor, the node is electrically connected with a third gate connection of the normally closed power transistor, the third gate connection can be controlled through the node, the node is electrically connected with a third voltage connection, and the third voltage connection has a third voltage value. The third voltage value is between the first voltage value and the second voltage value.

This application discloses an active display control device based on gallium arsenide (GaAs) optoelectronic devices. In this device, the GaAs heterojunction field-effect transistor used in the array driving unit, leveraging the material's high electron mobility and the two-dimensional electron gas structure formed by the heterojunction, can instantaneously control the luminous state of the display pixels. Furthermore, it is electrically connected to each display pixel in a one-to-one correspondence, eliminating signal lag caused by multiplexing. Additionally, the GaAs CMOS logic unit, utilizing the properties of GaAs material, can significantly reduce the signal transmission delay of logic gate circuits. Combined with the high-frequency modulation characteristics of pulse width modulation signals, it effectively improves the smoothness of dynamic image transitions. Regarding high-frequency power consumption control, the GaAs heterojunction field-effect transistor can significantly reduce Joule heat loss and static power consumption during high-frequency switching. The cascaded structure of the array driving unit and the GaAs CMOS logic unit can reduce signal attenuation and distortion at high frequencies, reducing the power consumption of the auxiliary amplifier circuit.

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate; the first insulating layer is formed on the substrate; a first semiconductor layer formed on the first insulating layer; the side surface of the first semiconductor layer obliquely intersects with the upper surface of the first insulating layer; a second semiconductor layer formed on a side surface of the first semiconductor layer, a third semiconductor layer formed on a side surface of the second semiconductor layer, a fourth semiconductor layer formed on the first to third semiconductor layers, two-dimensional charge carrier gas is formed at the interfaces of the fourth semiconductor layer and the first to third semiconductor layers. One of the following effects of simple device structure, simple process, low cost and excellent electrical performance can be realized.

The invention relates to an array substrate and a preparation method thereof, and a display panel. The array substrate comprises a substrate; the spacing layer is located on one side of the substrate, the spacing layer comprises a first surface deviating from the substrate, at least one groove sunken towards the substrate is formed in the first surface, and the groove has a first orthographic projection on the substrate; the first metal layer is located on the first surface and comprises a first grid electrode of a first transistor; the active layer is insulated from the first metal layer and located on the side, away from the substrate, of the first metal layer, the active layer comprises an active structure, the active structure comprises a channel region, at least part of the channel region and at least part of the first grid electrode are oppositely arranged, and the active structure comprises a first part and a second part; the orthographic projection of the first part on the substrate at least partially covers the first orthographic projection; the second metal layer is located on the side, away from the substrate, of the active layer, the second metal layer comprises a first electrode of the first transistor, the first electrode of the first transistor comprises a second surface facing the substrate, and the second surface makes contact with the second part.