84results about How to "Threshold Voltage Stability" patented technology

An organic light emitting display device includes a display unit having pixels located at crossing regions of scan, control, data and sensing lines. Scan, control line, and data drivers respectively supply scan, control, and data signals to the scan, control, and data lines. A switching unit selectively couples the data lines to output lines of the data driver, a reference voltage source, or a negative bias voltage source. A sensing unit senses degradation information of an organic light emitting diode in the pixels and threshold voltage of a driving transistor in the pixels through the sensing lines. A control block stores the sensed degradation information and threshold voltage information. A timing controller is configured to generate a second data by converting an externally inputted first data using the degradation information and the threshold voltage information, and supply the second data to the data driver.

For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening. The opening is filled with a gate electrode. Such an extra-doped channel region prevents undesired body effect in the field effect transistor.

A memory device includes a stack of conductive strips in a plurality of first levels with a first opening and a conductive strip in the second level with a second opening, both openings exposing sidewalls. Data storage structures are formed on the sidewalls of the conductive strips in the plurality of first levels. A first vertical channel structure including vertical channel films is disposed in the first opening, the vertical channel films in contact with the data storage structures. The second opening is aligned with the first vertical channel structure. A gate dielectric layer is disposed on the sidewall of the conductive strip in the second level. A second vertical channel structure including vertical channel films is disposed in the second opening in contact with the gate dielectric layer on the sidewall of the conductive strip in the second level.

To stably control a threshold voltage of a functional circuit using an oxide semiconductor. A variable bias circuit, a monitoring oxide semiconductor transistor including a back gate, a current source, a differential amplifier, a reference voltage source, and a functional circuit which includes an oxide semiconductor transistor including a back gate are provided. The current source supplies current between a source and a drain of the monitoring oxide semiconductor transistor to generate a gate-source voltage in accordance with the current. The differential amplifier compares the voltage with a voltage of the reference voltage source, amplifies a difference, and outputs a resulting voltage to the variable bias circuit. The variable bias circuit is controlled by an output of the differential amplifier and supplies voltage to the back gate of the monitoring oxide semiconductor transistor and the back gate of the oxide semiconductor transistor included in the functional circuit.

The invention discloses a shield gate MOSFET device with a uniformly doped channel and a processing technology, which are characterized in that on the basis of the existing shield gate MOSFET device,a heavily doped first conductive type polycrystalline silicon column region is formed in a groove etching heavily doped polycrystalline silicon filling mode, and then a first conductive type body region is formed in a rapid thermal annealing mode; by optimizing the doping concentration of the first conductive type body region, a mutation junction is formed between the first conductive type body region and the drift region, so that the threshold consistency of the device is improved, meanwhile, the problem that the first conductive type body region is excessively compensated by the drift regionis solved, the doping concentration of the body region is improved, and the possibility that a parasitic triode of the device is turned on is reduced; reliability of the device is improved.

The invention discloses a gate drive circuit. The gate drive circuit comprises multiple gate drive units which are controlled by a first mode signal and a second mode signal. Each gate drive unit comprises an input module which is used for controlling the voltage of a first node according to a former gate transmission signal and a latter gate transmission signal; a control module which is used forgenerating a first control signal when the first mode signal is effective and generating a second control signal when the second mode signal is effective, wherein the first mode signal and the secondmode signal are alternately effective; a pull-down module which is used for pulling down the voltage of the first node when the first control signal or the second control signal is effective; a resetmodule which is used for resetting the second control signal to the low level when the first control signal is effective and resetting the first control signal to the low level when the second control signal is effective; and an output module which is used for generating the present gate drive signal according to the first control signal, the second control signal and the voltage of the first node.

The invention discloses a semiconductor structure and fin field-effect tube forming method and an etching device. The fin field-effect tube forming method comprises the step of providing a semiconductor substrate; the step of etching the semiconductor substrate to form a plurality of fin parts, wherein first grooves are formed between every two adjacent fin parts; the step of filling the first grooves with isolation materials to form an isolation structure; the step of spraying liquid, spraying a layer of liquid on the surface of the isolation structure and the surfaces of the fin parts, wherein the semiconductor substrate is rotated in the process of spraying; the step of supplying reaction gas, wherein the reaction gas is blended with the layer of liquid spraying the surface of the isolation structure and the surfaces of the fin parts to form an etching solution used for etching the isolation structure; the step of executing the liquid spraying process and the reaction gas supplying process repeatedly until the isolation structure is removed by certain thickness to form a second groove and to expose the fin parts by certain height; the step of forming a gate structure striding the surfaces and the side walls of the fin parts which are exposed by the certain height. The precision of removing the isolation structure by the certain thickness is improved.

The invention provides a groove type power device and a manufacturing method thereof. The method comprises the following steps: providing a substrate sequentially comprising a first conductive type heavily doped layer and a first conductive type lightly doped epitaxial layer from bottom to top; forming a cellular region groove and a terminal region groove in the lightly doped epitaxial layer; forming a gate dielectric layer on the side wall and the bottom surface of the groove and the top surface of the lightly doped epitaxial layer; forming a polycrystalline silicon layer so as to fill the cellular region groove and the terminal region groove, and carrying out second conduction type doping on the polycrystalline silicon layer; etching the polycrystalline silicon layer until the polycrystalline silicon layer is flush with the top surface of the lightly doped epitaxial layer to obtain a cellular region groove gate and terminal region groove polycrystalline silicon; performing first conduction type doping on the cellular region groove gate and the terminal region groove polycrystalline silicon; forming a body region in the lightly doped epitaxial layer; and forming a source region in the body region. According to the invention, the groove type terminal is adopted, and body region injection can be carried out by adopting relatively high energy, so that the device has more stable threshold voltage and breakdown voltage.

A semiconductor device having an improved connecting reliability of an interconnect is presented via a simple and easy process, and further, a semiconductor device having a stable threshold voltage of a transistor that provide a stable electrical characteristic is also presented. A method for manufacturing a semiconductor device according to the present invention comprises: forming a trench in a silicon substrate; forming a first insulating film on a surface of said silicon substrate, said surface including an interior wall of said trench; forming a polysilicon film which plugged in said trench and covered on an entire surface of said silicon substrate; forming a second insulating film with oxidizing a portion of said polysilicon film disposed outside of said trench, and oxidizing a surface region of said silicon substrate located right under said first insulating film disposed outside of said trench and a surface region of said polysilicon film in said trench; and forming an embedded polysilicon layer with removing said second insulating film so that the surface of said silicon substrate is partially exposed and said polysilicon film is partially remained in said trench.

The invention provides a method for stabilizing flash memory unit word line threshold voltage. The method includes the steps that photoresist is distributed on a silicon wafer, the photoresist on an active area of the silicon wafer is removed, and the photoresist on the peripheral portion of the silicon wafer is left; first injection treatment is executed on a flash memory unit forming area of the active area of the silicon wafer, and an injection condition of the first injection treatment is selected so that an expected floating gate lower threshold can be formed on a final flash memory unit; the flash memory unit forming process is executed on the silicon wafer so that the flash memory unit can be formed on the flash memory unit forming area of the active area; second injection treatment is executed on the active area of the silicon wafer so that doping can be formed on the positions, corresponding to the silicon wafer area, of word lines on the two sides of the flash memory unit, and an injection condition of the second injection treatment is selected so that an expected word line lower threshold can be formed on the final flash memory unit, wherein ion injection is not carried out on the flash memory unit forming area in the flash memory unit forming process.

A grid electrode forming method includes: providing a substrate; forming a polycrystalline silicon layer on the substrate; subjecting the polycrystalline silicon layer to primary etching in a grid width direction, subjecting the polycrystalline silicon layer to secondary etching in a grid length direction, and forming a grid electrode after primary etching and second etching are finished. The secondary etching includes: forming a photoresist with a window on the polycrystalline silicon layer, wherein the window exposes an area between two adjacent grid electrodes in the grid width direction, and residues are attached in the window; removing the residues; forming a side wall on the side wall of the window after the residues are removed; after the side wall is formed, etching the polycrystalline silicon layer to the upper surface of the substrate through the window. The grid electrode forming method has the advantages that roughness of the window is reduced by removing the residues; the problem of size increase caused by excessive etching of the photoresist in removing of the residues is solved by forming the side wall on the side wall of the window after the residues are removed.

The invention provides a preparation method of a p-GaN gate enhanced HEMTs device with a stable threshold voltage. Improvement is carried out on the basis of a p-type gate enhanced HEMTs manufacturing method, the SiN passivation layer is arranged on the p-GaN cap layer in an epitaxial mode to introduce hydrogen elements to passivate a defect state in p-GaN, the p-GaN gate enhanced HEMTs with the high threshold voltage stability are obtained, and the threshold voltage of the p-GaN gate enhanced GaN HEMTs does not drift when the p-GaN gate enhanced GaN HEMTs works at high voltage and high frequency.

The disclosure provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate, a first insulating layer formed on the substrate, a first semiconductor layer formed on the first insulating layer, a second semiconductor layer formed on the side surface of the first semiconductor layer, a third semiconductor layer formed on the side surface of the second semiconductor layer, and a fourth semiconductor layer formed on the first, second and third semiconductor layers. The side surface of the first semiconductor layer is obliquely intersected with the upper surface of the first insulating layer. Two-dimensional charge carrier gas is formed at interfaces between the fourth semiconductor layer and the first to third semiconductor layers. Therefore, the semiconductor device has the following beneficial effects: the device structure is simple; the process is simple; cost is low; and the electrical performance is excellent.