Transistor and forming method thereof

Abstract

Provided are a transistor and a forming method thereof. The transistor comprises a semiconductor substrate, a groove located in the semiconductor substrate, a gate dielectric layer located on the lateral wall and the bottom surface of the groove, a gate electrode layer located on the surface of the gate dielectric layer, a source region and a drain region. The groove is formed by a first sub groove and a second sub groove located below the first sub groove, wherein the second sub groove is communicated with the first sub groove, an opening of the first sub groove is larger than that of the second sub groove, the lateral wall of the first sub groove is inclined relative to the surface of the semiconductor substrate, and the lateral wall of the second sub groove is perpendicular to the surface of the semiconductor substrate. The gate electrode layer fully fills the groove and the surface of the gate electrode layer is level to that of the semiconductor substrate. The source region is located in the semiconductor substrate on two sides of the groove. The drain region is located in the semiconductor substrate on one side opposite to the groove and is opposite to the second sub groove. The transistor is stable in threshold voltage and good in performance.

Description

technical field

[0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a transistor and a forming method thereof. Background technique

[0002] At present, transistors are widely used as a basic semiconductor device. Among various transistors, Trench Metal-Oxide-Silicon Transistors (Trench Metal-Oxide-Silicon Transistors), as a power device, are widely used in VLSI.

[0003] Schematic diagram of the cross-sectional structure of the formation process of the existing trench metal-oxide-semiconductor field effect transistor, such as Figure 1 to Figure 4 shown, including:

[0004] Please refer to figure 1 , provide a semiconductor substrate 100 , the semiconductor substrate 100 has a trench 101 inside, and the sidewall of the trench 101 is perpendicular to the surface of the semiconductor substrate 100 .

[0005] Please refer to figure 2 , in the trench 101 (as figure 1 ) to form a gate dielectric layer 102 on the sidewall a...

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