19results about How to "Reduce doping concentration" patented technology

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer sequentially comprises a substrate, a buffer layer, an intrinsic semiconductor layer, an N-type semiconductor layer, a multi-quantum well layer, an electron blocking layer and a P-type semiconductor layer. The P-type semiconductor layer comprises a Si3N4 layer, a first superlattice layer and a second superlattice layer which are sequentially stacked on the electron blocking layer, the first superlattice layer comprises a Mg-doped Al < x > Ga < 1-x > N layer and a Mg-doped GaN layer which are alternately stacked, and the second superlattice layer comprises a non-doped GaN layer and a Mg-doped In < y > Ga < 1-y > N layer which are alternately stacked. By implementing the invention, the luminous efficiency of the light-emitting diode can be improved.

The invention provides a diffusion method and a solar cell. In the diffusion method provided by the invention, a silicon wafer is firstly placed in a diffusion furnace, and pre-oxidation treatment is carried out on the silicon wafer for 200-240 seconds under the conditions that the temperature is 820-840 DEG C, the oxygen flow is 200-500 sccm and the nitrogen flow is 2000-3000 sccm; then, under the conditions that the temperature is 750-860 DEG C and the ratio of the flow of the boron source to the flow of the oxygen is 1: 3-1: 4, carrying out pre-deposition treatment on the silicon wafer for 100-160 seconds; carrying out secondary deposition treatment on the silicon wafer for 100-160 seconds under the conditions that the temperature is 840-900 DEG C and the ratio of the flow of the boron source to the flow of the oxygen is (1: 3)-(1: 4); and finally, performing junction pushing on the silicon wafer under the temperature condition of 850-950 DEG C to prepare a boron diffusion layer. Under the comprehensive action of the pre-oxidation treatment, the pre-deposition, the secondary deposition and the junction pushing treatment, the boron source doping concentration can be reduced, diffusion is uniform, diffusion sheet resistance is increased, and meanwhile PN junction distribution becomes shallow.

The invention discloses a light-emitting device and a preparation method thereof and a display device, a light-emitting layer comprises a host material, a sensitizer and a fluorescent object material, the ratio of the doping concentration of the sensitizer to the doping concentration of the fluorescent object material is high, and the light-emitting device aims at solving the problems that an existing light-emitting device is low in efficiency and short in service life. The invention further discloses a preparation method of the light-emitting device, the light-emitting layer is formed on the surface of the first electrode through linear source vacuum evaporation, the host material, the sensitizer and the fluorescent object material are placed in the corresponding evaporation sources respectively, the evaporation sources of the fluorescent object material are scanned preferentially, the evaporation rates of the three evaporation sources are adjusted, and the light-emitting device is obtained. The doping concentration of the sensitizer and the fluorescent guest material is gradually increased or decreased along with the increase of the thickness of the light-emitting layer; and evaporating a second electrode on the surface of the light-emitting layer.

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is internally provided with a drift region; forming a gate structure, wherein the gate structure covers a part of the drift region; a first body region is formed in the substrate, a first spacer region is arranged between the first body region and the drift region, and the doping type of the first spacer region is different from that of the drift region; a first inversion region is formed in the drift region, at least one part of the first inversion region is covered by the gate structure, and the doping type of the first inversion region is different from that of the drift region; the semiconductor structure is annealed, so that the first body region is diffused to the first interval region to obtain a second body region, the second body region is adjacent to the drift region, and the doping concentration of the second body region below the gate structure is gradually reduced in the direction adjacent to the drift region; a second inversion region is obtained based on the first inversion region, at least a part of the second inversion region is covered by the gate structure, and the doping type of the second inversion region is consistent with that of the first inversion region. By adopting the technical scheme, the breakdown voltage of the semiconductor structure can be improved.

A first contact hole at the top of a source region is directly composed of a material layer of a front metal layer filled in an opening of the first contact hole, the front metal layer is made of AlSiCu, and the content of Si in the AlSiCu reaches a saturation value; the AiSiCu of the first contact hole directly forms ohmic contact with the source region and the semiconductor material of the first epitaxial layer of the second conductive type well, and by utilizing the characteristic that the content of Si in the AlSiCu reaches a saturation value, the sharp convex defect is prevented from being formed when the A1Cu directly contacts with the semiconductor material of the first epitaxial layer; by utilizing the characteristic that the resistivity of AlSiCu is greater than that of AlCu, the forward conduction voltage drop of the body diode is increased, and the reverse recovery characteristic of the device is improved. The reverse recovery charge can be reduced, and the reverse recovery characteristic of the device can be improved.

The embodiment of the invention relates to the field of solar cells, and provides a solar cell and a photovoltaic module, and the solar cell comprises a substrate, and the surface of the substrate is provided with metal regions and non-metal regions which are alternately arranged; the semiconductor doping layer is located on the surface, corresponding to the metal region, of the substrate, and P-type doping elements are arranged in the semiconductor doping layer; the first tunneling dielectric layer is positioned on the surface of the substrate corresponding to the non-metal region; the first polycrystalline silicon layer is located on the surface of the first tunneling dielectric layer, and aluminum elements are doped in at least part of the first polycrystalline silicon layer; the first passivation layer is located on the surface of the semiconductor doping layer and the surface of the first polycrystalline silicon layer; and the first electrode is located on the surface of the first passivation layer corresponding to the metal region, and the first electrode is electrically connected with the semiconductor doping layer. The solar cell and the photovoltaic module provided by the embodiment of the invention at least can improve the photoelectric conversion efficiency of the cell.

The invention discloses a planar gate power device. A device unit comprises a drift region, a planar gate, a channel region, a source region and an anti-JFET region. The anti-JFET region is at least divided into an anti-JFET top layer region and an anti-JFET bottom layer region, and the anti-JFET top layer region is located between the channel regions on the two sides of the plane gate. The doping concentration of the anti-JFET top layer region is smaller than that of the anti-JFET bottom layer region, and the lower doping concentration of the anti-JFET top layer region is used for reducing stepping of the device. The higher doping concentration of the bottom region is used to reduce the specific on-resistance of the device. The first doping layer penetrates through the source region and the channel region, and the top region of the first doping layer is used for being in contact with the channel region and serving as a channel leading-out region for leading out the channel region; and the bottom region of the first doping layer is used for exhausting the bottom region of the anti-JFET, so that the breakdown voltage of the device is improved. The invention further discloses a manufacturing method of the planar gate power device. The on-resistance of the device can be reduced and the breakdown voltage of the device can be increased while the stepping of the device is reduced.

The embodiment of the present application provides a diode device, which comprises: a first semiconductor layer of a first doping type; a field termination layer of the first doping type formed on the first semiconductor layer; a field transition layer of the first doping type formed on the field termination layer; a drift region of the first doping type formed on the field transition layer, and a plurality of column regions of a second doping type formed in the drift region and arranged at intervals; a second semiconductor layer of the second doping type formed above the drift region; the doping concentration of the field transition layer is less than the doping concentration of the field termination layer, the drift region and the field transition layer can respectively cause a conductive modulation effect to accumulate minority carriers; when the diode device is turned off, the field transition layer is completely depleted, the electric field is reduced in the field transition layer and reduced to 0 in the field termination layer. The embodiment of the present application solves the technical problem that the traditional SJ-diode device has large turn-off energy loss caused by tail current in the turn-off process.

The invention discloses a fast recovery diode and a preparation method thereof, and relates to the technical field of semiconductors, and the fast recovery diode comprises a semiconductor body which comprises a terminal region and an active region; wherein the terminal region is doped with a first composite center impurity, and the first composite center impurity is used for compositing minority carriers in the terminal region so as to adjust the service life of the minority carriers in the terminal region; the doping concentration of the first composite center impurities is gradually reduced in the direction from the terminal region to the active region; the first groove is located in the first surface of the semiconductor body and located in the area, away from the active area, of the terminal area; the semiconductor body further comprises a first surface and a second surface which are oppositely arranged. The first groove is used as a diffusion center of the first composite center impurity, and the first composite center impurity diffuses from the first groove to the terminal area. According to the technical scheme provided by the invention, the performance and reliability of the fast recovery diode are improved.

The invention relates to the technical field of semiconductors, and particularly discloses a light-emitting diode epitaxial wafer and a preparation method thereof.The epitaxial wafer comprises a substrate and an epitaxial layer, the epitaxial layer comprises an active layer, an electron blocking layer and a P-type layer, and a hole injection layer is arranged between the active layer and the electron blocking layer; the hole injection layer comprises a first superlattice layer, a magnesium-carbon co-doped GaN composite layer and a second superlattice layer which are sequentially deposited in the epitaxial direction, the first superlattice layer is of a periodic structure formed by alternately stacking unintentionally-doped Mg AlGaN layers and low-doped Mg AlGaN layers, and the second superlattice layer is of a periodic structure formed by alternately stacking unintentionally-doped Mg GaN layers and high-doped Mg InGaN layers. The Mg doping concentration of the InGaN layer with high Mg doping is greater than the Mg doping concentration of the magnesium-carbon co-doped GaN composite layer, and the Mg doping concentration of the magnesium-carbon co-doped GaN composite layer is greater than the Mg doping concentration of the AlGaN layer with low Mg doping. Through mutual cooperation of multiple material layers, the self-compensation effect of Mg is effectively reduced, the concentration of activated Mg is improved, the hole concentration is improved, the effective hole injection efficiency is improved, and electron overflow is reduced, so that the radiation recombination efficiency of electrons and holes in the active layer is improved, and the luminous efficiency of the light-emitting diode is improved.

The present invention discloses a floating gate split-gate flash memory device, wherein the first gate structure comprises a floating gate dielectric layer, a floating gate polysilicon layer, an inter-polysilicon dielectric layer and a control gate polysilicon layer. The outer side surface of the first inner side wall defines the outer side surface of the first gate structure, the inner side surface of the first inner side wall defines the inner side surfaces of the inter-polysilicon dielectric layer and the control gate polysilicon layer, and the inner side surfaces of the floating gate dielectric layer and the floating gate polysilicon layer are self-aligned and defined by the second inner side wall of the inner side surface of the first inner side wall. The second gate structure is self-aligned and formed on the inner side surface of the first gate structure. The lightly doped drain region and the outer pocket injection region are both self-aligned with the outer side surface of the first gate structure. The inner pocket injection region is self-aligned with the inner side surface of the control gate polysilicon layer. The source-drain injection region is self-aligned with the outer side wall of the outer side surface of the first gate structure. The present invention also discloses a method for manufacturing a floating gate split-gate flash memory device. The present invention can reduce the short channel effect of the device and simultaneously improve the withstand voltage of the source-drain junction.

The invention discloses a trench Schottky barrier diode and a manufacturing method, a trench of the diode located in an epitaxial layer is in a step shape formed by a small upper cylindrical opening and a large lower cylindrical opening, conductive polycrystalline silicon is arranged in the trench, a dielectric layer isolates the conductive polycrystalline silicon from the epitaxial layer on the inner wall of the trench, and the dielectric layer is connected with the trench. The thickness of the dielectric layer on the inner wall of the upper cylindrical opening is smaller than that of the dielectric layer on the inner wall of the lower cylindrical opening. According to the trench and the upper cylindrical small opening, the conductive area during forward conduction is increased, and forward conduction voltage drop is reduced; the lower cylindrical opening is large, so that the point discharge effect during reverse bias of the device is avoided; furthermore, the dielectric layer covered on the inner wall of the lower cylindrical opening of the groove is thicker, and the pressure drop borne by the dielectric layer is increased during reverse bias; and the thin dielectric layer on the side wall of the upper cylindrical opening is beneficial to forming depletion pinch-off in the mesa structure epitaxial layer during reverse bias, so that the reverse blocking performance of the device is further improved, the reliability of the device is improved, and the service life of the device is prolonged.

The invention discloses a step-shaped groove Schottky barrier diode and a manufacturing method, the diode comprises a cathode metal layer, a substrate, an epitaxial layer, a functional metal layer and an anode metal layer from bottom to top, a step-shaped groove is distributed in the epitaxial layer, the groove is composed of an upper cylindrical opening and a lower cylindrical opening, the upper cylindrical opening is small, the lower cylindrical opening is large, and the functional metal layer is a metal layer. Conductive polycrystalline silicon is arranged in the groove, the dielectric layer isolates the conductive polycrystalline silicon from the epitaxial layer, the Schottky barrier region and the anode electrode region, and the epitaxial layer at the bottom of the groove further comprises an ion implantation region. According to the trench and the upper cylindrical small opening, the conductive area during forward conduction is increased, the forward conduction current density is reduced, the forward conduction voltage drop is reduced, and the forward conduction performance is improved; the lower cylindrical opening is large, so that the point discharge effect during reverse bias of the device is avoided, the reverse blocking performance of the device is improved, and the reliability and the service life of the device are improved.

The invention provides a manufacturing method of a high-voltage planar silicon controlled rectifier, which is characterized in that extended junctions surround the peripheral edge of a front P-type base region, the diameters of the extended junctions are different, and the extended junctions are gradually reduced along the direction far away from the front P-type base region, so that the doping concentration can be continuously and linearly decreased towards the edge direction along the front P-type base region; meanwhile, the doping concentration is gradually reduced, so that the junction depth is gradually reduced, the main junction electric field can be effectively improved, the size of the terminal is further reduced, and the chip area is reduced; and the composite passive film is formed on the front surface of the silicon wafer, so that an external electric field can be shielded, surface breakdown is avoided, reverse voltage resistance is improved, the silicon controlled rectifier is not easy to crack, and the performance of a silicon controlled rectifier product is more excellent.

The invention provides a super junction semiconductor device and a manufacturing method thereof. The super junction semiconductor device comprises a first conductive type substrate and a first conductive type epitaxial layer; a first groove is formed in the first conductive type epitaxial layer; a second conductive type epitaxial layer is arranged on the inner wall of the first groove; a first dielectric layer is arranged in the first groove; a part of the second conductive type epitaxial layer on the same side of the top of each first groove is removed to form a second groove; forming a gate trench at the upper part in the second trench; a section of first dielectric layer is reserved below the gate trench; a gate oxide layer is arranged on the side wall of the gate trench; grid polycrystalline silicon is arranged in the grid groove; second conductive type well regions are arranged at the tops of the first conductive type epitaxial layers on the two sides of the first groove; a heavily doped first conductive type injection region is formed at the top in the second conductive type well region, close to the same side of the gate trench, of each first trench; the device provided by the invention can bear higher withstand voltage, and the working frequency is improved.

The invention relates to a staggered floating island device and a rapid opening structure and a self-alignment manufacturing method thereof in the technical field of semiconductors, the staggered floating island device comprises a surface layer, a bottom layer and a drift region, the drift region comprises a plurality of groups of epitaxial layers and a plurality of groups of floating island layers, the floating island layers are arranged in a staggered manner, and a floating island in each floating island layer is composed of two doped regions, the floating islands of the at least two groups of floating island layers are partially overlapped or not overlapped in the overlook direction, one group of floating island layer is arranged between every two groups of epitaxial layers, or one group of epitaxial layer is arranged between every two groups of floating island layers, and a heavily doped inversion region is arranged in the floating island layer of the quick opening structure. The floating island adopts the two doped regions, so that the doping concentration of the annealed floating island is close to ideal uniform distribution, the junction capacitance of the floating island is increased, and the turn-on voltage is reduced. The staggered floating islands have the advantage of reducing obstruction of space charges to current after multiple times of opening, and the problem that the conduction capability of the floating island device is reduced after multiple times of opening is relieved.

The invention provides a light emitting diode chip and a preparation method thereof, and belongs to the technical field of semiconductors. The light-emitting diode chip comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are stacked in sequence; the P-type semiconductor layer comprises a non-doped sub-layer and a doped sub-layer which are stacked together, the doped sub-layer comprises a first high-temperature phase layer, a second high-temperature phase layer and a third high-temperature phase layer which are stacked in sequence, and precursor materials of the non-doped sub-layer and the doped sub-layer are TEGa. According to the invention, the crystallization quality can be ensured, and the high doping concentration can also be ensured.

The application discloses a preparation method of a buried heterojunction for a distributed feedback laser, which can reduce the threshold current of a laser, greatly improve the consistency of a device and has strong process compatibility. The method introduces a selective Zn diffusion treatment process step after growing a buried layer on a top cladding layer. A high-concentration p-type region formed through the diffusion step can form a more ideal ohmic contact with a metal electrode. In addition, an extra thin gold layer with a thickness of 5-10 nm is evaporated on the top cladding layer, which can significantly reduce the ohmic contact. The ohmic contact is reduced from 1.2e ‑5 to 4.5e ‑7 , about 26.6 times. In addition, while reducing the ohmic contact, the current limiting effect is significantly enhanced. The threshold current of the laser prepared by the method can be reduced to 15-18 mA. In addition, the method has low process difficulty, high operability, high freedom and greatly improved device consistency. Moreover, the method has strong process compatibility. The method is suitable for popularization and application in the field of semiconductor lasers.

This application relates to the photovoltaic field, providing a solar cell and a photovoltaic module. The solar cell includes: a substrate, the surface of which has a first region and a second region arranged at intervals, at least one of the first regions comprising a first part and a second part; a doped layer located within the substrate adjacent to the surface of the first part, the doping concentration of the doped layer being greater than the doping concentration of the substrate; a conductive layer located on the surface of the first region; a passivation layer located on the surfaces of the conductive layer and the second region; and a plurality of electrodes arranged at intervals along a first direction, the electrodes extending along a second direction, each electrode facing the second part, the electrodes being disposed on the side of the conductive layer away from the substrate and electrically connected to the conductive layer. The solar cell and photovoltaic module provided by this application can at least improve the photoelectric conversion efficiency.