426results about How to "Reduce doping concentration" patented technology

A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.

The invention relates to a nonpolar A side nitride film that comprises a silicon (102) underlay, metal layer which grows upon the silicon underlay sequentially, InGaAlN initial growth layer and the first InGaAlN buffer layer, it characterized in that: said silicon underlay is Si underlay which adopts the (102) side or offset angle. The nonpolar a side nitride film which grows on the silicon underlay can be used in LBD, laser, solar battery. The component extension configuration is adopted according to different component, for example the LBD and laser, and using the mature silicon craft further to produce relative diprosopia electrode component or peeling off component. The advantages of the invention are: the invention can increase the growth quality of nonpolar GaN base material, and decrease the cost; the craft of current component can be simplified greatly, the cost can be decreased, and increase the elimination efficiency and lightening efficiency greatly.

Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein.

This invention discloses a trench MOSFET comprising a top side drain region in a wide trench in a termination area besides a BV sustaining area, wherein said top side drain comprises a top drain metal connected to an epitaxial layer and a substrate through a plurality of trenched drain contacts, wherein the wide trench is formed simultaneously when a plurality of gate trenches are formed in an active area, and the trenched drain contacts are formed simultaneously when a trenched source-body contact is formed in the active area.

A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a thick contact interlayer, and further diffused to optimize a trade-off between Rds and the avalanche capability. Thus, only three masks are needed in fabrication process, which are trench mask, contact mask and metal mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Gaussian-distribution from trenched source-body contact to channel region.

A trench Schottky barrier rectifier includes an cathode electrode at a face of a semiconductor substrate and an multiple epitaxial structure in drift region which in combination provide high blocking voltage capability with low reverse-biased leakage current and low forward voltage. The multiple structure of the drift region contains a concentration of first conductivity dopants therein which comprises two or three different uniform value from a Schottky rectifying junction formed between the anode electrode and the drift region. The thickness of the insulating region (e.g., SiO2) in the MOS-filled trenches is greater than 1000 Å to simultaneously inhibit field crowing and increase the breakdown voltage of the device. The multiple epi structure is preferably formed by epitaxial growth from the cathode region and doped in-situ.

The invention discloses a nitride LED (light-emitting diode) structure. A P-type doped InGaN/GaN superlattice structure is inserted between a multiple quantum well active layer and an electronic barrier layer so as to improve the hole concentration and reduce the dosage concentration of the P-type hole injection layer; the superlattice structure has polarization effect, thus being capable of improving the doping efficiency and reducing the P-type impurity concentration; and impurity atoms are prevented from being diffused to the potential well, and the inner quantum efficiency and the luminous efficiency of the device can be improved. The invention also discloses a preparation method of the nitride LED structure, through inserting the P-type doped InGaN/GaN superlattice structure between the multiple quantum well active layer and the electronic barrier layer, the hole concentration can be improved, and the dosage concentration of the P-type hole injection layer can be reduced; since the superlattice structure has polarization effect, the doping efficiency can be improved and the P-type impurity concentration can be reduced; and the impurity atoms are prevented from being diffused to the potential well, and the inner quantum efficiency and the luminous efficiency of the device can be improved.

The invention discloses a method for manufacturing an insulated gate bipolar transistor (IGBT) device. The method sequentially comprises an ion injection step of forming a p type heavily doped collecting region on the back side of a silicon wafer, a partial or whole annealing step and a step of depositing surface metal on the front side of the silicon wafer; and after the p type heavily doped collecting region is formed on the back side of the silicon wafer, a layer of silicon dioxide is deposited on the back side of the p type heavily doped collecting region. The method has the advantages that the temperature limitation of the p type ion annealing on the back side of the silicon wafer is eliminated, and high activity rate is easy to obtain. Simultaneously, the p type impurity distribution in the p type heavily doped collecting region can be optimized. On one hand, the ohmic contact with back metal is easy to form, on the other hand, the emission efficiency of a precision navigation processor (PNP) is favorably controlled, and the alternating current characteristic of the IGBT device is improved.

A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a contact interlayer, and further diffused to optimize a trade-off between Rds and the avalanche capability. Thus, only three masks are needed in fabrication process, which are trench mask, contact mask and metal mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Guassian-distribution from trenched source-body contact to channel region.

A pixel cell including a substrate of a first conductivity type over an epitaxial layer of a second conductivity type. The epitaxial layer has a dopant gradient, wherein the dopant concentration decreases from a surface of the epitaxial layer adjacent the substrate to the surface of the epitaxial layer opposite the substrate. A photo-conversion device is at a surface of the epitaxial layer.

The invention provides a bidirectional tri-path turn-on high-voltage ESD (Electro-Static Discharge) protective device which can be used in an on-chip IC (Integrated Circuit) high-voltage ESD protective circuit. The bidirectional tri-path turn-on high-voltage ESD protective device comprises a P minus substrate, an N plus buried layer, a left N-type epitaxy, a right N-type epitaxy, a drifting area, a high-voltage P trap, a drain region, a source region, a polysilicon gate, a positive pole contact area and a negative pole contact area, wherein the drifting area, the high-voltage P trap, the drain region, the source region and the polysilicon gate form an NLDMOS (laterally diffused metal oxide semiconductor) structure, and the positive pole contact area, the N plus buried layer, the high-voltage P trap and the source region form a positive SCR (semiconductor control rectifier)structure, so that two high-voltage ESD current discharge paths are formed to improve secondary striking current of the device and reduce the turn-on resistance and trigger voltage; and the negative pole contact area, the left N-type epitaxy, the high-voltage P trap, the N plus buried layer and the drain region form a reverse SCR structure to form a reverse high-voltage ESD current discharge path. The current paths of the two SCR structures are longer, so that the maintaining voltage of the device can be improved, bidirectional discharge of ESD current can be realized, and the device has bidirectional ESD protection function.

The invention relates to a semiconductor LED (Light-Emitting Diode) chip and a manufacturing method thereof. The semiconductor LED chip comprises a transparent conductive layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer, a p-type contact layer, a dielectric insulating layer, an n-type contact layer, a bonding metal layer and a substrate, wherein the n-type contact layer reaches the interior of the n-type semiconductor layer or penetrates through the whole n-type semiconductor layer by virtue of through holes penetrating through each layer at the upper part of the n-type contact layer. The manufacturing method for the semiconductor LED chip comprises the following steps of manufacturing an epitaxial wafer, bonding the epitaxial wafer to another conductive or insulating substrate, removing a growing substrate, and manufacturing the transparent conductive layer on the surface of the n-type semiconductor layer. According to the semiconductor LED chip and the manufacturing method thereof, a transparent conductive layer material is adopted as a current expansion layer, so that the thickness or doping concentration of the n-type semiconductor layer is reduced, light is favorably absorbed by an n-type material, and the light extraction efficiency of the LED chip is improved.

A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment of the present invention, the first doped region (28) is doped with arsenic, while the second doped region (26) is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer (28) allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.

The invention provides a GaN (gallium nitride)-based semiconductor laser and a manufacturing method thereof, belonging to the field of semiconductor lasers. The GaN-based semiconductor laser does not have an electronic barrier layer, thus reducing the working voltage of the laser and prolonging the service life of the laser. For the laser, a quantum cascade radiation layer is arranged between an n-type optical limited layer and an n-type waveguide layer of the laser and utilized to generate infrared radiation when the laser operates, thus realizing ionization of magnesium acceptor impurities in a p-type GaN waveguide layer and a AlGaN optical limited layer, improving carrier concentration in each p-type layer, increasing hole injection current, reducing leakage of electronics from an active area, avoiding introduction of a AlGaN electronic barrier layer and eliminating optical absorption loss caused by the magnesium-doped AlGaN electronic barrier layer, thereby reducing the threshold current of the laser, reducing the working voltage of the laser and prolonging the service life of the laser.

The invention relates to the technical field of crystalline silicon solar cells, and provides a regional layered deposition diffusion process in order to solve the problems of over-high surface dopingconcentration, weak regional diffusion controllability, poor cell blue light response and short minority carrier lifetime of an existing PERC+LDSE cell sheet. The process comprises the following steps: (1) pretreatment of a silicon wafer; (2) pre-oxidizing; (3) low-temperature low-concentration phosphorus source deposition; (4) high-temperature medium-concentration phosphorus source deposition; (5) forming of a PN junction; (6) depositing of a low-temperature high-concentration phosphorus source; (7) cooling, pushing of a quartz boat, and taking-out of the silicon wafer. Regional layered diffusion control is adopted in the process, so that a uniform phosphorosilicate glass layer is formed on the surface of a silicon wafer, the laser SE heavy doping is facilitated, and the ohmic contact and good contact performance of a battery piece are improved; and the emitter region has low doping concentration and high-quality PN junctions, so that the battery piece has the characteristics of excellent blue light response and long minority carrier lifetime, and finally, the conversion efficiency of the battery piece is improved.

The present invention relates to a method of selectively fabricating metal gate electrodes in one or more device regions by fully siliciding (FUSI) the gate electrode. The selective formation of FUSI enables metal gate electrodes to be fabricated on devices that are compatible with workfunctions that are different from conventional n+ and p+ doped poly silicon electrodes. Each device region consists of at least one Field Effect Transistor (FET) device which consists of either a polysilicon gate electrode or a fully silicided (FUSI) gate electrode. A gate electrode comprised of silicon and a Ge containing layer is used in combination with a selective removal process of the Ge containing layer. The Ge containing layer is not removed on devices with threshold voltages that are not compatible with the FUSI workfunction. Devices that are compatible with the FUSI workfunction have the Ge containing layer removed prior to the junction silicidation step. The remaining thin silicon layer of the gate electrode becomes fully silicided during the same step as the junction silicidation step.

The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

The invention relates to a nonpolar (1120)A side nitride film that comprises a silicon underlay, metal layer which grows upon the silicon underlay sequentially, InGaAlN initial growth layer and the first InGaAlN buffer layer, it characterized in that: said silicon underlay is Si underlay which adopts the (100) side, (110) side or offset angle. The nonpolar a side nitride film which grows on the silicon underlay can be used in LBD, laser, solar battery. The component extension configuration is adopted according to different component, for example the LBD and laser, and using the mature silicon craft further to produce relative diprosopia electrode component or peeling off component. Comparing with current technique, the advantages of the invention are: the invention can increase the growth quality of nonpolar GaN base material, and decrease the cost; the craft of current component can be simplified greatly, the cost can be decreased, and increase the elimination efficiency and lightening efficiency greatly.

The invention relates to a low-voltage MOSFET device with an antistatic protection structure and a manufacturing method therefor. A static protection region comprises a second conductive type well region positioned at the upper part of a first conductive type drift region, and an insulating supporting layer positioned above the second conductive type well region; the second conductive type well region penetrates through a terminal protection region; the insulating supporting layer is positioned on a first main surface of a semiconductor substrate and is in contact with the second conductive type well region; a polycrystalline silicon diode group is arranged on the insulating supporting layer; the polycrystalline silicon diode group comprises a first diode and a second diode; the negative electrode end of the first diode is connected with the negative electrode end of the second diode; the positive electrode end of the first diode is in ohmic contact with the a grid electrode metal on the upward side; and the positive electrode end of the second diode is in ohmic contact with the a source electrode metal on the upward side. The low-voltage MOSFET device is compact in structure, compatible with the existing technological steps, safe, reliable, and capable of improving the voltage resistance of the device with ESD (Electro-static Discharge) protection and reducing manufacturing cost.

The invention discloses a method of producing SiGe HBT transistors, which includes steps of reducing the doping concentration of emitter polysilicon, controlling the undercut dimension of an emitter window, increasing the thickness of an emitter monocystal silicon layer, and increasing the final activation temperature of devices, thereby maintaining bases out of highly defective areas and further greatly reducing the base recombination current.