34results about How to "Reduce recombination current" patented technology

A thin film solar battery structure and a manufacturing method thereof, and a thin film solar battery array are provided. The manufacturing method of the thin film solar battery structure includes: at least two first trenches are formed by etching semiconductor substrate from the first surface; at least one of the second trench is formed by etching the semiconductor substrate from the second surface; each of the second trench is located between two adjacent first trenches; a first structure is formed on the side wall of at least the first trench; a second structure is formed on the side wall of at least the second trench; the semiconductor substrate is cut or drawn from the first trench and the second trench for forming the thin film solar battery structure, the distance of the electrodes can be reduced effectively, the probability recombination of the electron and the hole can be reduced, the bulk recombination current and the surface bulk recombination current can be reduced, the efficiency of the electrical power can be increased, the thin film solar battery structure and the manufacturing method thereof can reduce the semiconductor material and reduce the manufacturing cost.

The invention provides a manufacturing method of a MWT (Metal Wrap Through) solar battery. The method comprises the steps of: providing a substrate which comprises a body layer, a reflection-reducing layer and a passivation layer, wherein a plurality of through holes and openings are arranged on the substrate; forming conductive electrodes in the through holes and forming a first back contact electrode on the back of the substrate; forming second back contact electrodes in the openings; forming a touch grid line electrode on the front face of the substrate; sintering the substrate so that the touch grid line electrode is electrically connected with the conductive electrode; and forming a local front surface field in the front surface of the body layer; and forming a local back emitting electrode in the back surface of the substrate. The MWT solar battery manufactured by the method is small in composite current, large in light receiving area and high in photoelectric conversion efficiency, and the problem that the battery is bended is reduced. In addition, according to the manufacturing method provided by the invention, steps such as diffusive knot manufacture, edge corrosion, glass layer removal and secondary clean in conventional process are avoided, so that the manufacturing process flow is simplified and the production cost is reduced.

The invention discloses a manufacture method for a twin pole device resisting low dosage rate irradiation. According to the invention, a multi-layer passivation structure employing PSG (Phosphorosilicate Glass) + SiO2 double-layer electrode isolation medium and SiO2+BPSG (Boron Phosphorosilicate Glass)+SiO2. By adopting the above structure, total number of defects in the electrode isolation medium layer is reduced substantially on one hand. On the other hand, through adsorption of positive charges of the PSG and the BPSG, accumulation of the positive changes generated in the irradiation environment on the surface of Si-SiO2 is prevented and further the low dosage rate irradiation resistance of the twin-pole device is improved. The manufacture method provided by the invention is simple in technical procedure and is compatible to Si manufacture technique that is widely applied currently, and can be used for manufacturing the twin pole device having low dosage rate irradiation resistance.

The invention provides a thin film strip structure, a manufacturing method the thin film strip structure, and a thin film strip structure array. The manufacturing method of the thin film strip structure comprises the following steps: providing a semiconductor substrate; forming at least one dent or a row of separating holes on a first surface and / or a second surface of the semiconductor substrate; etching the semiconductor substrate from the first surface to form at least two first grooves, and etching the semiconductor substrate from the second surface to form at least one second groove; and separating the semiconductor substrate from the dent or the separating holes, and cutting or stretching the semiconductor substrate from the first grooves and the second grooves to form the thin film strip structure. With the adoption of the thin film strip structure, the damage to the strip structure and the thin film when separating the thin film strip structure from the semiconductor substrate can be effectively reduced, and the production rate can be increased. The thin film strip structure and the manufacturing method of the thin film strip structure also can save the semiconductor material and reduce the manufacturing cost.

The invention discloses a CMOS integrated process BJT structure, which comprises: P wells and N wells arranged side by side on a silicon substrate, a first shallow trench isolation is formed at the boundary between the P well and N well, and a first shallow trench isolation is formed in the P well. Two shallow trench isolations, a first P+ doped region is formed in the P well between the first and second shallow trench isolations, and a first N+ doped region is formed in the N well next to the first shallow trench isolation , a second N+ doped region is formed in the P well on the other side of the second shallow trench isolation, and a parallel first electrode and a metal silicide barrier layer are formed on the second N+ doped region, and the first P+ doped region A second electrode is formed on the first N+ doped region, and a third electrode is formed on the first N+ doped region; before the source-drain region ion implantation process, a flat layer is deposited, source-drain region ion implantation is performed, a metal silicide barrier layer is deposited, and metal silicide is performed. The blocking layer is etched to form the first electrode to the third electrode. The invention also discloses a BJT manufacturing method of CMOS integration technology. The invention can improve the uniformity of the current gain of the transistor, and can realize precise adjustment of the current gain.

The invention discloses a method of producing SiGe HBT transistors, which includes steps of reducing the doping concentration of emitter polysilicon, controlling the undercut dimension of an emitter window, increasing the thickness of an emitter monocystal silicon layer, and increasing the final activation temperature of devices, thereby maintaining bases out of highly defective areas and furthergreatly reducing the base recombination current.

The invention belongs to the technical field of solar cell manufacturing, and relates to a step-by-step phosphorus doping method of a high-efficiency and low-cost crystal silicon cell, namely a primary depletion diffusion combined with secondary high-concentration shallow layer diffusion and back etching method. By controlling the flow of oxygen, A low-temperature low-phosphorus source depositionis carry out for that first time on a p-type silicon substrate by nitrogen flow rate and phosphorus oxychloride flow rate, After a long time of high temperature propulsion, the phosphorus in the phosphor-silicate glass is exhausted, and the low surface concentration layer n + is realized. The second time, the phosphor-free glass is deposited on the phosphor-silicate glass, and the high surface concentration layer n + + is pushed to form a very thin high concentration layer, which can be quickly etched off by means of back etching. The method can accurately control the phosphorus doping distribution in different regions independently to ensure that the non-electrode region has low doping concentration and low recombination current so as to ensure higher open-circuit voltage. The electrode region has high doping concentration, which forms good ohmic contact with the metal electrode and ensures that the filling factor is not lost, so as to improve the photoelectric conversion performanceof the battery as a whole.

The invention discloses a method for implementing a base region window of a silicon germanium heterojunction transistor, which comprises the following steps of: depositing a composite dielectric film on a silicon chip with an embedded layer, a collector region and a substrate isolation region on a silicon substrate; performing dry etching on the composite dielectric film, defining the base region window, and etching an oxide film stopped on the composite dielectric film; after the base region window is opened and before the oxide film of the composite dielectric film is removed, depositing a dielectric film layer, and forming a D-shaped side wall at the interface step of the base region window by using the dielectric film layer; and meanwhile, performing wet removal on the residual oxide film in the base region window by using the protection of the D-shaped side wall, and epitaxially growing an SiGe base region. The interface step of the base region window is changed slowly because of the formation of the D-shaped side wall, and the slowly changed step formed by the D-shaped side wall is continuously reserved after SiGe extension and has no insulator residue in the subsequent emitter polycrystalline silicon side wall process, so that continuous metal silicide is formed, the resistance of an outer base region is reduced, and the performance of the device is improved.

The invention provides a BJT device structure and a manufacturing method thereof. The structure comprises a P well; an N+ region which is positioned on the P well; a barrier layer structure which is located on the N+ region and is a frame-shaped structure surrounding the periphery of the N+ region, wherein the region in the barrier layer structure is an emitter region of the BJT device, the N+ region of the emitter region is provided with a plurality of STI regions which are arranged at intervals, and the upper surface of the P well is higher than the bottoms of the STI regions; a base region which is positioned on the periphery of the emitter region; and a collector region which is positioned on the periphery of the base region. The BJT device structure and the manufacturing method thereof have the following beneficial effects: the BJT device structure can significantly reduce the recombination current of the emitter region and the base region due to the fact that the STI region of the emitter region is a discontinuous structure. Therefore, the amplification coefficient of the BJT device is effectively improved.