The application discloses a
clock tree synthesis method based on clustering and
reinforcement learning collaborative optimization, and relates to the technical field of
integrated circuit design and
electronic design automation. The method comprises the following steps: firstly, reading the coordinates of flip-
flops, the position of
clock sources and design constraint parameters in a circuit; secondly, clustering and grouping the flip-
flops in the circuit through a clustering method, generating an initial hierarchical
clock tree topology and determining the candidate
insertion positions of buffers; thirdly, constructing a
reinforcement learning environment, defining a
state space, an action space and a multi-objective reward function; fourthly, within displacement constraints, learning a flip-flop
relocation strategy and a buffer
insertion and removal strategy by maintaining independent moving Q tables and action Q tables; and finally, evaluating performances such as
clock skew and
delay, generating a synthesis performance
evaluation result, and iteratively optimizing and judging through a closed-loop feedback mechanism. The application effectively controls
clock skew and
delay, avoids the local optimal problem of traditional methods, and improves the
clock tree synthesis quality and
automation efficiency.