26results about How to "Improve leakage current" patented technology

The present invention relates to the field of semiconductor technology, and proposes a semiconductor device with a shallow trench isolation structure, the semiconductor device comprising a substrate, a buffer layer and an insulating dielectric layer; at least one trench is provided on the substrate; the buffer layer is provided on the trench wall of the trench; the insulating dielectric layer is provided on the surface of the buffer layer and fills the trench. In the semiconductor device with a shallow trench isolation structure of the present invention, it is difficult for hot carriers to jump to the insulating dielectric layer, so that no conductive channel is formed, and the leakage current of the semiconductor device can be improved; the buffer layer is provided between the substrate and the insulating dielectric layer, and the stress between the substrate and the insulating dielectric layer can be improved.

The invention discloses a laminated aluminum electrolytic capacitor and a preparation method thereof. The preparation method comprises the following steps: S100, cutting an aluminum foil; s200, depositing on the surface of the aluminum foil through metal sputtering to form an aluminum oxide film; s300, the sputtered aluminum foil is subjected to multi-step heat treatment and quenching treatment; s400, depositing a conductive polymer on the aluminum oxide to serve as a cathode of the capacitor; s500, covering the conductive polymer with a graphite layer; s600, covering the graphite layer with a silver paste layer; s700, stacking a plurality of aluminum foils coated with the silver paste layers together to form a laminated capacitor structure; and S800, packaging and aging are carried out. The aluminum oxide film formed on the aluminum foil of the laminated aluminum electrolytic capacitor provided by the invention is uniform, flat and compact, the laminated aluminum electrolytic capacitor is small in leakage current and long in service life, and the leakage current of the laminated aluminum electrolytic capacitor cannot be obviously increased along with the increase of service time.

The invention discloses a transistor, a semiconductor device, a preparation method thereof and electronic equipment. The transistor comprises a source electrode, a channel region and a drain electrode which are sequentially arranged along a first direction, and a grid electrode which is arranged at the periphery of the channel region in an insulating manner; the source electrode comprises a first semiconductor layer and a second semiconductor layer, the same ends of the first semiconductor layer and the second semiconductor layer in the first direction are connected with the channel region, and the second semiconductor layer is located on the side, close to the grid electrode, of the first semiconductor layer in the direction perpendicular to the first direction. The doping concentration of the first semiconductor layer is smaller than that of the second semiconductor layer. The invention relates to the technical field of semiconductor devices, in particular to a transistor, a semiconductor device, a preparation method of the semiconductor device and electronic equipment, and aims to restrain accumulation of holes in a channel as a starting point, relieve formation of a parasitic bipolar transistor and prolong storage retention time.

An AC arrester, characterized in that it includes an arrester body, the arrester body includes a fixed element and a controlled element, and characterized in that the arrester also includes: a thyristor-controlled switch branch connected in parallel with the controlled element; a voltage-equalizing branch connected in parallel with the fixed element; and voltage equalization of the fixed element and the controlled element of the arrester body is achieved by adjusting the resistance of the voltage-equalizing resistor and the capacitance of the capacitor in the voltage-equalizing branch respectively. This prevents the arrester fixed element from having a high voltage division under steady-state conditions, which increases the leakage current.

This invention relates to a display panel and a display device including the display panel. The display panel includes: a pixel circuit connected to a data line, a plurality of gate lines, a plurality of constant voltage nodes, a first light-emitting element, and a second light-emitting element; a first gate driver configured to output a first scan signal; a second gate driver configured to output a second scan signal; and a multiplexer configured to select the first scan signal, the second scan signal, and a gate cutoff voltage, and output them to the corresponding gate lines.

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: forming a dummy gate structure crossing a channel stack; source and drain grooves are formed in the channel lamination layer on the two sides of the pseudo gate structure and a part of thickness of the substrate; forming an isolation side wall on the side wall of the substrate exposed out of the source-drain groove; and forming a source-drain doping layer in the source-drain groove, wherein the source-drain doping layer is in contact with the side wall of the isolation side wall. According to the embodiment of the invention, the source-drain doping layer is isolated from the side wall of the substrate through the isolation side wall, and the isolation side wall can achieve a blocking effect on a leakage current channel between the source-drain doping layer and the substrate at the bottom of the channel lamination layer; in addition, the isolation side wall can also play a role in blocking diffusion of doping ions in the source-drain doping layer to the substrate at the bottom of the channel lamination layer, the problem of leakage current between the source-drain doping layer and the substrate can be improved, and the performance of the semiconductor structure is improved.

The invention discloses a gallium nitride epitaxial wafer using a buried layer type silicon substrate and a preparation method of the gallium nitride epitaxial wafer, and belongs to the technical field of semiconductor materials, the buried layer type silicon substrate sequentially comprises a surface layer, a buried layer and a base layer from top to bottom, the surface layer is made of silicon, and the thickness of the surface layer is 1-2000 nm; the buried layer is made of a silicon oxide insulating material, and the thickness of the buried layer is 1-50 microns; the base layer is made of silicon, the thickness of the base layer ranges from 50 micrometers to 1500 micrometers, and nitriding treatment is carried out on the surface layer before the aluminum nitride nucleating layer grows on the buried layer type silicon substrate. According to the invention, the problem that the operation loss of the silicon-based gallium nitride power device is obviously increased when the frequency is increased is avoided, the stress problem existing in the silicon-based gallium nitride heteroepitaxy process is improved, and the electric field voltage withstanding characteristic of the gallium nitride epitaxial structure is obviously improved.

The utility model discloses a thin film transistor structure based on a carbon nanotube, comprising an epitaxial layer, the surface of which is provided with an occupying groove; the top of the substrate layer is fixedly connected with the bottom of the epitaxial layer; the top of the metal layer is fixedly connected with the bottom of the substrate layer, and the metal layer is made of aluminum; the high-K dielectric material is located at the top of the epitaxial layer and fixedly connected with the epitaxial layer, and the shape of the high-K dielectric material is rectangular; the utility model relates to the technical field of transistors. According to the thin film transistor structure based on the carbon nano tube, the high-k dielectric material is used for replacing silicon dioxide to serve as a gate medium, the high-k dielectric material has a high k value and has good thermal stability with silicon, and the high-k material is prevented from reacting with the silicon substrate at high temperature.

This invention discloses a photoresist stripping device that avoids parasitic gate effects and murex patterns. The photoresist stripping device is sequentially configured with a drying zone, a stripping zone, a hot water washing zone, an ultracooled water washing zone, and an air drying zone according to the substrate transport direction. A hot air knife for blowing hot air onto the substrate surface is provided at the outlet of the stripping zone. A second spray pipe for spraying hot water onto the substrate surface is provided in the hot water washing zone. A cold air knife for blowing cold air onto the substrate surface is provided at the inlet of the ultracooled water washing zone. A third spray pipe for spraying ultracooled water onto the substrate surface is provided in the ultracooled water washing zone. The photoresist stripping device also includes a vortex tube, a heating device, and a cooling device. This invention avoids the product yield and quality risks caused by parasitic gate effects and murex patterns; it also ensures the versatility of the photoresist stripping equipment, which is beneficial for production line logistics optimization and capacity improvement.

This invention relates to the field of silicon nitride etching technology, specifically a method for dry etching of silicon nitride using extremely low power, comprising the following steps: S1. Fixing the workpiece to be etched on the chuck of a plasma etching machine, closing the chamber, and evacuating to a chamber background pressure ≤2mTorr; S2. Introducing a composite etching gas into the chamber; S3. Starting a pulsed radio frequency power supply to excite the composite gas to generate plasma; S4. Adjusting various parameters of the chamber; S5. After etching is completed, evacuating the chamber, then introducing helium gas to purge the chamber until the chamber pressure returns to atmospheric pressure; S6. Introducing a mixed gas, ashing treatment, and then introducing H2 plasma to repair dangling bonds on the silicon nitride surface to complete the etching. This invention discloses a method for dry etching of silicon nitride using extremely low power, relating to the field of semiconductor manufacturing technology. This method, through the synergistic design of "precisely proportioned composite gas system + pulsed radio frequency excitation + multi-field coupling process control," achieves efficient, highly selective, and low-damage etching of silicon nitride layers at extremely low radio frequency power.

The invention provides a semiconductor device and a preparation method thereof, and belongs to the technical field of semiconductors. The active region is positioned in the substrate and extends along a first direction; the gate structure is located on the surface of the substrate and crosses the active region along a second direction, and the second direction is orthogonal to the first direction; the trench isolation structure is located in the substrate and surrounds the active region, grooves are formed in the edges of the two sides, making contact with the active region, of the trench isolation structure, and the grooves are located below the gate structure; the groove is filled with the wide bandgap semiconductor material layer, the wide bandgap semiconductor material layer is in contact with the edge of the active region, the top of the wide bandgap semiconductor material layer is in contact with the bottom of the gate structure, and the bandgap width of the wide bandgap semiconductor material layer is larger than that of the substrate. The performance of the semiconductor device can be improved.

The invention discloses a fuel rod sliding monitoring system based on a cadmium zinc telluride detector assembly array, and belongs to the technical field of nuclear radiation fuel rod monitoring. Comprising a cadmium zinc telluride detector assembly array; the tellurium-zinc-cadmium detector assembly array comprises a plurality of groups of tellurium-zinc-cadmium detector assemblies, each group of tellurium-zinc-cadmium detector assemblies independently works and is in parallel communication with the host module through an independent communication interface, the host module is used for processing data returned by the tellurium-zinc-cadmium detector assemblies in parallel, and the tellurium-zinc-cadmium detector assemblies are arranged around the fuel rod in a surrounding manner; the host module is used for setting assembly parameters of the tellurium-zinc-cadmium detector assembly, monitoring data returned by the tellurium-zinc-cadmium detector assembly in real time, and starting the alarm control device and triggering emergency measures if abnormity is found. A plurality of groups of independent tellurium-zinc-cadmium semiconductor detector assemblies are used to form an annular array, so that the detection area of the system is increased, and the detection sensitivity of the fuel rod is improved.

The application discloses a semiconductor device and a manufacturing method thereof, and a storage system. The semiconductor device comprises a channel structure, a capacitor structure, a bit line and a word line. The channel structure extends along a first direction. The bit line and the capacitor structure are connected to two ends of the channel structure along the first direction respectively. The word line comprises a word line part and a unidirectional conduction part which are connected to each other, and the word line part and the unidirectional conduction part cover at least part of the channel structure respectively.

The invention discloses a local medium modulated transverse super junction silicon carbide device, and belongs to the technical field of semiconductor power devices. The device comprises a semiconductor substrate, a buried oxide layer, a silicon carbide active layer and a metal layer which are sequentially stacked from bottom to top, the silicon carbide active layer comprises a local dielectric region and a super-junction structure, and the dielectric region partially covers the two sides of the super-junction structure and the surface of a small-width part. A medium with a high dielectric constant is used for replacing a common silicon oxide gate medium to improve the problem of gate leakage current, the turn-on voltage of the device is reduced, meanwhile, a local medium is introduced to introduce a new electric field peak in a drift region, electric field distribution is modulated, the charge unbalance effect of a transverse super-junction structure is improved, and the performance of the device is improved. The drift region concentration is optimized, the on-resistance of the device is reduced, and the performance and reliability of the device are improved.

The utility model discloses a filter for medical frequency converter, including connector J1 and connector J2, the one foot of connector J1 is connected respectively piezo -electric resistance MOV1, piezo -electric resistance MOV3, inductance L1 one foot, electric capacity C2 and electric capacity C3, piezo -electric resistance MOV1 other end connects inductance L1 three feet, piezo -electric resistance MOV3 other end connects gas discharge tube and piezo -electric resistance MOV2 respectively, gas discharge tube ground connection, piezo -electric resistance MOV2 other end connects inductance L1 three feet, electric capacity C2 other end connects electric capacity C1, electric capacity C1 ground connection, electric capacity C3 other end ground connection, inductance L1 two feet connects electric capacity C5, electric capacity C4, resistance R1 and inductance L2 one foot respectively, electric capacity C4 other end ground connection, resistance R1 other end connects electric capacity C10, electric capacity C10 ground connection, electric capacity C5 other end connects inductance L1 four feet.

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate for forming a first-type doped transistor, comprising a plurality of discrete active regions and an isolation region between the active regions; forming a polysilicon gate located in the active region and the isolation region on the substrate; removing the polysilicon gate located in the isolation region, and forming an opening in the polysilicon gate; filling a metal gate in the opening, the metal gate comprising a work function layer located at the bottom of the opening, the material of the work function layer comprising a second-type work function metal, the second type being different from the first type. The embodiments of the present invention are conducive to improving the problem of leakage current and enhancing the matching degree of the device.

The embodiments of the present disclosure provide a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate; memory cells arranged in an array along a first direction and a third direction on a surface of the substrate; the memory cells at least comprise a channel structure and a drain arranged along a second direction; the channel structure comprises a first channel region and a second channel region; an electron mobility of a bulk material of the channel structure is greater than an electron mobility of a bulk material of the drain; the second channel region is connected with the drain, and a size of the second channel region is less than or equal to a size of the first channel region.

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate and one or more sequentially stacked channel lamination layers located on the substrate, and each channel lamination layer comprises a sacrificial layer and a channel layer located on the sacrificial layer; forming a pseudo gate structure which stretches across the channel lamination layer on the substrate; doping inversion ions in the channel lamination layers at the two sides of the pseudo gate structure, wherein the doping type of the inversion ions is different from the channel conduction type of the MOS transistor; removing the channel lamination layers at two sides of the pseudo gate structure to form a source-drain groove, and forming an inversion doping region by using the residual inversion ions in the edge of the channel layer at the side wall of the source-drain groove; and forming a source-drain doped layer in the source-drain groove, wherein the source-drain doped layer is adjacent to the inversion doped region. According to the embodiment of the invention, the performance of the semiconductor structure is optimized.

The application relates to a triode for improving the uniformity of leakage current, belonging to the technical field of semiconductors. The triode is provided with a plurality of resistive substances located on the top surface of the second heavily doped emitter region; the heights of the resistive substances decrease from the middle part to the side part; the emitter electrode is provided with a plurality of resistive substances respectively located on the top surface of the resistive substances; the leakage current and the junction temperature of the central region, the sub-central region and the peripheral region of the triode are regulated in different degrees, so that the leakage current of the central region is low and the leakage current of the peripheral region is high, thereby the junction temperature of the central region, the sub-central region and the peripheral region of the triode is kept consistent, the purpose of reducing the leakage current of the device and the junction temperature of the weak region of the triode is achieved, and compared with the common triode, the central weak region with the highest junction temperature does not exist, so that the device can bear greater current and voltage stress.

The present invention relates to the field of semiconductor technology, and proposes a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a substrate; an isolation structure formed in the substrate; and a word line, wherein the word line includes a first convex portion and a second convex portion, wherein the first convex portion and the second convex portion are located in the isolation structure, and the depth of the first convex portion is greater than the depth of the second convex portion. The first convex portion has a longer depth, which can enhance the control ability of the word line on the transistor channel and improve the leakage current.

The embodiment of the invention provides an array substrate and a display panel, and relates to the technical field of display. The array substrate comprises a driving transistor, a switching transistor and a dehydrogenation hole, wherein the distance between the dehydrogenation hole and a channel of the driving transistor is smaller than the distance between the dehydrogenation hole and a channel of the switching transistor. Through the dehydrogenation hole, the channel of the driving transistor can be subjected to more thorough dehydrogenation treatment, so that the driving transistor has a relatively large sub-threshold swing, meanwhile, the influence of the dehydrogenation treatment on the switching transistor can be reduced, the leakage current of the switching transistor is improved, and the reliability of the switching transistor is improved. Therefore, the grid voltage of the driving transistor can be well kept in the low-frequency refreshing scene, the influence of current fluctuation on the display brightness is reduced, the splash screen problem caused by overlarge leakage current of the switching transistor is solved, the display effect of the display panel in the low-frequency refreshing scene is improved, and the use experience of a user is improved.

The utility model discloses a self-healing insulating power cable terminal accessory, which relates to the technical field of insulating power cables and comprises an accessory body, and a sealing mounting mechanism is arranged at one end of the accessory body. Through the arrangement of the sealing installation mechanism, the effect of sealing the connecting position can be achieved, in the using process, the upper clamping hoop and the lower clamping hoop are connected through the cooperation of the bolt and the nut, the sealing ring is installed and fixed to the connecting position through the upper clamping hoop and the lower clamping hoop, the connecting position is sealed through the sealing ring, and the sealing effect is good. The problems that water, moisture and dust enter, cable insulation is damaged, leakage current is increased, insulation resistance is reduced, partial discharge is caused, even cable breakdown short circuit is caused, water and moisture corrode cable conductors and metal parts of terminal accessories, contact resistance is increased, the connecting position is heated, and the service life of the cable is prolonged due to the fact that the connecting position cannot be sealed can be solved. Therefore, the service life of the cable terminal accessory is ensured.

The invention discloses a high-power laser diode based on a gradient aluminum gallium nitride electron blocking heterojunction, wherein the laser diode is an n-type lower confinement layer, a lower waveguide layer, an active region, an upper waveguide layer, a p-type gradient Al x Ga 1‑x N layer and p-type GaN contact layer, in which the p-type graded Al x Ga 1‑x The Al component content x of the N layer changes linearly from a certain value of 0.1 to 0.2 from bottom to top to 0. In the laser diode of the present invention, the gradient AlGaN layer simultaneously bears the functions of the light field limiting layer and the electron blocking layer. Compared with the traditional laser structure of the electron blocking layer plus the limiting layer, the gradient layer structure of the present invention realizes a higher electron barrier through doping modulation, and has a larger barrier thickness, which is conducive to improving the power of the laser diode. Under high-power working conditions, it has a better electron blocking effect, significantly reduces the leakage current, and has a better hole injection effect, thereby improving the device efficiency.

The invention relates to the technical field of microelectronic devices, and in particular to a silicon carbide power device and a processing and manufacturing method thereof; the invention firstly adopts a high-temperature vapor deposition method to prepare a silicon carbide ingot, then shapes the silicon carbide ingot to obtain a silicon carbide crystal rod, then slices the silicon carbide ingot to obtain a silicon carbide wafer, then grinds, polishes, detects and cleans the silicon carbide wafer in sequence to obtain a silicon carbide substrate, then prepares a silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate by a chemical vapor deposition method to obtain a silicon carbide wafer, then injects aluminum ions into the silicon carbide wafer by an ion implanter to form a P-type doping region and nitrogen ions to form an N-type conductive region of a drain and a source, and then prepares a junction barrier Schottky diode in a JFET region, etc.; the invention can effectively solve the problems of poor high temperature and high voltage tolerance, low switching speed and high production cost in the prior art.

The embodiment of the invention relates to the photovoltaic field, and provides a single crystal silicon rod drawing method which comprises the following steps: acquiring a first curve which is a relation curve between the equal diameter length and the resistivity of a single crystal silicon rod with a first dopant; acquiring a first preset length based on the first curve; the method comprises the following steps: adding a silicon material and a first doping agent into a crucible, sequentially carrying out a melting process, a seeding process and a shouldering process, and then entering an equal-diameter growth process; in the equal-diameter growth procedure, after the equal-diameter length of an initial crystal bar formed through equal-diameter growth reaches a first preset length, a second doping agent is added into the crucible, the equal-diameter growth procedure continues to be carried out till the equal-diameter length of the initial crystal bar reaches a second preset length, and then an ending procedure is carried out, a segregation coefficient of the first dopant is less than a segregation coefficient of the second dopant. The drawing method of the silicon single crystal rod provided by the embodiment of the invention at least can improve the uniformity of the resistivity of the drawn silicon single crystal rod.

This invention provides a JBS diode structure and its fabrication method. The JBS diode structure includes a substrate of a first conductivity type, an epitaxial layer of a first conductivity type, a well region of a second conductivity type, a first electrode, and a second electrode. The epitaxial layer is located on the upper surface of the substrate. Multiple well regions are spaced apart and located on the upper surface of the epitaxial layer. Each well region includes a first implantation region and a second implantation region. Multiple doped regions of the second conductivity type, stacked upwards sequentially, form the second implantation region. The lateral width of the doped region is greater than the lateral width of the first implantation region. The first electrode is located on the upper surface of the epitaxial layer and electrically connected to the epitaxial layer and the well regions. The second electrode is located on the lower surface of the substrate and electrically connected to the substrate. This invention adjusts the process for forming the well regions to create sharp, curved sidewalls, increasing the electric field strength at these sharp corners. This shifts the peak electric field strength of the device to the sharp corners of the well region sidewalls, reducing leakage current and increasing the reverse breakdown voltage of the device.