557results about How to "Lower breakdown voltage" patented technology

The present application is generally directed to ultrapure synthetic carbon materials having both high surface area and high porosity, ultrapure polymer gels and devices containing the same. The disclosed ultrapure synthetic carbon materials find utility in any number of devices, for example, in electric double layer capacitance devices and batteries. Methods for making ultrapure synthetic carbon materials and ultrapure polymer gels are also disclosed.

An MRAM device, and a process for manufacturing the device, provides improved breakdown distributions, a reduced number of bits with a low breakdown voltage, and an increased MR, thereby improving reliability, manufacturability, and error-free operation. A tunnel barrier is formed between a free layer and a fixed layer in three repeating steps of forming a metal material, interceded by oxidizing each of the metal materials. The oxidization of the third metal material is greater than the dose of the first metal, but less than the dose of the second metal. The fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.

An MOS device comprises a semiconductor layer of a first conductivity type and source and drain regions of a second conductivity type formed in the semiconductor layer, the source and drain regions being spaced apart from one another. A drift region is formed in the semiconductor layer proximate an upper surface of the semiconductor layer and between the source and drain regions, and a insulating layer is formed on the semiconductor layer above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the source and drift regions. The MOS device further includes a conductive structure comprising a first end formed on the insulating layer and spaced apart from the gate, and a second end formed on the insulating layer and extending laterally toward the drain region above at least a portion of the drift region. The conductive structure is configured such that a thickness of the insulating layer under the second end of the conductive structure increases as the second end extends toward the drain region.

In a battery system, battery modules (3a, 3b) connected to each other in series respectively include: one or more single cells (3a1 to 3an, 3b1 to 3b-n) connected to one another in any one of series, parallel, and series-parallel; cell voltage switches (7a, 7b) for detecting voltages respectively of the one or more single cells; module monitoring control units (9a, 9b) each for monitoring the detected voltages respectively of the one or more signal cells; and communications level converter circuits (14a, 14b). The battery system includes a master unit (8a) for receiving information on the voltages respectively of the one or more single cells from the module monitoring control units via the communications level converter circuits. One of the communications level converter circuits includes a switch element (Q32) for transmitting a signal of a low-potential battery module to a high-potential battery module. A series circuit includes resistors R1′, R2′ and R5 as well as the switch element is connected between a positive electrode of the highest-potential single cell in the high potential battery module and a negative electrode of the lowest-potential single cell in the low-potential battery cell.

Provided is a nonvolatile memory element which is capable of performing a stable resistance change operation at a low breakdown voltage.A nonvolatile memory element (100) includes: a first electrode layer (103); a second electrode layer (105); and a variable resistance layer (104) which is placed between the electrodes (103 and 105), and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a polarity of a voltage applied between the electrodes (103 and 105). The variable resistance layer (104) is formed by stacking a first oxide layer (104a) including an oxide of a first transition metal and a second oxide layer (104b) including an oxide of a second transition metal which is different from the first transition metal. At least one of the following conditions is satisfied: (1) a dielectric constant of the second oxide layer (104b) is larger than a dielectric constant of the first oxide layer (104a); and (2) a band gap of the second oxide layer (104b) is smaller than a band gap of the first oxide layer (104a).

A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.