21results about How to "Lower breakdown voltage" patented technology

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the base comprises a substrate and an epitaxial layer which are stacked; the main junction is positioned in the epitaxial layer; at least one field limiting ring located in the epitaxial layer; the junction termination extension region is located in the epitaxial layer; the junction termination expansion region and the field limiting ring have an overlapping region; the cut-off ring is located in the epitaxial layer; wherein the surfaces of one sides, far away from the substrate, of the main junction, the field limiting ring, the cut-off ring and the junction termination extension region are flush with the surface, far away from the substrate, of the epitaxial layer; the main junction, the field limiting ring and the cut-off ring are arranged at intervals along a first direction, and the first direction is perpendicular to a direction pointing to the main junction along the substrate; the field oxide layer is at least located on the sides, away from the substrate, of the epitaxial layer, the junction termination extension region and the cut-off ring; the field plates are respectively positioned on one sides, far away from the substrate, of the main junction and the field oxide layer; wherein the doping types of the substrate and the cut-off ring are the same, and the doping types of the main junction, the field limiting ring and the junction termination expansion region are the same. The semiconductor structure has a high withstand voltage level.

In the device, a plurality of low-temperature plasma reactors are fixed in an absorption liquid storage tank in an array manner, a quartz tube is immersed in liquid in the absorption liquid storage tank, and a plurality of through micropores are uniformly distributed in the bottom of the quartz tube; the lower end of the connecting fastener is fixed with the orifice of the quartz tube, and the side edge of the connecting fastener is provided with an air tube; the metal electrode is fixed through the upper end of the connecting firmware and extends into the quartz tube to serve as a high-voltage electrode; the discharge power supply is connected with the metal electrode and the ground electrode, so that the low-temperature plasma reactor generates bubble plasma in liquid; the electrolytic cell is communicated with an absorption liquid storage tank through a switch pipeline, the working electrode is provided with foamy copper as an electro-catalysis material, and the working electrode, the platinum wire counter electrode and the silver / silver chloride reference electrode form a three-electrode electrochemical structure to electrocatalytically synthesize ammonium nitrate in the electrolytic cell.

The invention discloses a wide bandgap power diode with a periodic composite anode, which comprises a wide bandgap semiconductor material substrate layer, a third anode groove, a wide bandgap semiconductor material epitaxial layer, and a periodic first anode groove and a periodic second anode on the wide bandgap semiconductor material epitaxial layer from bottom to top, a first dielectric layer and a second dielectric layer are sequentially arranged on the upper surfaces of the first anode groove and the wide bandgap semiconductor material epitaxial layer, a second dielectric layer is arranged on the upper surfaces of the second anode groove and the wide bandgap semiconductor material epitaxial layer, and a third dielectric layer is arranged on the third anode groove. And a metal anode and a metal cathode are respectively arranged on the upper surface of the wide bandgap semiconductor material epitaxial layer and the lower surface of the wide bandgap semiconductor material substrate layer. Benefited from the periodic composite anode structure, the device has the performance advantages of high current density, high breakdown voltage, low on-resistance and low reverse electric leakage.

The present invention relates to a low-capacitance low-clamping voltage transient voltage suppressor and a manufacturing method thereof. The low-capacitance low-clamping voltage transient voltage suppressor, based on the TVS tube structure, comprises an N-type silicon substrate N-sub silicon wafer, a P-type well PW, a P+ region, an N+ region, a dielectric, a ground metal layer Gnd, a power supply metal layer VCC, and a TVS device of a signal terminal IO1 and IO2 metal, characterized in that: at least the first to fourth P-type wells PW1-4 are included on the N-type silicon substrate N-sub or the grown N-type epitaxial layer N-epi, and the TVS tube is composed of a bipolar transistor composed of N+ / PW2 / PW3 / N+. The TVS tube of the low-capacitance low-clamping voltage transient voltage suppressor structure of the present invention is a bipolar transistor effect, which not only has the advantages of low breakdown voltage and trigger voltage, and faster protection response; it also has the characteristics of smaller on-resistance and clamping voltage, and stronger protection capability for subsequent integrated circuits.

The invention relates to the technical field of semiconductors, and relates to a semiconductor device and a manufacturing method thereof, and the manufacturing method comprises the steps: forming a stacked film layer on a substrate, and the stacked film layer comprises a first conductive layer, a first insulating layer and a second conductive layer which are sequentially stacked in the vertical direction; an opening is formed in the stacked film layer, and the opening penetrates through the second conductive layer in the vertical direction; a second insulating layer and a first sacrificial layer are formed, the second insulating layer at least covers the side wall of the opening, and the first sacrificial layer is located on the surface of the second insulating layer; removing part of the first insulating layer located at the bottom of the opening; forming a second sacrificial layer in the opening with the first sacrificial layer; and removing the residual first insulating layer at the bottom of the opening to form a groove exposing the first conductive layer. The manufacturing method disclosed by the invention can reduce structural defects and improve the electrical performance of a product.

The invention relates to a liquid-phase bubble induced discharge plasma oxidation water treatment device and a treatment method, and particularly belongs to the technical field of water treatment. The water treatment device provided by the invention comprises a plasma reactor, the plasma reactor comprises a high borosilicate glass container, the bottom end of the high borosilicate glass container is connected with a flange plate, openings are formed in the middle of the high borosilicate glass container and the middle of the flange plate, glass tubes are mounted at the openings, stainless steel tubes are sleeved with the glass tubes, and the stainless steel tubes are connected with the high borosilicate glass container. The liquid-phase bubble discharge mode is adopted, the influence of the solution conductivity on the plasma state is overcome, and under the condition of high conductivity, plasma discharge can be triggered, and the water treatment and purification effect is good. And in addition, under the condition that the breakdown voltage and the energy consumption are reduced, the technical effect that large-volume plasma can be generated in water / liquid can be achieved.

The invention discloses a SnO / beta-Ga2O3 power diode and a preparation method of the SnO / beta-Ga2O3 power diode, and a p-type SnO layer is deposited on a beta-Ga2O3 epitaxial layer to construct a SnO / beta-Ga2O3 vertical structure heterojunction diode or a heterojunction barrier diode. The reverse leakage current of the power diode is reduced and the reliability and the breakdown voltage of the device are improved by utilizing the depletion region of the II-type heterojunction, and meanwhile, the heterojunction has lower built-in potential, is expected to reduce the conduction power consumption and can be used for a high-voltage and high-power power electronic system.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

The invention belongs to the field of avalanche diodes, and particularly discloses a single-photon avalanche diode, a preparation method, an electronic element and a detector. The invention provides the P-doped well with concentration change, the single-photon avalanche diode with the curved surface junction structure is prepared by matching the P-doped well, and the single-photon avalanche diode can also be used for preparing an electronic element and a detector. According to the single-photon avalanche diode provided by the invention, the probability that photon-generated carriers converge to an avalanche region can be remarkably improved, and the detection efficiency is finally improved; and meanwhile, diffusion movement of carriers in the P-doped well region is utilized, so that the time for the carriers to move towards the avalanche region is shortened, and time jitter under the same photosensitive region thickness is reduced.

A unidirectional low-voltage transient suppression diode disclosed in the present invention comprises an N++ single crystal, an epitaxial P-region and a P-region formed in sequence on the surface of the N++ single crystal, an Nb+ buried layer region, an N+ region and a P+ region arranged in the P-region, a dielectric layer arranged above the P-region, a first metal layer arranged above the dielectric layer, a second metal layer and a deep groove arranged below the N++ single crystal, wherein the deep groove extends downward from the dielectric layer to the N++ single crystal. The unidirectional low-voltage transient suppression diode of the present invention introduces a low-voltage triode NPN composed of an N++ single crystal, a P-region and an Nb+ buried layer region to obtain a low breakdown voltage. Under the condition that the chip area remains unchanged, a lower breakdown voltage and a lower leakage current are obtained through a new structure and process design.

This invention provides a GGNMOS structure for electrostatic discharge (ESD) protection, comprising: a substrate, two sets of current discharge modules, and a ring-shaped heavily doped region. Each set of current discharge modules includes multiple discharge units; wherein each discharge unit includes: two source terminals, one drain terminal, two gate terminals, one floating heavily doped region, multiple lightly doped drain regions, and an isolation layer. In each discharge unit, this application forms a DN+ / Psub / P+ (Diode) by embedding a floating heavily doped region in the drain terminal. By adjusting the distance between the floating heavily doped region and the sub-drain terminal, the breakdown voltage of the Diode is made greater than VDD and less than the trigger voltage of the parasitic NPN. This allows the Diode to trigger before the parasitic NPN triggers, injecting a large number of electron-hole pairs into the substrate, increasing the substrate current, reducing the trigger voltage, and ensuring uniform device conduction, thereby improving the ESD protection performance of the GGNMOS.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a forming method thereof, a shallow trench is arranged in a drift region, a first shallow trench isolation structure first part and a first shallow trench isolation structure second part which are isolated from each other are arranged in the shallow trench, a first field plate is formed on the first shallow trench isolation structure first part, and a second field plate is formed on the second shallow trench isolation structure second part. A first field plate is formed on the first shallow trench isolation structure first part, a second field plate is formed on the first shallow trench isolation structure second part, a control gate is formed between the first shallow trench isolation structure first part and the first shallow trench isolation structure second part, the control gate is electrically connected with the first field plate, and the control gate is isolated from the second field plate. The LDMOS device has an unexpected technical effect, regulation and control of key parameter breakdown voltage and conduction impedance of the LDMOS device can be realized by adjusting the voltage applied to the control gate, the conduction impedance is obviously reduced on the premise of not changing the size of the LDMOS device, and meanwhile, the breakdown voltage is increased to a certain extent.

The application relates to a double-medium spacer symmetrical electrode discharge reactor and a plasma catalytic synthesis ammonia method. The reactor comprises an inner quartz medium pipe and an outer quartz medium pipe which are coaxially arranged, a high-voltage spiral electrode which is wound on the outer surface of the inner quartz medium pipe, a grounding spiral electrode which is wound on the outer surface of the outer quartz medium pipe, and a metal powder filling layer which is filled in the inner cavity of the inner quartz medium pipe. The outer quartz medium pipe is arranged on the periphery of the inner quartz medium pipe, and an annular discharge reaction cavity is formed between the outer quartz medium pipe and the inner quartz medium pipe. The high-voltage spiral electrode and the grounding spiral electrode are axially symmetrically distributed in space. The reactor provided by the application adopts a double-medium sandwich structure, and through the synergistic effect of the inner and outer quartz medium pipes and the high-voltage and grounding spiral electrodes which are symmetrically wound, a strong electric field which is uniformly coupled in space is realized, and the reactor is obviously superior to a traditional coaxial single-medium design.

The present application belongs to the field of avalanche diodes, and specifically discloses a single-photon avalanche diode and a preparation method, an electronic component, and a detector. The present application proposes a P-doped well with a concentration change, and a single-photon avalanche diode with a curved junction structure is prepared in conjunction with the P-doped well. The single-photon avalanche diode can also be used to prepare electronic components and detectors. The single-photon avalanche diode provided by the present application can significantly increase the probability of photogenerated carriers converging to the avalanche region, and ultimately improve the detection efficiency; at the same time, the diffusion movement of carriers in the P-doped well region is utilized to reduce the time for carriers to move to the avalanche region, thereby reducing the time jitter under the same photosensitive area thickness.

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a semiconductor structure, a bottom dielectric layer and a field plate structure, the semiconductor structure comprises a semiconductor layer and a gate structure located on the upper surface of the semiconductor layer, the semiconductor layer comprises a cellular region and a terminal region adjacent to the cellular region, and the gate structure is located on the upper surface of the terminal region. A source region and a drain region of the device are positioned on the upper surface layers of the semiconductor layers on two opposite sides of the gate structure; the bottom dielectric layer covers the upper surface of the semiconductor structure; the field plate structure is located on the upper surface of the bottom dielectric layer on the side, close to the drain region, of the gate structure, the field plate structure at least comprises an optimized field plate, and in the direction from the source region to the drain region, the size of the optimized field plate above the cellular region is larger than that of the optimized field plate above the terminal region. According to the invention, the optimized field plate is arranged in the field plate structure, so that the breakdown voltage of the device is improved, and the robustness of the device is improved.

The invention discloses a unidirectional low-voltage transient suppression diode, which comprises an N + + single crystal wafer, an epitaxial P-region and a P-region which are sequentially formed on the surface of the N + + single crystal wafer, an Nb + buried layer region, an N + region and a P + region which are arranged in the P-region, a dielectric layer arranged above the P-region, and a first metal layer arranged above the dielectric layer, and a second metal layer and a deep groove are arranged below the N + + single crystal wafer, and the deep groove extends downwards from the dielectric layer to the N + + single crystal wafer. According to the unidirectional low-voltage transient suppression diode, a low-voltage triode NPN composed of an N + + single crystal wafer, a P-region and an Nb + buried layer region is introduced to obtain low breakdown voltage. Under the condition that the area of the chip is not changed, lower breakdown voltage and lower leakage current are obtained through new structure and process design.

The embodiment of the utility model provides an integrated circuit device. The integrated circuit device comprises a semiconductor substrate; a transistor including a channel in the semiconductor substrate, a gate over the channel, a gate dielectric between the gate and the channel, source and drain regions on opposite sides of the gate, where the source and drain regions have a first doping type and the channel has an opposite second doping type; a drift region provided by the semiconductor substrate, the drift region having a first doping type, contacting the drain region and the channel, having a doping concentration lower than that of the drain region, and extending below the gate; the first deep trap is arranged below the drain electrode region, the first deep trap has a first doping type, and the doping concentration of the first deep trap is higher than that of the drift region; and a second deep well under the drain region and the first deep well, the second deep well having a second doping type, having a doping concentration higher than that of the drift region, and being in contact with the first deep well to form a diode.

The invention provides a trench type silicon carbide MOSFET device and a preparation method thereof, and the preparation method comprises the following steps: providing a semiconductor substrate, forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on the semiconductor substrate, forming a well region and a source region in the epitaxial layers, etching to form a virtual groove, wherein the virtual groove extends into the third epitaxial layer from the source region; ion implantation is carried out in the virtual groove to form an ion implantation region, the ion implantation region extends to the first epitaxial layer, and the conduction type of the ion implantation region is the same as that of the well region; respectively depositing a first insulating layer and a first polycrystalline silicon layer in the virtual groove to form a virtual groove structure, then forming a gate groove structure, forming a gate side wall on the side wall, higher than the source region, of a second polycrystalline silicon layer in the gate groove, and etching the second polycrystalline silicon layer in the gate groove until the top of the second polycrystalline silicon layer is lower than the upper surface of the source region; and forming an interlayer dielectric layer and a front metal layer.

The invention discloses a double-gate LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, the double-gate LDMOS device comprises a substrate, a buried gate layer, a body region, a drift region, a body electrode, a source electrode, a shallow trench isolation, a drain electrode and a gate oxide layer, wherein the body electrode and the source electrode are positioned in the body region and on the same side as the buried gate layer; the shallow trench isolation is positioned at the top of the drift region; the second grid electrode is positioned above the gate oxide layer; the buried gate layer sequentially comprises a first oxide layer, a first gate and a second oxide layer from bottom to top; and side walls are arranged at two ends of the second grid electrode. Through the arrangement of the buried gate layer, the depletion region can extend more in the N-type drift region, the electric field intensity between the source electrode and the drain electrode is reduced, and then the off-state voltage endurance capability is improved; besides, the structure can generate a channel at the buried gate layer in an on state, so that a current path is increased, the conduction current is increased under the same voltage, and the on-state conduction resistance is reduced while the off-state breakdown voltage is improved.

The invention relates to a system and a method for obtaining large-volume plasma by utilizing micro-cavity discharge. The system comprises a vacuum discharge chamber, a positive high-voltage direct-current power supply, a negative high-voltage direct-current power supply, a vacuum pump, a gas source, a mass flow meter, a barometer and the like, a positive bias anode and a micro-cavity cathode are arranged in the vacuum discharge chamber; the positive bias anode is formed by distributing air holes and molybdenum needles on a molybdenum sheet; according to the micro-cavity cathode, a ceramic sheet is clamped between two layers of molybdenum sheets, and a micro-cavity is formed in a cathode plate of a three-layer structure. The positive electrode of the positive high-voltage direct-current power supply is connected with the molybdenum sheet and the molybdenum needle of the positive bias anode and provides positive bias voltage for the positive bias anode; the anode of the negative high-voltage direct-current power supply is connected with an anode molybdenum sheet in the micro-cavity cathode through a current-limiting resistor R2, and the cathode of the negative high-voltage direct-current power supply is connected with a cathode molybdenum sheet in the micro-cavity cathode through a current-limiting resistor R1; and the negative high-voltage direct-current power supply is used for providing negative high voltage for the micro-hollow cathode. According to the invention, the generation volume of high-density plasma is increased, and the discharge volume can reach more than 10 cm < 3 >.

The invention discloses an MRAM (Magnetic Random Access Memory) device with an OTP (One Time Programmable) unit and a preparation method, which are applied to the technical field of MRAM devices, and the preparation method comprises the following steps: arranging a top wiring mask on the surface of a chip provided with a magnetic tunnel junction; the top connection line mask corresponds to an etching position of a preset OTP region and comprises at least one side wall of a magnetic tunnel junction of the OTP region; the chip is etched based on the top connection line mask until the magnetic tunnel junction in the OTP area corresponds to the side wall of the etching position, and an insulating layer of the magnetic tunnel junction is damaged; and filling a top connecting line groove formed by etching the chip with a conductive medium to form a top connecting line. And the optimization of the MRAM OTP in the writing direction is realized by etching and damaging the insulating layer on at least one side of the magnetic tunnel junction. And the front-end process of the preparation process is compatible with other processes, and a photomask is not additionally added, so that the MRAM device with the OTP unit can be manufactured with lower cost.