1results about How to "Lower breakdown voltage" patented technology

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.