4results about How to "Lower breakdown voltage" patented technology

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

This invention provides a GGNMOS structure for electrostatic discharge (ESD) protection, comprising: a substrate, two sets of current discharge modules, and a ring-shaped heavily doped region. Each set of current discharge modules includes multiple discharge units; wherein each discharge unit includes: two source terminals, one drain terminal, two gate terminals, one floating heavily doped region, multiple lightly doped drain regions, and an isolation layer. In each discharge unit, this application forms a DN+ / Psub / P+ (Diode) by embedding a floating heavily doped region in the drain terminal. By adjusting the distance between the floating heavily doped region and the sub-drain terminal, the breakdown voltage of the Diode is made greater than VDD and less than the trigger voltage of the parasitic NPN. This allows the Diode to trigger before the parasitic NPN triggers, injecting a large number of electron-hole pairs into the substrate, increasing the substrate current, reducing the trigger voltage, and ensuring uniform device conduction, thereby improving the ESD protection performance of the GGNMOS.

The application relates to a double-medium spacer symmetrical electrode discharge reactor and a plasma catalytic synthesis ammonia method. The reactor comprises an inner quartz medium pipe and an outer quartz medium pipe which are coaxially arranged, a high-voltage spiral electrode which is wound on the outer surface of the inner quartz medium pipe, a grounding spiral electrode which is wound on the outer surface of the outer quartz medium pipe, and a metal powder filling layer which is filled in the inner cavity of the inner quartz medium pipe. The outer quartz medium pipe is arranged on the periphery of the inner quartz medium pipe, and an annular discharge reaction cavity is formed between the outer quartz medium pipe and the inner quartz medium pipe. The high-voltage spiral electrode and the grounding spiral electrode are axially symmetrically distributed in space. The reactor provided by the application adopts a double-medium sandwich structure, and through the synergistic effect of the inner and outer quartz medium pipes and the high-voltage and grounding spiral electrodes which are symmetrically wound, a strong electric field which is uniformly coupled in space is realized, and the reactor is obviously superior to a traditional coaxial single-medium design.

The invention provides a trench type silicon carbide MOSFET device and a preparation method thereof, and the preparation method comprises the following steps: providing a semiconductor substrate, forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on the semiconductor substrate, forming a well region and a source region in the epitaxial layers, etching to form a virtual groove, wherein the virtual groove extends into the third epitaxial layer from the source region; ion implantation is carried out in the virtual groove to form an ion implantation region, the ion implantation region extends to the first epitaxial layer, and the conduction type of the ion implantation region is the same as that of the well region; respectively depositing a first insulating layer and a first polycrystalline silicon layer in the virtual groove to form a virtual groove structure, then forming a gate groove structure, forming a gate side wall on the side wall, higher than the source region, of a second polycrystalline silicon layer in the gate groove, and etching the second polycrystalline silicon layer in the gate groove until the top of the second polycrystalline silicon layer is lower than the upper surface of the source region; and forming an interlayer dielectric layer and a front metal layer.