83results about How to "Avoid premature breakdown" patented technology

The invention belongs to the technical field of electronic technologies and photoelectronic imaging technologies, in particular relates to a single-photon avalanche diode and a three-dimensional CMOS (Complementary Metal Oxide Semiconductor) image sensor based on the diode. The single-photon avalanche diode of the invention improves the traditional rectangular photosensitive PN junction into a regular octagon and can conveniently and simply weaken edge breakdown and improve gain uniformity. A two-dimensional pixel array of the three-dimensional CMOS image sensor based on the diode comprises unit pixels of the regular octagon-shaped single-photon avalanche diode and is arrayed in a honeycomb-shape, thereby being convenient for interpolation and improving resolution in horizontal and vertical direction.

The present invention provides a p-i-n-(-n)-type GaN single-photon avalanche detector. The detector comprises a p-GaN upper contact layer, an i-GaN avalanche multiplication layer, an n<->-GaN hole-injection layer and an n-AlGaN lower contact layer arranged from up to down, wherein the n<->-GaN hole-injection layer is light doping. The p-i-n-(-n)-type GaN single-photon avalanche detector replaces an n-GaN layer with a traditional pin-type structure with the n<->GaN/n-AlGaN heterojunction, takes the n<->-GaN as an absorption injection layer, and takes the n-AlGaN as the lower contact layer so as to facilitate the improvement of the crystalline quality of epitaxial materials of an active region and improve the external quantum efficiency and the cavity minority carrier injection efficiency; and moreover, the parameters, such as doping concentration, thickness and the like, of the n<->-GaN layer are flexible and adjustable, and a very high avalanche gain can be obtained under the low work bias through compromise optimization.

The invention discloses a silicon carbide avalanche photoelectric detector provided with a graphene transparent electrode and relates to a semiconductor photoelectric detector. The silicon carbide avalanche photoelectric detector is provided with a substrate, wherein a first N type epitaxial buffer layer, an N type epitaxial absorption layer, a second N<-> type epitaxial multiplication layer and aP<+> type ohmic contact layer which are homogeneous are sequentially arranged on the substrate; and multiple graphene transparent electrode layers grow on the surface of the P<+> type ohmic contact layer by virtue of an electrothermal decomposition process, and one height from the surface of a graphene layer to the surface of the first N type epitaxial buffer layer is etched by adopting a photolithography mask technology and an ICP etching process, so that the P<+> type ohmic contact layer, the second N type epitaxial multiplication layer and the N- type epitaxial absorption layer are circular truncated cones; and one compact SiOx/Si3N4 protection passivation layer is grown by virtue of a plasma enhanced chemical vapor deposition process. An N type ohmic contact electrode is sputtered onthe back of an N+ type substrate, and a bonding pad window is etched by virtue of a photolithography technology and a bonding pad for the graphene transparent electrode layers is prepared on the SiOx/Si3N4 protection passivation layer.

The invention belongs to the technical field of a semiconductor, in particular relates to a junction terminal structure of a transverse high-voltage power device. In the structure, the inner wall of an N-type shift region 2 and the inner wall of a P-type buried layer 9 in a curvature junction terminal structure respectively extend to the middle until to be connected with the inner wall of an N-type shift region 2 and the inner wall of a P-type buried layer 9 in a direct junction terminal structure, included angles of Alpha degrees are generated between the extension directions and the vertical directions of the inner walls of the N-type shift region 2 and the P-type buried layer 9 in the direct junction terminal structure, and the Alpha degrees is 45 degrees. By the junction terminal structure, the curvature effect of an electric field at a connection part can be effectively relieved; and on the vertical direction of the extension direction at the connection part, the distance of the P-type buried layer 9 exceeding the N-type shift region is 5 micrometers, and thus, the problem of charge unbalance is solved. The junction terminal structure has the advantages that the problems of charge unbalance in the connection part between the direct junction terminal structure and the curvature junction terminal structure and the curvature effect of the electric field at the connection part are solved, a device is prevented from being broken down in advance, and thus, optimal breakdown voltage is obtained.

The invention discloses a method for preparing double side dielectric groove part SOI material. Compared with the conventional bonding technology, before bonding, the method adds the following steps: 1. silicon groove etching on top layer silicon chip; 2. thermal growth and chemical vapor deposition of SiO2 layer; 3. removing the SiO2 layer positioned in a source area and under a channel region by etching; 4. deposition of polysilicon; 5. planarization of the polysilicon. As devices manufactured on the SOI material prepared by the method pass through reinforcing buried oxide layer electric field, the pressure resistance of the devices can be improved, and heat can be fully dispersed. Compared with devices with the conventional SOI structure, SOI devices prepared on the SOI material prepared by the method can utilize thinner top layer silicon and the buried oxide layer to reach the same pressure resistance, thus further reducing self-heating effect.

The invention belongs to the technical field of semiconductors, and particularly relates to a junction termination structure of a transverse high-voltage power device. According to the structure provided by the invention, in the connected part of a linear junction termination structure and a curvature junction termination structure, in the Y direction, a P-type buried layer exceeds an N-type drift region 5 microns; and meanwhile, the P-type buried layer also exceeds an N-type doped layer 3 microns. In an actual technology, an N-type drift region 2 is formed by ion injection; after annealing junction pushing, the N-type drift region diffuses towards the Y direction; and the P-type buried layer exceeds the N-type drift region 2 a certain distance, so that P-type impurities in the diffused N-type drift region are exhausted, therefore, the problem of unbalanced charge in the connected part of the linear junction termination structure and the curvature junction termination structure is solved, so as to obtain relatively optimized breakdown voltage. The junction termination structure has the beneficial effects that the problem of unbalanced charge in the connected part of the linear junction termination structure and the curvature junction termination structure is solved; and pre-breakdown of the device is avoided, so as to obtain the optimal breakdown voltage.

The invention discloses a double step field plate terminal based 4H-SiC Schottky diode, which mainly solves the problem that the breakdown voltage of a conventional double step field plate terminal based 4H-SiC Schottky diode is less than 1500V. The Schottky diode comprises an N + 4H-SiC substrate (1) and an N- 4H-SiC epitaxial layer (2). The back of the substrate is provided with an ohmic contact (3). The two sides of the epitaxial layer surface are provided with SiO2 passivation layers (4). The middle part of the epitaxial layer surface is provided with a metal field plate terminal (5). The schottky diode is characterized in that the passivation layers (4) and field plate terminal (5) are of a double step shape; the thickness of the double step passivation layers is identical to that of the double step field plate terminal, and the total thickness ranges from 350nm to 600nm. Because the field plate terminal is designed to be of a double step shape, the breakdown voltage of the 4H-SiC Schottky diode can reach 1800V or above; therefore, the diode breakdown ability improves, making it suitable for fabrications of large power integrated circuits.

The invention provides a semiconductor structure, a semiconductor assembly and a power semiconductor device. The semiconductor structure comprises a P-type semiconductor material layer, an N-type semiconductor material layer and multiple insulating material layers, wherein the N-type semiconductor material layer is adhered to the P-type semiconductor material layer, and forms a PN junction together with the P-type semiconductor material layer; the multiple insulating material layers are positioned on the outer side of the PN junction and are distributed along the laminated direction of the P-type semiconductor material layer and the N-type semiconductor material layer, and the relative dielectric constants of the adjacent insulting material layers are different. According to the semiconductor structure provided by the invention, the electric field distribution when the device is resistant to voltage is obviously optimized, and the breakdown voltage of the device is greatly improved; device voltage resistance drop caused by a junction edge electric field concentration effect is avoided, and pre-breakdown of the device is prevented; and a field ring and a metal field plate structure are avoided from being used, so that the chip area is decreased, the cost of the device is reduced, and the reliability of the device is improved.

The invention discloses a growth method of a surface passivation layer of a mesa detector. The growth method comprises the following steps of: forming a SiO2 passivation film on the surface of the mesa structure of a wafer by using a plasma chemical vapor deposition process in a low-temperature environment; coating a polyimide film on the SiO2 passivation film and carrying out gradient curing to densify the polyimide film; spin-coating a photoresist on the polyimide film to form a photoresist layer, and forming an exposure region on the photoresist layer; developing the photoresist layer of the exposure region, etching the polyimide film of the exposure region, and then removing the photoresist layer; performing imidization treatment on the polyimide film so that the polyimide film is fixed to the surface of the SiO2 passivation film; and etching the exposed SiO2 passivation film to set apart an electrode position. The growth method disclosed by the invention can be used for improving the passivation quality of the mesa detector, effectively reducing the surface leakage current of a device, preventing the device from premature breakdown, and improving the reliability of the device.

The invention discloses an L-type base region SiC MOSFET cellular structure, a device and a manufacturing method. The L-type base region SiC MOSFET cellular structure comprises an N++ SiC substrate, an N- SiC drift layer, a P-type base region and an N+ source region. The N- SiC drift layer is located above the N++ SiC substrate, a source trench and a gate trench are formed in the N- SiC drift layer, and a gate dielectric layer and a gate electrode are arranged in the gate trench. The P-type base region and the N+ source region are positioned on the N- SiC drift layer between the source trench and the gate trench and are arranged from bottom to top, an N-type current conducting layer is arranged between the P-type base region and the N- SiC drift layer, and a source N+ ohmic contact region is arranged between the P-type base region and the source trench. According to the device structure, the on resistance and the gate-drain capacitance can be further reduced, the conduction loss and the switching loss can be reduced, the working frequency can be improved, the premature breakdown of the P-type base region can be avoided, and the reliability of the device can be ensured.

The invention provides a junction termination structure of a transverse high-voltage power device, wherein the junction termination structure comprises a linear junction termination structure and a curved junction termination structure. The curved junction termination structure comprises a drain N<+> contact region, an N-type drift region, a P-type substrate, a gate polycrystalline silicon, a gate oxide layer, a P-well region, a source P<+> contact region and insulating medium, wherein the insulating medium comprises sub-mediums which are separated from each other. Each sub-medium extends from outside of the P-well region to outside of the N-type drift region. The annular drain N<+> contact region surrounds the annular N-type drift region. The annular N-type drift region surrounds the annular insulating medium. The annular insulating medium is used for insulating the P-well region. The annular insulating medium is arranged between the P-well region and the N-type drift region. The P-well region is not connected with the N-type drift region, and furthermore the distance between the P-well region and the N-type drift region is LP. The junction termination structure settles problems of charge unbalance and electric field curvature effect at the connecting part between the linear junction termination structure and the curved junction termination structure, thereby obtaining an optimal breakdown voltage.

The invention relates to a Ga2O3 Schottky diode based on a diamond terminal structure and a manufacturing method. The Schottky diode comprises a Ga2O3 epitaxial layer; an active region, located in the surface layer of the Ga2O3 epitaxial layer; a terminal region, located in the Ga2O3 epitaxial layer and located on the two sides of the active region. The terminal region comprises a plurality of first diamond terminal structures and a plurality of second diamond terminal structures, the first diamond terminal structures are arranged at intervals, and the second diamond terminal structures are arranged at intervals; the plurality of first diamond terminal structures and the plurality of second diamond terminal structures are alternately distributed up and down, and pn junctions are formed between the plurality of first diamond terminal structures and the Ga2O3 epitaxial layer and between the plurality of second diamond terminal structures and the Ga2O3 epitaxial layer. A surface electric field in the Schottky diode is intensively and gradually introduced into a device body, so that the phenomenon that the device is broken down in advance is avoided, the reliability of the device is improved, and the reverse voltage endurance capability of the device under normal static characteristics is improved.

The invention discloses a bipolar integrated circuit chip based on groove dielectric isolation and a production technology thereof, and belongs to the field of integrated circuit design/manufacturing. The production technology sequentially comprises the steps of N+ buried layer forming, lower isolation area forming, epitaxial layer forming, phosphorus bridge area forming, upper isolation area forming, groove forming and the like. According to the bipolar integrated circuit chip based on groove dielectric isolation, which is manufactured by the production technology, the inner side of an upper isolation area, the outer side of the upper isolation area and the outer side of a base area are respectively provided with an annular groove, the design size is lowered to the high limit, meanwhile, the maximum withstanding voltage of BVCBO is improved, and electrical performance maximization between electrodes within minimum spacing is achieved.

The invention provides a structure for improving the breakdown voltage of a gallium nitride HEMT power device and a preparation method of the structure. The structure comprises a substrate, an epitaxial layer, a source electrode, a drain electrode and a grid electrode. The epitaxial layer is arranged above the substrate and comprises a nucleating layer, a first material layer, a channel layer and a barrier layer which are arranged from bottom to top; the channel layer is internally provided with two-dimensional electron gas, and the barrier layer is internally provided with an ion doped region. The ion doping region is introduced between the grid electrode and the drain electrode, the two-dimensional electron gas concentration of partial region in the channel is changed, the electric field distribution is changed on one side of the grid electrode, the peak electric field is obviously lower than that of a device without the ion doping region, the electric field uniformity between the grid electrode and the drain electrode is enhanced, and the electric field distribution is effectively improved; and advanced breakdown of the device caused by a grid edge electric field peak value is avoided, and the device can bear higher drain voltage. And finally, the breakdown voltage of the device is improved, and the frequency characteristic of the device is not reduced.

The invention provides a high-voltage-withstand transverse super junction device. First doped type bars and second doped type bars which are alternated form a super junction structure; a second doped type multi-surface exhausting region is formed at an intersection of a second doped type well region and a region where the second doped type bars and the first doped type bars appear alternately; the second doped type bars and the second doped type well region form a three-surface exhausted structure for the first doped type bars; the left side and the right side are based on the same way; a first doped type multi-surface exhausting region exists on the right; and therefore, influence of an edge region on the voltage withstand of the device is reduced, a charge balance is remained, and the aims of avoiding in-advance breakdown by eliminating a high electric field at a super junction point AB and enhancing the voltage withstand of the device are fulfilled. As the peak of edge voltage is suppressed, under a condition of remaining high voltage withstand, the on-state resistance is reduced by further increasing the doping concentration of super junction bars; and therefore, the aims of eliminating the high electric field at the super junction point AB, enhancing the voltage withstand of the device and reducing the specific on-state resistance are finally fulfilled.

The invention provides a method for manufacturing a grooved MOSFET device on the basis of two-step microwave plasma oxidation. The method comprises the step that after a grooved gate is etched, silicon carbide on the surface of the grooved gate is oxidized into silicon dioxide by means of microwave plasmas to form a grooved gate oxide layer. The grooved gate oxide layer is formed through the stepsthat the silicon carbide substrate after the grooved gate is etched is placed in a microwave plasma generation device; first oxygen-containing gas is introduced, the temperature of generated oxygen plasmas rises to the first temperature at a first temperature rising speed, and low-temperature plasma oxidation is conducted at the first temperature under the first pressure; the temperature of the oxygen plasmas rises to the second temperature at a second temperature rising speed, second oxygen-containing gas is introduced, and high-temperature plasma oxidation is conducted at the second temperature under the second pressure until silicon dioxide with the predetermined thickness is generated; and the oxygen-containing gas stops being introduced, and the reaction is finished. According to themethod, the oxidation efficiency of silicon carbide can be significantly improved, the interface quality is improved, and the uniform gate dielectric layer is formed.