6results about How to "Avoid premature breakdown" patented technology

The invention discloses a power semiconductor device and a preparation method thereof. The power semiconductor device comprises a substrate, and the substrate comprises a substrate and an epitaxial layer located on the substrate; a plurality of first cells and second cells, wherein the first cells and the second cells are arranged in parallel in the first direction; the second cell comprises communication grooves penetrating from the surface of the epitaxial layer to the interior of the epitaxial layer, the communication grooves comprise second grooves and third grooves, and the third grooves are located between the adjacent second grooves and are communicated with the adjacent second grooves; the well regions are located in the epitaxial layer, the well regions extend into the epitaxial layer from the surface of the epitaxial layer, and the well regions are located on the two sides of the communicating groove; the second cell comprises a first region, a well region between adjacent second grooves of the first region in the second cell further comprises a first part well region and a second part well region, the first part well region is close to the third groove, the second part well region is far away from the third groove, the first source region is located on the surface of the second part well region, and no source region exists on the surface of the first part well region.

The utility model relates to an environmental protection type high pressure pulse line explosion type selective crushing device, include: pressure increasing device, energy storage device and discharge device, pressure increasing device is equipped with AC transformer, and energy storage device and discharge device are connected with AC transformer, discharge device includes control unit and electrode system that are connected in proper order in series, and control unit and electrode system all are connected with energy storage device, the utility model has the beneficial effect that: electrode top is hemispherical or conical, reduces the local concentration of electric field, prevents early breakdown, through electrode insulation design and sealing system, effectively prevent electrode from being eroded by vaporized metal wire, prolongs the service life of equipment, and simultaneously operating process is no dust, low noise, no harmful gas emission, accords with environmental protection requirement.

The invention provides a multi-channel power diode and a preparation method thereof, and belongs to the field of power electronics. The multi-channel power diode comprises an epitaxial layer, an anode layer and a cathode layer, the epitaxial layer comprises a plurality of stacked heterojunctions, the top surface of the epitaxial layer is provided with first grooves and second grooves which are arranged at intervals, the first grooves and the second grooves extend to the heterojunctions farthest away from the top surface of the epitaxial layer, and the cathode layer is located in the second grooves and electrically connected with the heterojunctions; at least one groove wall of the first groove is an inclined plane, and the anode layer is located in the first groove and at least located on the inclined plane. According to the embodiment of the invention, the voltage endurance capability of the power diode can be improved.

This invention provides a high-voltage enhancement-mode HEMT device that suppresses current collapse, comprising a substrate, a GaN layer, and an Al layer. x Ga 1‑x N layer, Al x Ga 1‑x From left to right, the N-layer consists of a source, a P-GaN gate, a P-GaN hole injection structure, and a drain. A high-resistivity capping layer covers the P-GaN gate, gate metal, P-GaN hole injection structure, the upper surface of the drain, and the Al layer between the P-GaN gate source side and the drain. x Ga 1‑x In the upper surface region of the N-layer, the hole injection structure in this invention can be sufficiently close to the gate, allowing for more complete surface trap recombination. Simultaneously, it avoids long-distance surface charge transport, resulting in faster surface charge transfer and improved surface trap recombination efficiency, achieving the optimal hole injection effect. This invention suppresses current collapse without shortening the device drift region, thus avoiding a decrease in device breakdown voltage.

This invention discloses a gallium oxide field-effect transistor and its fabrication method, relating to the field of gallium oxide device technology. The gallium oxide field-effect transistor includes, from bottom to top, a drain, a gallium oxide substrate, a gallium oxide epitaxial layer, a gallium oxide current blocking layer, and an n-type electrode. + Type-n highly doped gallium oxide layer; n + The surface of the highly doped gallium oxide layer has grooves, the bottom of which abuts into the gallium oxide epitaxial layer; it also includes: a gallium oxide gate dielectric layer located on the bottom wall and sidewalls of the grooves and n + On a portion of the surface of a highly doped gallium oxide layer; the gate, located on the surface of the gallium oxide gate dielectric layer; the source, located on the n-type... + On the surface of a highly doped gallium oxide layer, this invention effectively solves the problem of a large number of dangling bonds failing to form due to lattice mismatch between the silicon oxide or aluminum oxide gate dielectric layer and gallium oxide, reduces the interface state density between the gate dielectric layer and gallium oxide, and effectively improves characteristics such as gate leakage current and threshold voltage drift.

The invention belongs to the technical field of power semiconductors, and relates to a transverse enhancement type gallium oxide field effect transistor with a NiO extended gate field plate. When the device is in forward conduction, an electron accumulation layer is formed in the drift region below the extended gate field plate, so that the on-resistance of the device is reduced, and the defect that the specific on-resistance of an enhanced MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is large is overcome; in a blocking state, the extending gate structure and the N-type gallium oxide drift region form a super-junction-like structure, electric field distribution is modulated, depletion of the drift region is assisted, the breakdown voltage of the device is improved, the doping concentration of an epitaxial layer of the device is further improved, and the on-resistance is reduced. The invention has the beneficial effects that the device is an enhanced device and has the dual advantages of low on-resistance and high breakdown voltage, in addition, the applied nickel oxide deposition process is simple, an additional etching process is not introduced, and the manufacturing cost is reduced. And etching damage in the drift region of the device and advanced breakdown caused by an interface problem between gallium oxide and nickel oxide are avoided.