94results about How to "Reduce self-heating effect" patented technology

The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.

The invention provides a matrix multi-path temperature detection circuit for a small satellite platform, comprising a matrix thermistor measurement network, an analog switch, a main backup analog/digital (A/D) conversion module and a main backup singlechip controlling and processing module, wherein the matrix thermistor measurement network completes voltage value collection of the terhmistor of each temperature monitor point in a satellite system; the analog switch is matched with the matrix thermistor measurement network to select the voltage of a particular temperature monitor point transmitted to the A/D conversion module; the A/D conversion module is used for carrying out the filtration, amplification and A/D conversion on a collected temperature voltage; and the singlechip controlling and processing module is used for setting and outputting an inspection control signal of the matrix thermistor network and the analog switch, converting the voltage output by the A/D conversion module into a temperature value, and managing communication with a controller area network (CAN) bus. By utilizing the temperature detection circuit, elements and devices required for temperature measurement of the satellite platform are reduced, the self-heating effect of the thermistor is reduced, the backup design is added simultaneously, and the reliability is improved.

A MOS device having low floating charge and low self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

A semiconductor structure and a method for forming same are provided. One form of the method includes: providing a substrate including a device unit area, where at least two fins are formed on the substrate of the device unit area, a channel structure layer is formed on the fins, the channel structure layer includes a first channel structure layer located on at least one fin and a second channel structure layer located on at least one fin, the first channel structure layer includes multiple channel laminates, each channel laminate includes a first sacrificial layer and a first channel layer located on the first sacrificial layer, and the second channel structure layer is a second channel layer of a single-layer structure; forming a dummy gate structure across the channel structure layer of the device unit area; forming a source-drain doping layer in the channel structure layer on two sides of the dummy gate structure; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure; and after forming the interlayer dielectric layer, forming a gate structure at positions of the dummy gate structure and the first sacrificial layer. The present disclosure can improve overall performance of a device.

The invention relates to the SOI (silicon on insulator) technology. The invention solves the problem that the heating effect of the existing conventional SOI device is obvious, and provides a partial SOI traverse double-diffused device. The technical scheme of the invention is summarized as follows: one end of an oxide buried layer of the partial SOI traverse double-diffused device is arranged below a source electrode and is contacted with the edge of the device, the horizontal distance between the other end of the oxide buried layer and a drain type II impurity ohm contact area is not less than zero, a PN (phosphorus-nitrogen) junction is formed by the way that a type I impurity substrate is contacted with the silicon layer of the type II impurity top layer between the other end of the oxide buried layer and the edge of the device below the drain. The partial SOI traverse double-diffused device has the beneficial effects that the oxide buried layer is provided with an opening below the drain, the heat produced by an SOI device can be effectively transferred, and the partial SOI traverse double-diffused device is applicable to SOI devices.

The invention relates to a semiconductor device with a height-controllable fin and a preparation method. The preparation method comprises the following steps: providing a semiconductor substrate; forming a first semiconductor material layer, a second semiconductor material layer and a hard mask layer on the substrate; etching the hard mask layer, a second semiconductor material layer and a first semiconductor material layer to form a trench and a fin pattern; performing isotropic etching to remove a part of the first semiconductor material layer in the fin pattern to form a virtual fin with reduced critical size; depositing dielectric layers to fill the trench and cover the fin pattern; etching the dielectric layers till the second semiconductor material layer below, in order to expose the second semiconductor material layer to form the fin. The preparation process of the fin is easy to control, and the obtained device is more stable.

A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

The invention discloses a double-layer sectioned SOI LIGBT device. The double-layer sectioned SOI LIGBT device comprises a silicon substrate; a first buried oxide layer and an N buried layer are sequentially arranged on the silicon substrate from left to right; the upper surface of the N buried layer is higher than the upper surface of the first buried oxide layer; a P buried layer is arranged on the first buried oxide layer; a second buried oxide layer is arranged on the N buried layer; the upper surface of the P buried layer and the upper surface of the second buried oxide layer are at the same height; and an N type drift region is arranged on the P buried layer and the second buried oxide layer. The invention also discloses a manufacturing method of the double-layer sectioned SOI LIGBT device. According to the manufacturing method, the oxide layer of a conventional SOI LIGBT is divided into two layers, and layers are separated from each other through reverse PN junctions; and with a novel sectionally-isolated structure adopted, excellent substrate leakage current isolation of the device can be ensured, heat dissipation performance can be improved, operating temperature can be decreased, and breakdown voltage can be improved.

The invention provides a semiconductor device, which comprises a substrate, a second conductor layer, a third conductor layer, isolating structures, hollow cavities, oxide layers, oxidation barrier layers on the oxide layers, and a device structure, wherein the substrate comprises a first semiconductor material; the second conductor layer is located on the substrate; the third conductor layer is located on the second conductor layer; the isolating structure is located at two sides of the third semiconductor layer above the substrate; and the hollow cavities are located at the end parts of the second semiconductor layer and between the third semiconductor layer and the substrate; the oxide layers and the oxidation barrier layers thereon are located on the inner surfaces of the hollow cavities and on the side walls of the isolating structures; the device structure is located on the third semiconductor layer; and source-drain regions of the device structure are located above the hollow cavities. The device structure provided by the invention simultaneously has the advantages of a bulk-silicon device and an SOI device, and has the characteristics of low cost, small electricity leakage, low power consumption, high speed, relatively simple process and high integration level.

A method and apparatus are provided for calibrating digital thermal sensors. A processor chip with a plurality of digital thermal sensors receives an analog voltage. A test circuit coupled to the processor chip receives a clock signal and a register coupled to the test circuit outputs a value on each clock cycle to a digital thermal sensor in the plurality of digital thermal sensors. The digital thermal sensor transitions an output state in response to the value of the register received in the digital thermal sensor equaling a temperature threshold of the digital thermal sensor. The value of the register at the point of transition is used to calibrate the digital thermal sensor. An incrementer increments the value of the register on each clock cycle in response to the value of the register received in the digital thermal sensor failing to equal the temperature threshold of the digital thermal sensor.

A method of producing a silicon-on-insulator article is provided. The method includes: forming a first aluminium nitride layer thermally coupled to a first silicon substrate; forming a second aluminium nitride layer thermally coupled to a second substrate, the second substrate including at least a surface layer of silicon; bonding the first and second aluminium nitride layers of the first and second substrates together so that the first and second aluminium nitride layers are disposed between the first and second substrates; and removing most of the second substrate to leave a layer of silicon that is electrically insulated from but thermally coupled to the first silicon substrate by the first and second aluminium nitride layers.

A transistor structure disposed on a substrate includes a gate electrode, a gate insulating layer overlapping the gate electrode, a channel layer overlapping the gate electrode, and a plurality of first electrodes and a plurality of second electrodes overlapping the gate electrode. The gate insulating layer is disposed between the channel layer and the gate electrode. Besides, the gate insulating layer is located among the first electrodes, the second electrodes, and the gate electrode. The first electrodes and the second electrodes are alternately arranged along a first direction. Each of the first electrodes has a first width along the first direction. Each of the second electrodes has a second width along the first direction. A ratio of the first width to the second width ranges from 2 to 20. A driving circuit structure having the transistor structure is also provided.

The invention discloses a preparation method of a high-performance gallium oxide field effect transistor with an insulating substrate, and mainly solves the problems that the cost of growing a Ga2O3 thin film by an existing epitaxial method is high, and lattice mismatch and thermal mismatch between the substrate and the thin film are difficult to eliminate. The method comprises the steps of selecting an n-type beta-Ga2O3 single crystal substrate, cleaning the n-type beta-Ga2O3 single crystal substrate, and obtaining a nano-scale beta-Ga2O3 thin film through multiple times of mechanical stripping; soaking the insulating substrate in acetone to remove organic pollutants and the like, transferring the nano-scale beta-Ga2O3 thin film to the insulating substrate, and sequentially performing photoetching and metal layer deposition on the thin film to form a source end electrode and a drain end electrode; and depositing Al2O3 on the surface of a sample piece with the manufactured source and drain electrodes, sequentially carrying out photoetching and metal layer deposition on the surface of Al2O3 to form a gate electrode, and completing manufacturing of the gallium oxide-based device. Thepreparation method is simple in preparation process and low in cost, and the prepared Ga2O3 film is high in quality and can be used for preparing a high-performance gallium oxide-based device.

The invention provides a reticle and a forming method of a semiconductor device. The reticle comprises a substrate, a shade layer placed on the substrate and a main pattern placed in the shade layer and further comprises an auxiliary pattern placed in the shade layer, wherein the auxiliary pattern is placed inside the main pattern or at the periphery of the main pattern and is used for increasing the light transmittance of the reticle. The reticle has the advantages that the light transmittance of the reticle is increased due to arrangement of the auxiliary pattern; since the area of the reticle, receiving irradiation of exposure light, is reduced, absorbed light is reduced, the self-heating effect of the reticle is decreased, the self deformation of the reticle is reduced, further the deflection of a device pattern formed by using the reticle can be prevented, and the pattern accuracy of a semiconductor device formed by using the reticle can be improved.

The invention provides an SOI device capable of improving a self-heating effect and a preparation method thereof. The preparation comprises the steps: providing a semiconductor substrate with a cavitystructure, enabling the cavity structure to be located in a top semiconductor layer and exposing an insulating layer, preparing an active region coating the cavity structure, and preparing a gate electrode structure, a source-drain region and a source-drain electrode. The SOI substrate with the nanoscale cavity is adopted, the cavity structure is located in the top semiconductor layer, the size of the cavity is effectively reduced, the cavity is in the nanoscale size in the channel length direction, the heat dissipation path of the device cannot be obviously blocked, and compared with a device with a large-size cavity, the self-heating effect is relieved. Theoretically, the thickness of the top semiconductor layer above the cavity can reach 2 nm, it is guaranteed that top silicon is not damaged, a channel can be completely exhausted by a gate electrode, and the floating body effect is effectively restrained. The cavity is located in the top semiconductor layer and makes contact with the insulating layer, parasitic charges in the insulating layer cannot be introduced into a parasitic channel at the bottom of the top semiconductor layer, and the total dose radiation effect is effectively restrained.