Silicon-on-insulator (SOI) substrate structure and device

Abstract

The invention provides a silicon-on-insulator (SOI) substrate structure and an SOI device using the SOI substrate structure, for further reducing the self-heating effect of the SOI device and avoiding the problems of substantially reduced SOI device performance, many process modifications and high cost and the like in the existing scheme of reducing the self-heating effect; meanwhile, by the adoption of the invention, current at a drain terminal can be increased, the off-state leakage current of the device can be reduced and the ratio of on-state current to off-state current can be obviously improved. The SOI substrate structure provided by the invention comprises an insulating layer and a bottom substrate below the insulating layer, wherein the insulating layer is divided into a first insulating layer below a channel region and a second insulating layer beyond the first insulating layer, and the thickness of the first insulating layer or a part of the first insulating layer is smaller than that of the second insulating layer.

Description

Technical field [0001] The present invention relates to the field of semiconductor manufacturing, in particular to a silicon on insulator (SOI, Silicon on Insulator) substrate structure and devices. Background technique [0002] With the advancement of technology, the development of integrated circuits to the ultra-large-scale nanoscale stage. The process of bulk silicon substrates and bulk silicon devices is approaching physical limits, and severe challenges are encountered in further reducing the feature size of integrated circuits. At present, the industry believes that SOI substrates and SOI devices are one of the best solutions to replace bulk silicon substrates and bulk silicon devices. [0003] SOI devices usually have a three-layer structure of "top device / insulating layer / bottom substrate". The full dielectric isolation between the top device and the bottom substrate is achieved through an insulating layer. The insulating layer is usually silicon dioxide, called buried Ox...

AI Technical Summary

Problems solved by technology

[0007] For the scheme of reducing the thickness of BOX 15, the isolation distance between D12 and S13 and the underlying silicon 16 will be reduced. Since the thickness of BOX 15 directly below D12 and S13 is extremely related to the performance of SOI devices, if the thickness is reduced, it will increase The capacitance in this area degrades the switching speed of SOI devices, thereby greatly reducing the performance of SOI devices, or failing to manufacture SOI devices that meet the conditions of use.

[0008] For the scheme of forming a window under the channel region 14 so that the channel region 14 is partially in contact with the underlying silicon 16 for heat dissipation, not only will there be defects or even a large number of defects in the transition region between the fracture of the BOX 15 and the underlying silicon 16 during the process of forming the window. defects, and because the channel region 14 is in contact with the underlying silicon 16, the parasitic capacitance will be increased, and the advantages brought by the isolation of the channel region 14 and the underlying silicon 16 by the BOX 15 will be greatly lost, resulting in a significant reduction in device speed and high power consumption, for example. issues such as increased

In addition, this solution will make many changes to the existing SOI process, and the implementation cost is high

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