33 results about "Soi ldmos" patented technology

The invention belongs to a field of semiconductor technology and specifically relates to an HK SOI LDMOS (Lateral Double-Diffusion Metal Oxide Semiconductor) device. The device has the following characteristics. First, the device has three separated grating structures including a plane grate and two channel grates. In an open state, the three-grating structure an form a plurality of crosswise and longitudinal channels, thus increasing channel density, increasing current and reducing specific on-resistance. Second, high K mediums are embedded into drifting zones adjacent to a semiconductor zone and are arranged in alternation with the drifting zones. In the open state, electron accumulation layers are formed on side walls of the drifting zones adjacent to the high K mediums, so that low resistance channels are provided and the specific on-resistance is reduced. In a closed state, the high K mediums assist to drain the drifting zones, so that the drifting zone doping is improved, the electric field is improved and the specific on-resistance is reduced and the voltage holding performance is improved further. Third, an SOI structure is adopted, so that longitudinal voltage holding performance is improved, leakage current is reduced and a latch-up effect is eliminated.

The invention provides a multi-gate SOI-LDMOS device structure which comprises an SOI substrate, an active region and a polysilicon gate. The SOI substrate comprises a silicon substrate body, an oxygen buried layer and a top silicon layer, the active region is formed in the top silicon layer and comprises a source region, a channel region, a drift region, a shallow doping drain region and a drain region, the source region, the channel region, the drift region, the shallow doping drain region and the drain region are sequentially connected, the polysilicon gate comprises a gate-oxide layer and a polysilicon layer, the gate-oxide layer is combined to the surface of the channel region, the polysilicon gate is separated by at least one dielectric layer into two short gate structures, and heavy doping regions inversed with the channel region in doping type are formed corresponding to the position, below the dielectric layer, in the channel region. The multi-gate SOI-LDMOS device structure has the advantages of being high in breakdown voltage, good in transconductance characteristic, small in positive break-over resistance, low in self-heating effect and the like. As the heavy doping regions inversed with the channel region in doping type are formed between short gates, when a device is irradiated, the heavy doping regions serve as recombination centers, the large number of recombination centers are provided for electron hole pairs generated by irradiation, and the whole radiation resisting performance of the device is accordingly improved.

The invention discloses an SOI power LDMOS device provided with a junction type field plate structure, and belongs to the technical field of power semiconductor devices. According to the JFP SOI LDMOS device, a PN junction is adopted as a field plate, and a high-K medium is used as a field plate medium. On one hand, a PN junction electric field of the junction type field plate modulates the electric field on the surface of the device to improve the electric field distribution of the device and enhance the pressure resistance of the device; on the other hand, in a reverse blocking state, the junction type field plate assists in exhausting a drift region of the device to enable the doping density of the drift region of the device to be increased substantially, so that on-resistance is lowered; the high-K medium is used as a field dielectric layer so that the on-resistance and static power consumption can be lowered more beneficially. Compared with a conventional metal field plate, the junction type field plate technology also effectively avoids the defect that an electric field peak exists at the tail end of the field plate; compared with a polycrystalline resistance field plate, the junction type field plate has a PN junction potential barrier so that a high leakage current can be avoided. In addition, the SOI power LDMOS device provided with the junction type field plate structure also has good compatibility with SOI CMOS circuits.

The invention discloses a silicon-on-insulator laterally diffused metal oxide semiconductor (SOI LDMOS) device containing a composite drift region. The device sequentially comprises a grid oxide layer, a top silicon layer, a buried oxide layer and a bottom silicon layer from top to bottom, wherein the top silicon layer contains the composite drift region; and the composite drift region contains a first drift region and a second drift region, wherein the first drift region is adjacent to a channel region and is encircled by the second drift region. By adopting the composite drift region in the device, the maximum electric field value of the drift region close to one end of the channel, and the breakdown voltage value is improved; and because the first drift region is thinner than the top silicon layer, the additional value of the on resistance caused by the first drift region is reduced, and the on conduction property is improved.

The invention relates to the field of radio frequency power devices, and discloses a radio frequency SOI LDMOS device with H-shaped gate. The device comprises bottom layer silicon, an embedding oxide layer, top layer silicon, a P region, an N region, an H-shaped gate oxide layer, an H-shaped polysilicon gate layer, an H-shaped gate poly-silicide layer, a gate electrode, a silicon nitride side wall, an N drift region, a drain region, a drain region silicide layer, a drain electrode, a source region, a body lead-out region, a source region silicide layer and a source electrode. The radio frequency LDMOS device is manufactured on an SOI substrate, and forms the body lead-out which is in short circuit with the source region by utilizing a heavily doped region in the same form as the P region; the source/body, a drain/body and the gate and the corresponding electrodes are interconnected by the silicide; and a plurality of gate bars are connected in parallel in the forked mode so as to improve the driving capability of the device. Simultaneously, the invention discloses a method for adjustment, back-gate injection, N region injection and N drift region injection, which is compatible with the CMOS process and a method for hiding the silicide in the N drift region, which is compatible with the CMOS process.

The invention relates to an integrated double longitudinal channel SOI LDMOS (silicon on insulator laterally double diffusion metal oxide semiconductor) device unit. Improvement on the device structure and electrical properties of the traditional product is restricted. In the invention, a hidden buried oxidation layer divides a semiconductor substrate into a semiconductor substrate and a lightly doped drift region, wherein the two sides of the lightly doped drift region are respectively provided with a buffer zone of the LDMOS and a first low resistance polycrystalline silicon gate, and a longitudinal gate oxidation layer is arranged between the first low resistance polycrystalline silicon gate and the lightly doped drift region. The top of the lightly doped drift region is provided with a well region and a slot oxygen region, the well region is internally provided with two source electrodes and an ohm contact region, and the slot oxygen region is internally embedded with a second polycrystalline silicon gate. The upper part of the device is provided with three field oxidation layers and a metal layer. In the invention, a shallow slot gate is added between the well region and the drift region, a longitudinal conducting channel is added, the transconductance and on state current of the device are improved, and the on state resistance and on state voltage drop of the device are reduced, thus the on state power consumption is reduced, the thermostability and resistance to voltage of the device are improved, and the reliability of the device is improved.

The invention discloses an SOI LDMOS (Silicon On Insulator Laterally Double-Diffused MOSFET) device with buried field plates, and relates to a semiconductor power device. The SOI LDMOS device comprises a P-type substrate, buried oxide layers, the buried field plates, top silicon, transverse polysilicon gate, a source electrode, a drain electrode, a metal electrode and a gate oxide layer. The SOI LDMOS device is provided with the source and drain buried oxide plates; due to the introduction of the drain buried oxide plate, a drift region in an N<+> drain region is shielded, so that a longitudinal voltage of the device is applied to the buried oxide layer in the drain buried field plate; due to the introduction of the source buried field plate, body exhaustion of the device is enhanced and transverse electric field distribution of the device is modulated, so that a breakdown voltage of the device is increased and on-resistance is reduced; and in addition, the buried field plates replace part of buried oxide layers and the heat conductivity of polysilicon is greater than that of silicon dioxide, so that a self-heating effect of the device can be effectively improved.

The invention discloses an SOI-LDMOS (silicon-on-insulator laterally diffused metal oxide semiconductor) high-tension power device with a triangular trench and aims to solve the problems that voltage of a drain of the prior SOI-LDMOS device is induced out of an electronic inversion layer from beneath a buried oxide layer, an equipotential line is prevented from penetrating the buried oxide layer, and early breakdown occurs to a silicon layer, and breakdown voltage withstanding is difficult to increase. The SOI-LDMOS high-tension power device is mainly characterized in that the triangular trench is etched in a buried oxide layer under a drift area; a buried oxide slope exists under the drift area and is capable of constraining positively charged holes, high-density positive charge is produced, and breakdown voltage withstanding of the device is greatly increased through the high-density positive charge; thickness of the drift area linearly increases from a source to a drain, according to the principle of RESURF (reduced surface field), a transverse electric field is uniformized owing to modulation, lateral voltage withstanding can be improved, and rejection ratio on resistance can be increased fast.

The invention relates to a method for making an integrated silicon on insulator (SOI) laterally diffused metal oxide semiconductor (LDMOS) device with double vertical channels. The SOI LDMOS device made by the traditional method does not have a double-vertical-channel structure and an excellent performance corresponding to the double-vertical-channel structure. In the method, a channel etching technology is adopted to realize a double-vertical-groove grid electrode structure and a stepped-groove drain electrode structure, pit doping is replaced by a reverse doping distributed ion implantationpit ohmic contact doping technology, and a grid electrode and a drain electrode are simultaneously doped when an n+ source area is doped. By adopting the traditional SOI complementary metal-oxide-semiconductor transistor (CMOS) very large scale integrated circuits (VLSI) process technology under the condition of slightly increasing the process complexity and the cost, the integrated power and the electric and thermal performance of the SOI LDMOS device can be obviously improved so as to be beneficial to saving of resources and energy sources and protection on the environment.

The invention discloses an SOI LDMOS device for improving a self-heating effect, which relates to the field of SOI devices, and adopts a P-type heavily doped silicon layer and an N-type lightly doped semiconductor layer which are stacked to replace a conventional buried oxide layer, so that the dielectric isolation effect of the buried oxide layer can also be realized; and the thermal conductivity of the silicon layer and the semiconductor layer is much higher than that of the conventional buried oxide layer, so that the self-heating effect can be improved on the basis that the SOI LDMOS device has the advantages of high speed and low power consumption.

A hybrid semiconductor device is presented in which one or more diode regions are integrated into a transistor region. In a preferred embodiment the transistor region is a continuous (self-terminating) SOI LDMOS device in which are integrated one or more diode portions. Within the diode portions, since there is only one PN junction, the mechanism for breakdown failure due to bipolar turn-on is nonexistent. The diode regions are formed such that they have a lower breakdown voltage than the transistor region, and thus any transient voltage (or current) induced breakdown is necessarily contained in the diode regions. In a preferred embodiment, the breakdown voltage of the diode portions is lowered by narrowing their field plate length relative to the transistor portion of the device. This allows the device to survive any such breakdown without being destroyed, resulting in a more rugged and more reliable device.