33 results about "Soi ldmos" patented technology

The invention discloses an SOI LDMOS (Silicon On Insulator Laterally Double-Diffused MOSFET) device with buried field plates, and relates to a semiconductor power device. The SOI LDMOS device comprises a P-type substrate, buried oxide layers, the buried field plates, top silicon, transverse polysilicon gate, a source electrode, a drain electrode, a metal electrode and a gate oxide layer. The SOI LDMOS device is provided with the source and drain buried oxide plates; due to the introduction of the drain buried oxide plate, a drift region in an N<+> drain region is shielded, so that a longitudinal voltage of the device is applied to the buried oxide layer in the drain buried field plate; due to the introduction of the source buried field plate, body exhaustion of the device is enhanced and transverse electric field distribution of the device is modulated, so that a breakdown voltage of the device is increased and on-resistance is reduced; and in addition, the buried field plates replace part of buried oxide layers and the heat conductivity of polysilicon is greater than that of silicon dioxide, so that a self-heating effect of the device can be effectively improved.

The invention relates to a technical method for preparing an SOI LDMOS device. The method comprises the following steps: (1), performing P-type trap injection in a top-layer silicon film; (2), applying an oxidation backflow technology on the top-layer silicon film; (3), using a photoetching technology; (4), employing the photoetching technology and a corrosion technology; (5), utilizing the oxidation backflow technology;(6), employing the corrosion technology; (7), performing N-type trap injection to form an N-type doped area; (8), performing the P-type trap injection to form a first P-type doped area; (9), performing the P-type trap injection to form a second P-type doped area; (10), performing P-type source-drain injection to form a P-type source area and a P-type drain area; (11), performing deposition to form an insulation medium layer; (12), carrying out photoetching corrosion; (13), performing deposition to form a metal layer; (14), and carrying out the photoetching corrosion. The technical method is compatible with a CMOS technical process, the technology is concise and controllable, voltage withstanding performance of the high-voltage SOI LDMOS device can be ensured, and at the same time, isolation between devices can also be ensured.

The invention discloses a local ultra-thin SOI LDMOS device which overcomes the short channel effect and increases the frequency, and belongs to the field of semiconductor devices. Including semiconductor substrate 1, channel region 2, drift region 3, source region 4, drain region 5, gate oxide 6, field oxygen 7, gate 8, channel substrate heavily doped region 9, BOX layer 18, sidewall 19. The source extension region 20, wherein the drift region 3 is a lateral variable doping structure, characterized in that a through groove is opened along the width direction of the drift region at one end of the BOX layer close to the drift region, and the BOX layer 18 is located at the side of the channel Directly below, or directly below the channel and part of the source region, or directly below the channel and the source region, to ensure the breakdown voltage while improving the frequency characteristics and drive capability of the device. The invention effectively suppresses the short-channel effect, and improves the frequency characteristic and driving ability while ensuring the breakdown voltage.

The invention relates to the field of a radio frequency power device, and discloses a radio frequency SOI LDMOS device with close body contact. The device comprises bottom layer silicon, an embedding oxidation layer, top layer silicon, a P<-> region an N<-> region, a gate oxidation layer, a polysilicon gate layer, a gate poly-silicide layer, a gate electrode, a silicon nitride side wall, an N<-> drift region, a drain region, a drain region silicide layer, a drain electrode, a source region, a body contact region, a body region, a source region silicide layer and a source electrode. The radio frequency LDMOS device is manufactured on an SOI substrate, and forms the close body contact which is in short circuit with the source region by utilizing a heavily doped region in the same form as the P<-> region; the source / body, a drain / body and the gate and the electrodes are interconnected by the silicide; a plurality of gate bars are connected in parallel in the forked mode so as to improve the driving capability of the device; a method for adjustment, back-gate injection, N<-> region injection and N<-> drift region injection, which is compatible with the CMOS process, is designed; and amethod for hiding the silicide in the N<-> drift region, which is compatible with the CMOS process, is designed.

The invention relates to the field of radio frequency power devices, and discloses a radio frequency SOI LDMOS device with H-shaped gate. The device comprises bottom layer silicon, an embedding oxide layer, top layer silicon, a P<-> region, an N<-> region, an H-shaped gate oxide layer, an H-shaped polysilicon gate layer, an H-shaped gate poly-silicide layer, a gate electrode, a silicon nitride side wall, an N<-> drift region, a drain region, a drain region silicide layer, a drain electrode, a source region, a body lead-out region, a source region silicide layer and a source electrode. The radio frequency LDMOS device is manufactured on an SOI substrate, and forms the body lead-out which is in short circuit with the source region by utilizing a heavily doped region in the same form as the P<-> region; the source / body, a drain / body and the gate and the corresponding electrodes are interconnected by the silicide; and a plurality of gate bars are connected in parallel in the forked mode so as to improve the driving capability of the device. Simultaneously, the invention discloses a method for adjustment, back-gate injection, N<-> region injection and N<-> drift region injection, whichis compatible with the CMOS process and a method for hiding the silicide in the N<-> drift region, which is compatible with the CMOS process.

A latch-up resisting N-type SOI (Silicon On Insulator) laterally diffused metal oxide semiconductor (LDMOS) comprises an N-type substrate, wherein a buried oxide is arranged on the N-type substrate; an N-type epilayer is arranged on the buried oxide; an N-type buffering well and a P-type body region are arranged in the N-type epilayer; an N-type drain region is arranged in the N-type buffering well; an N-type source region and a P-type body contact region are arranged in the P-type body region; a gate oxide and a field oxide are arranged on the surface of the N-type epilayer; a shallow P-type well region is arranged on the surfaces of both the N-type source region and the P-type body contact region; a polysilicon gate is arranged on the surface of the gate oxide; and a passivation layer is arranged on the surfaces of the field oxide, the P-type body contact region, the N-type source region, the polysilicon gate and the N-type drain region. The latch-up resisting N-type SOI-LDMOS is characterized in that a deep P-type well region sharing the same photoetching board together with the shallow P-type well region and formed by high-energy ion implantation is arranged right below the shallow P-type well region, and the deep P-type well region effectively reduces the conducting resistance of the body region and lowers the latch-up risk in the working process while improving the current capacity of devices.

The invention relates to a manufacturing method of an anti-ESD integration SOI LDMOS device unit. By using the SOI LDMOS device manufactured through using the prior art, system weight is heavy; cost is high and reliability is low. According to the invention, through using five-time oxidation and nine-time photoetching, the SOI LDMOS device unit which integrates an anti-ESD structure and a function is manufactured. By using the method of the invention, under the condition that chip area cost is increased slightly, the integrated power and radio frequency SOI LDMOS device possesses an excellent integrated anti-ESD self-protection function; anti-ESD self-protection performance of the SOI LDMOS device is significantly improved; sizes, weight and cost of various kinds of power electronics systems using the device are reduced; and system reliability is increased.

Disclosed is a high-reliability silicon-on-insulator (SOI) laterally diffused metal oxide semiconductor (LDMOS) power element, which comprises a buried layer with high concentration and a contact injection region, wherein the buried layer with high concentration and the contact injection region are injected in top layer silicon of the SOI LDMOS power element, and the buried layer is connected with the contact injection region; current carriers which are located near a SOI LDMOS gate in the SOI LDMOS power element can be extracted through the buried layer and educed through the contact injection region, and electric potentials which are near the SOI LDMOS gate can be controlled. According to the high-reliability SOI LDMOS power element, in the top layer silicon of the SOI LDMOS, the buried layer with high concentration is produced and educed through the contact injection region, the current carriers which are located near the SOI LDMOS gate in the SOI LDMOS power element can be extracted through the buried layer, the electric potentials which are near the gate can be controlled, so that damages or burning of LDMOS elements caused by the fact that parasitic transistors open due to noise current or colliding current, maintaining voltage of the LDMOS elements under static shock is raised simultaneously, electrical safety working areas of the LDMOS power elements are expanded, and reliability of the elements is strengthened.

The invention discloses an SOI power LDMOS device provided with a junction type field plate structure, and belongs to the technical field of power semiconductor devices. According to the JFP SOI LDMOS device, a PN junction is adopted as a field plate, and a high-K medium is used as a field plate medium. On one hand, a PN junction electric field of the junction type field plate modulates the electric field on the surface of the device to improve the electric field distribution of the device and enhance the pressure resistance of the device; on the other hand, in a reverse blocking state, the junction type field plate assists in exhausting a drift region of the device to enable the doping density of the drift region of the device to be increased substantially, so that on-resistance is lowered; the high-K medium is used as a field dielectric layer so that the on-resistance and static power consumption can be lowered more beneficially. Compared with a conventional metal field plate, the junction type field plate technology also effectively avoids the defect that an electric field peak exists at the tail end of the field plate; compared with a polycrystalline resistance field plate, the junction type field plate has a PN junction potential barrier so that a high leakage current can be avoided. In addition, the SOI power LDMOS device provided with the junction type field plate structure also has good compatibility with SOI CMOS circuits.

The invention provides a high voltage low power consumption SOI LDMOS transistor having strained silicon structure, which comprises a source region (9), a body region (8), a drain region (5), a super-junction structure middle n column (3), a super-junction structure middle p column (4), a source electrode (10), a drain electrode (12), a grid electrode (11) and an embedded dielectric layer (6), wherein the super-junction structure middle p column (4) is silicon material lattice-unmatched monocrystal material, which is a material capable of leading silicon to generate strain, like Ge or SiGe, and the super-junction structure middle n column (3) is n-type transverse tensile strain silicon which is parallel to the source electrode and the drain electrode and generated on the basis of the super-junction structure middle p column (4). According to the invention, the requirement of reducing drain-source on-resistance is taken into consideration on the premise of maintaining the pressure resistance of devices. The transistor according to the invention is compatible with conventional SOI LDMOS transistor technology, has quite strong practicability and is easier for meeting the application requirement of power electronic system.