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HK SOI LDMOSdevice having three-grating structure

A gate structure and device technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of large specific on-resistance and high power consumption, and achieve the effect of increasing channel density, eliminating latch-up effect, and increasing current

Active Publication Date: 2016-10-12
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The literature (Variation of lateral width technique in SoI high-voltage lateral double-diffused metal–oxide–semiconductor transistors using high-k dielectric, IEEE Electron Device Letter, vol.36, no.3, 2015) introduced variable width high K medium greatly improves the withstand voltage of the device, but the specific on-resistance of the device is still large and the power consumption is high.

Method used

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  • HK SOI LDMOSdevice having three-grating structure
  • HK SOI LDMOSdevice having three-grating structure
  • HK SOI LDMOSdevice having three-grating structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0027] Such as figure 1 As shown, the specific structure of this example includes a second conductivity type semiconductor substrate layer 1 and a dielectric buried layer 2 above it; the upper surface of the dielectric buried layer 2 has a first conductivity type semiconductor drift region 5, and the upper layer of the drift region 5 There is a second conductivity type semiconductor body region 4 on one side, and a high-K dielectric 6 is embedded in the drift region 5 close to the semiconductor body region 4. The high-K dielectric 6 and the drift region 5 are alternately arranged in the longitudinal direction. It is a material with a dielectric constant greater than 3.9; a first trench gate structure extending to the buried dielectric layer 2 is formed through the side of the semiconductor body region 4 away from the drift region 5. The first trench gate structure includes a first trench gate structure. The trench gate dielectric 3 and the first conductive material 8 surrounded...

Embodiment 2

[0030] Such as image 3 As shown, compared with Embodiment 1, the first trench gate structure is segmented in the longitudinal direction, and the upper layer of the semiconductor body region 4 between every two first trench gate structures has the second conductivity type. A heavily doped semiconductor body contact region 9; on the side of the upper layer of the semiconductor body region 4 that is in contact with the first trench gate, there is a heavily doped semiconductor source region 72 of the first conductivity type, and the source structure includes a heavily doped semiconductor source region 72 of the first conductivity type. The doped semiconductor source region 72 and the heavily doped semiconductor body contact region 9 of the second conductivity type.

[0031] Compared with the embodiment 1, the first conductive type heavily doped semiconductor source region and the second conductive type heavily doped semiconductor body contact region can be formed by the entire ion im...

Embodiment 3

[0033] Such as Figure 4 As shown, compared with embodiment 1, the first trench gate structure is continuous in the longitudinal direction; the upper layer of the semiconductor body region 4 between the first trench gate and the planar gate is of the first conductivity type The heavily doped semiconductor source region 72, the upper layer of the semiconductor body region 4 between the first trench gate and the second trench gate is the second conductivity type heavily doped semiconductor body contact region 9, and the source structure includes a first A heavily doped semiconductor source region 72 of one conductivity type and a heavily doped semiconductor body contact region 9 of a second conductivity type.

[0034] Compared with the first embodiment, the first trench gate structure is continuous in this embodiment, and it can be used as a dielectric isolation layer in the low and high voltage region of the integrated circuit, which facilitates the isolation of high and low voltag...

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PUM

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Abstract

The invention belongs to a field of semiconductor technology and specifically relates to an HK SOI LDMOS (Lateral Double-Diffusion Metal Oxide Semiconductor) device. The device has the following characteristics. First, the device has three separated grating structures including a plane grate and two channel grates. In an open state, the three-grating structure an form a plurality of crosswise and longitudinal channels, thus increasing channel density, increasing current and reducing specific on-resistance. Second, high K mediums are embedded into drifting zones adjacent to a semiconductor zone and are arranged in alternation with the drifting zones. In the open state, electron accumulation layers are formed on side walls of the drifting zones adjacent to the high K mediums, so that low resistance channels are provided and the specific on-resistance is reduced. In a closed state, the high K mediums assist to drain the drifting zones, so that the drifting zone doping is improved, the electric field is improved and the specific on-resistance is reduced and the voltage holding performance is improved further. Third, an SOI structure is adopted, so that longitudinal voltage holding performance is improved, leakage current is reduced and a latch-up effect is eliminated.

Description

Technical field [0001] The invention belongs to the field of semiconductor technology, and specifically relates to an HK SOI LDMOS device with a three-gate structure. Background technique [0002] LDMOS (Lateral Double-diffusion Metal Oxide Semiconductor, lateral double-diffusion metal-oxide-semiconductor field) is a multi-sub-conductivity device with high input impedance, fast switching speed, and easy integration. It is used in smart power integrated circuits. widely used. For LDMOS, high withstand voltage (BV) means longer drift region length and lower drift region doping, which also leads to the specific on-resistance (R on,sp ) Greatly increases, therefore, the silicon limit problem (R on,sp ∝BV 2.5 ) Severely restrict the development of LDMOS devices. [0003] For low withstand voltage (BV <200V) devices, the channel resistance has become an important factor of the conduction power consumption, so how to reduce the channel resistance of the device has become a research to...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/10H01L29/423H01L29/78
CPCH01L29/0684H01L29/1037H01L29/4236H01L29/7824H01L29/7825H01L29/7831
Inventor 罗小蓉吕孟山尹超魏杰谭桥周坤葛薇薇何清源
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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