The invention relates to a switch-on accelerated
current mirror with a MOS reference
transistor (T1), the first terminal of which is connected to a reference potential (GND) and the control terminal of which is connected to the reference
voltage line (V ref ) and whose second terminal is connected to a reference
voltage line (V ref ). The MOS reference
transistor (T1) conducts an input current (I in ) against the reference potential (GND). The turn-on accelerated
current mirror comprises a
current source transistor (T2), the first terminal of which is connected to the reference potential (GND) and the control terminal of which is connected to the reference
voltage line (V ref ) and which has an output current (I out ) to the reference potential (GND), which is proportional to the input current (I in). The turn-on accelerated
current mirror comprises a second
current source transistor (T3), the first terminal of which is connected to the reference potential (GND) and the control terminal of which
current source transistor (T3) is connected to the reference voltage line (V ref ) and whose second current source transistor (T3) supplies an output current (I ist ) to the reference potential (GND), which is proportional to the input current (I in ). The switch-on accelerated current mirror also has a current
comparator (Icmp) that determines the value of the output current (I ist ) with the value of a
reference current (I ref ), and a first switch (T4) which, when closed, provides a positive supply voltage line (V bat ) with the reference voltage line (V ref) electrically connects or disconnects them. The first switch (T4) is closed when the current
comparator (Icmp) detects a value of the output current (I ist ) which is smaller than the current value of the
reference current (I ref ) multiplied by a first positive numerical value greater than zero, and opened when the current
comparator (Icmp) detects a value of the output current (I ist ) which is greater than the current value of the
reference current (I ref ) multiplied by a second positive numerical value greater than zero, where the first positive numerical value can be equal to the second positive numerical value.