20 results about "Sample and hold" patented technology

The present application relates to aerospace, geological exploration and micro-light detection fields, and particularly relates to a reconfigurable noise shaping successive approximation register analog-to-digital converter, which comprises a sampling unit, a capacitive digital-to-analog converter array, a comparison unit, a passive noise shaping feedback unit, a successive approximation control unit, an output unit and a mode control unit. The sampling unit samples and holds an input signal, and the capacitive digital-to-analog converter array outputs to the comparison unit. The comparison unit compares its output with a common-mode reference voltage, and the result is sent to the successive approximation control unit. In the noise shaping mode, the successive approximation control unit additionally generates an integral clock timing to activate the passive feedback unit, samples a residual voltage and feeds back to the digital-to-analog converter array. The output unit drives the conversion result to a lower circuit. The present application also contains a method. The present application can effectively suppress the capacitive parasitic effect and low-frequency noise, realize flexible switching between high-speed conventional mode and high-resolution noise shaping mode, and significantly improve the system performance.

A sample and hold circuit includes a pixel level connection coupled to a pixel cell. In a voltage domain global shutter operation, a reset voltage and a signal voltage are sampled and stored in a reset capacitor and a signal capacitor sequentially. In readout, the stored signal voltage is read out first to a comparing circuit to determine the best gain factor for the analog to digital converter (ADC) circuit to fully utilize the conversion range of the ADC to achieve a better signal to noise ratio. Once the better gain is determined and set for the ADC by comparing the signal voltage with a pre-determined threshold voltage, the same signal voltage is converted directly to become a digital signal value by the ADC. Then, the stored reset voltage is converted to a digital reset value by the ADC without changing the gain factor, to shorten the readout time.

The present invention inhibits interference of time-interleaved AD converters.　An AD conversion circuit (TD1) is provided with a plurality of time-interleaved AD converters (AD1 to AD4) and a plurality of sample-and-hold circuits (SH1 to SH4; SW1, SC1, GW1, . . . , SW4, SC4, and GW4) that sample and hold an analog input (AI) and a reference potential (VS) of each of the plurality of AD converters (AD1 to AD4).

An adaptive following capacitive sensor chip circuit, comprising: a CDAC circuit connected to an external load capacitor, a sample and hold circuit and a digital logic circuit respectively, for tracking the external load capacitor to keep consistent with the size of the external load capacitor; a RDAC circuit connected to the digital logic circuit and a comparator circuit group respectively, for generating a reference value that can be automatically adjusted to adapt to different degrees of external triggering action; an input end of the sample and hold circuit is connected between the external load capacitor and the CDAC circuit, and an output end is connected to the comparator circuit group, for controlling the acquisition of the external load capacitor size according to the signal sent by the digital logic circuit to the CDAC circuit, and outputting it to the comparator circuit group for comparison and judgment; the digital logic circuit is connected to the comparator circuit group and the sample and hold circuit, for providing the sample and hold circuit with a control timing signal, and providing the CDAC circuit and the RDAC circuit with an excitation voltage signal according to the output result of the comparator circuit group.

The control circuit and the switching circuit based on the slope of the upper power tube and the delay detection are provided, the current detection module outputs a first voltage and a second voltage; the slope detection module determines a third voltage corresponding to the slope of the change amount of the conduction current of the upper power tube according to the first voltage and the second voltage; the sample and hold module samples the third voltage and outputs a fourth voltage during the conduction of the upper power tube, and holds the third voltage at the time before the opening during the conduction of the lower power tube; the overcurrent detection module outputs a first control signal according to the first voltage and a preset threshold voltage; the delay correction module determines an off delay time according to the first control signal output by the overcurrent detection module, determines a correction voltage according to the off delay time and the fourth voltage, corrects the preset threshold voltage input to the overcurrent detection module according to the correction voltage, and resets the correction voltage after the correction of the preset threshold voltage of the overcurrent detection module is completed.

Described herein are systems and methods related to a device including an analog-to-digital converter (DAC) configured to convert a digital signal into an analog signal. The systems and methods can receive an analog signal at a first input, and provide the analog signal to a first output in response to a first clock signal. The first clock signal has a level at least partially dependent on the analog signal. The systems and methods can provide a path to a ground node for the first clock signal in response to a second clock signal. The second clock signal is independent of the analog signal.

The application discloses an integrated control module, an IO interface circuit and a controller, wherein the integrated control module is configured to build a closed-loop control system in an analog domain, convert an electrical signal input by an IO interface into an analog input waveform by using a waveform encoder, synthesize the analog input waveform into a periodic time-division multiplexing analog input signal wave by using an input waveform multiplexer driven by a time sequence controller, generate an isomorphic analog setting signal wave by setting a waveform generator, directly analog subtract two waveforms by using a differential amplifier to obtain an analog differential signal wave, separate the analog differential signal wave into independent pulse error signals of each channel by using a synchronous demodulation and distribution unit in combination with a sample and hold circuit, and finally generate a driving signal by an analog PID controller. The application solves the problems of the synchronism and the integration of multi-loop control by using a unique analog domain time-division multiplexing and demodulation architecture, and provides a new hardware solution for high-performance real-time control.

A sample and hold circuit includes a pixel level connection coupled to a pixel cell. In a voltage domain global shutter operation, a reset voltage and a signal voltage are sampled and stored in a reset capacitor and a signal capacitor sequentially. In readout, the stored signal voltage is read out first to a comparing circuit to determine the best gain factor for the analog to digital converter (ADC) circuit to fully utilize the conversion range of the ADC to achieve a better signal to noise ratio. Once the better gain is determined and set for the ADC by comparing the signal voltage with a pre-determined threshold voltage, the same signal voltage is converted directly to become a digital signal value by the ADC. Then, the stored reset voltage is converted to a digital reset value by the ADC without changing the gain factor, to shorten the readout time.

Systems, devices, and methods relating to analog-to-digital converters (ADCs) having a split digital-to-analog converters (DAC) are described. The ADC may include sample and hold circuitry having multiple sample and hold branches, with each branch coupled to a separate DAC. The total capacitor area for all of the separate DACs in the ADC may sum to the total capacitor area required in a non-branched ADC configuration. Exemplary ADCs may enable analog correlated multi-sampling to reduce noise or otherwise improve signal-to-noise ratio. The ADC may include a configurable gain factor and a configurable number of correlated multi-sampling reads. Exemplary embodiments include an image sensor having a pixel output coupled with a readout circuitry, wherein the readout circuitry includes an ADC having a split-DAC architecture, enabling lower read noise and higher framerates with lower power usage.

The present invention relates to a gain adaptive readout circuit, a gain controller circuit and methods of operation thereof. A sample and hold circuit includes a pixel level connection coupled to a pixel cell. In a voltage domain global shutter operation, a reset voltage and a signal voltage are sequentially sampled and stored in a reset capacitor and a signal capacitor. At readout, the stored signal voltage is first read out to a comparison circuit to determine an optimal gain factor for an analog to digital converter circuit to fully utilize the conversion range of the analog to digital converter for better signal to noise ratio. Once the better gain for the analog to digital converter is determined and set by comparing the signal voltage to a predetermined threshold voltage, the same signal voltage is directly converted by the analog to digital converter to become a digital signal value. The analog to digital converter then converts the stored reset voltage to a digital reset value without changing the gain factor, thereby shortening the readout time.

The present application relates to the technical field of optical communication, in particular to a test circuit and method for testing burst RSSI sampling and holding time; by adjusting the delay time of a reset signal relative to a trigger signal, the time for a chip to complete the sampling process can be measured, so as to determine whether the sampling and holding function of the chip is qualified, and a blank that many sampling and holding chips cannot test the specific sampling completion time is filled. In the chip mass production test or in the chip verification test, whether the sampling and holding circuit function is qualified can be tested more conveniently.

A control circuit, for controlling a switching converter having a primary switch, an energy storage component and a plurality of rectifiers, the control circuit having: a sample and hold circuit, configured to sample and hold a power source winding voltage provided by a power source winding of the energy storage component during when any one of the plurality of rectifiers is on, and to provide a sample&hold voltage based thereon; and a feedback circuit, configured to receive the sample&hold voltage and a power supply voltage of the control circuit, and to provide a feedback voltage based thereon; wherein the primary switch is controlled to be on and off based on the feedback voltage.

The fixed-frequency peak current mode control slope compensation circuit and the switching circuit provided by the embodiments of the present disclosure, the current detection module collects the switching node voltage, and outputs a first voltage according to the switching node voltage and the input node voltage during the conduction of the upper power tube, and outputs a second voltage according to the switching node voltage and the ground node voltage during the conduction of the lower power tube; the slope detection module determines a third voltage corresponding to the slope of the change amount of the conduction current of the lower power tube according to the first voltage and the second voltage; the sample and hold module samples the third voltage during the conduction of the lower power tube, holds and outputs a fourth voltage of the third voltage at the time before the conduction of the upper power tube during the conduction of the upper power tube; the slope compensation module generates a slope compensation voltage corresponding to the fourth voltage according to the fourth voltage, and generates a ripple voltage according to the slope compensation voltage and the first voltage; and the duty cycle modulation module generates a duty cycle signal according to the ripple voltage and an error voltage.

An analog signal processing circuit can include a front-stage processing module configured to process an analog signal to generate a first differential signal; at least one switched capacitor circuit, coupled with the front-stage processing module to receive the first differential signal, and configured to integrate or sample and hold the first differential signal to generate a second differential signal; and where the front-stage processing module and the at least one switched capacitor circuit receive synchronous control signals, the front-stage processing module chops the analog signal according to the control signals, and the at least one switched capacitor circuit is in different operating modes at a first phase and a second phase of an operation cycle of the control signals, in order to eliminate DC offset voltages of the front-stage processing module and the at least one switched capacitor circuit.

A metrology system includes: a light portion that outputs light; a branching portion; and a detector and processing portion. The branching portion branches the light as reference light along a reference optical path and as measurement light along a measurement optical path to be reflected by a workpiece that is to be measured. The detector and processing portion is configured to: receive combined light comprising the reference light and the measurement light; and convert the combined light into a combined light electrical signal. The detector and processing portion includes: an analog to digital converter; and a sample and hold portion. The sample and hold portion includes at least a first sample and hold circuit and a second sample and hold circuit, and is coupled to sample the combined light electrical signal (e.g., at respective first and second sample rates) and to provide outputs to the analog to digital converter.

A capacitive charge-coupling mode analog compute in-memory (CIM) bitcell array is configured to generate an analog output voltage corresponding to a multiply-accumulate (MAC) operation result using a multibit weight. The analog output voltage is inputted to a dual-mode activation module which is selectively operable either in a Deep Neural Network (DNN) mode and a Spiking Neural Network (SNN) mode. The activation module comprises a sample and hold (S&H) circuit, a comparator, a digital-to-analog converter (DAC) which can be reconfigured in accordance with the selected one of the DNN mode and the SNN mode.

The utility model discloses a kind of modularized half duplex 2FSK low error code communication circuit, it is related to communication circuit field, including modulation module, demodulation module and logic control module, wherein, logic control module is connected with modulation module and demodulation module, for control modulation module or demodulation module is in working condition;Demodulation module includes adaptively connected waveform conversion circuit, time voltage conversion circuit, sample and hold circuit, low pass filter and comparator, waveform conversion circuit is used to convert 2FSK signal into detection signal, time voltage conversion circuit generates voltage signal according to detection signal, sample and hold circuit is used to sample voltage signal under the control of detection signal, the voltage signal output to comparator and low pass filter by sample and hold circuit sampling, low pass filter is used to generate reference voltage signal after voltage signal filtering, comparator is used to compare voltage signal and reference voltage signal to generate demodulation signal.The circuit has low error rate and high reliability.

The application provides a single-ended SAR ADC circuit with lockable capacitor array and a working method thereof, which comprises a sample and hold circuit, a comparator, a SAR control logic module and a DAC capacitor array with a lock switch. Before starting the analog-digital conversion, it is necessary to determine whether the lock switch in the capacitor array needs to be closed. Therefore, the input signal is compared with a specific voltage first, and according to the comparison result, the off state of the lock switch is judged. If the lock switch is open, the single-ended SAR ADC carries out normal analog-digital conversion. If the lock switch is closed, the capacitor connected with the lock switch in the capacitor array of the single-ended SAR ADC will be locked and kept connected to GND. When the input signal is small, by closing the lock switch, the high-order capacitor is locked, the unnecessary switching of the capacitor array is reduced, and the power consumption of the capacitor array and the switch can be greatly saved at the cost of less hardware overhead.

A sensing circuit includes a sample and hold circuit configured to sample and hold a difference between a first input and a second input, based on a sensing voltage being a first input and an initial reference voltage being a second input, and an amplifying circuit configured to amplify and output an output of the sample and hold circuit, wherein the sample and hold circuit includes a first sampling capacitor configured to sample a voltage level of the sensing voltage, a second sampling capacitor configured to sample a voltage level of the initial reference voltage, and a first voltage switch circuit configured to set a voltage applied to one end of the first sampling capacitor and one end of the second sampling capacitor to a first level, which is the voltage level of the initial reference voltage.

The application discloses a switching converter and a light load control circuit thereof. The switching converter comprises a reference voltage generation module configured to generate a first reference voltage; a sample-and-hold module configured to sample and hold the first reference voltage to generate a second reference voltage; a pulse width modulator configured to compare an output voltage of the switching converter with the second reference voltage to generate a pulse width modulation signal; a zero-crossing detection module configured to compare an inductor current of the switching converter with a first threshold to provide a detection signal; and a mode switching module configured to receive the detection signal and control the switching converter to switch from an operation period to a sleep period when the detection signal indicates that the inductor current decreases to the first threshold. The sample-and-hold module is configured to sample the first reference voltage in the operation period and hold the first reference voltage in the sleep period to obtain the second reference voltage, so that the reference voltage generation module can be turned off in the sleep period.