139 results about "Sample and hold" patented technology

A time-of-flight pixel circuit includes a photodiode configured to generate charge in response to modulated light reflected from an object. First and second transfer transistors are coupled to the photodiode. The first transfer transistor transfers a first portion of charge from the photodiode in response to a first modulation signal and the second transfer transistor transfers a second portion of charge from the photodiode in response to a second modulation signal. The second modulation signal is an inverted first modulation signal. A first floating diffusion is coupled to the first transfer transistor to receive the first portion of charge in response to a first modulation signal. Each one of a first plurality of sample and hold transistors is coupled between a respective one of a first plurality of memory nodes and the first transfer transistor.

The invention provides a real-time electroencephalogram phase locking closed-loop stimulation method and system, and relates to the technical field of electroencephalogram signal processing. The method comprises the following steps: firstly, acquiring a cortex electrical activity signal and establishing a baseline statistic, then carrying out causal band-pass filtering on the signal, and carrying out sampling and holding substitution in a stimulation artifact window; setting an amplitude and a duration threshold based on the baseline, and performing phase judgment after conditions are met; estimating an average period through zero crossing and calculating an instantaneous phase; outputting a trigger instruction when the three-point crossing judgment is established; and outputting stimulation under the constraint of charge balance and a safety limit value, setting a minimum prohibition period and link abnormity suppression, and recording a hit rate and a response rate for quality evaluation. According to the method, through causal phase estimation, artifact isolation and a schedulable triggering mechanism, the high hit rate of non-stationary signal phase locking stimulation is achieved, and the safety and effectiveness of a stimulation system are ensured.

A system and method for measuring mutual inductance between adjacent first communication transmission line and second communication transmission line is disclosed. The system includes a mutual inductance measurement circuit that includes a coupling generator which biases the first communication transmission line with a current ramp signal; a sample and hold circuit which captures an induced voltage on the second communication transmission line using a switched capacitor storage element; a switched capacitor integrator configured to integrate the induced voltage onto an output voltage node; and a comparator configured to switch states once the switched capacitor integration has surpassed a reference trippoint.

Systems, devices, and methods are provided for pulsed strain gauge topologies. A weight sensor assembly may comprise one or more load cells for receiving excitation pulses during a first state period of a duty cycle, sample and hold (S / H) circuitry connected to the one or more load cells that holds analog measurement signals from the one or more load cells, first filtering circuitry connected to the S / H circuitry for processing the analog measurement signals and producing a DC level signal, an amplification system connected to the filtering circuitry, for amplifying the DC level signal, second filtering circuitry connected to the amplification system for filtering power line noise, and analog-to-digital (ADC) circuitry connected to the second filtering circuitry. Examples of load cells described herein include full-bride load cells (FBLCs) and half-bridge load cells (HBLCs).

A photoelectric conversion apparatus comprises a pixel region where pixels are arranged in a matrix, a sample hold circuit configured to sample and hold, as a first signal and a second signal, two different signals output from each of two pixels in the pixel region, and an analog-digital conversion circuit configured to perform analog-digital conversion of the second signals from the two pixels after performing analog-digital conversion of the first signals from the two pixels. A time interval between a period set to perform analog-digital conversion of the first signals from the two pixels and a period set to perform analog-digital conversion of the second signals from the two pixels is set longer than a time interval between periods set to perform analog-digital conversion of each of the first signals from the two pixels.

An equalizer circuit includes: an analog front end circuit configured to receive an analog input signal from a transmission line; an analog finite impulse response filter circuit including: a sample and hold circuit configured to sample an output of the analog front end circuit; and a weighting circuit configured to weight the output of the analog front end circuit to generate a feedforward signal; and a decision feedback equalizer circuit configured to receive an output of the analog front end circuit and the feedforward signal.

Techniques and apparatus for accurately measuring an open circuit voltage of a battery included in a battery-powered device are provided. One example apparatus generally includes a sample-and-hold circuit configured to sample a voltage of a battery before loading the battery and to hold the sampled voltage of the battery; an analog-to-digital converter (ADC) selectively coupled to an output of the sample-and-hold circuit and configured to digitize the held voltage of the battery; and a controller configured to enable the ADC for digitizing the held voltage of the battery after the sample-and-hold circuit samples the voltage of the battery.

The integrated circuit of the present invention switches a transistor that controls the inductor current based on the inductor current flowing through an inductor to which a rectified voltage from a rectifier circuit that rectifies an AC voltage is applied and an output voltage generated from the AC voltage, and includes: a sample-and-hold circuit that samples and holds a voltage corresponding to the rectified voltage at a prescribed timing; an output circuit that outputs a limit voltage indicating a limit value for limiting the inductor current based on the voltage held by the sample-and-hold circuit; and a first signal output circuit that outputs a first signal for turning off the transistor based on a voltage corresponding to the inductor current and the limit voltage when a current value of the inductor current is greater than the limit value.

The present application relates to aerospace, geological exploration and micro-light detection fields, and particularly relates to a reconfigurable noise shaping successive approximation register analog-to-digital converter, which comprises a sampling unit, a capacitive digital-to-analog converter array, a comparison unit, a passive noise shaping feedback unit, a successive approximation control unit, an output unit and a mode control unit. The sampling unit samples and holds an input signal, and the capacitive digital-to-analog converter array outputs to the comparison unit. The comparison unit compares its output with a common-mode reference voltage, and the result is sent to the successive approximation control unit. In the noise shaping mode, the successive approximation control unit additionally generates an integral clock timing to activate the passive feedback unit, samples a residual voltage and feeds back to the digital-to-analog converter array. The output unit drives the conversion result to a lower circuit. The present application also contains a method. The present application can effectively suppress the capacitive parasitic effect and low-frequency noise, realize flexible switching between high-speed conventional mode and high-resolution noise shaping mode, and significantly improve the system performance.

An electronic device may include a receiver coupled to an antenna over a transmission line. The receiver may include a set of sample and hold circuits coupled in parallel between the transmission line and at least one pulse modulator. The pulse modulator(s) may be coupled between the sample and hold circuits and at least one time-to-digital converter (TDC). Each sample and hold circuit may be clocked using a different respective phase of a clock signal. During signal reception, the antenna may receive a radio-frequency signal. The sample and hold circuits may convert the radio-frequency signal into analog signals using the different phases of the clock signal. The pulse modulator(s) may convert voltages of the analog signals into pulse widths in at least one analog pulse width modulation (PWM) signal. The TDC(s) may convert the analog PWM signal(s) into digital codes.

A sample and hold circuit includes a sampling circuit including a first amplifier configured to amplify an input voltage to generate an amplification voltage, the sampling circuit configured to perform a sampling operation of sampling the amplification voltage. The sample and hold circuit also includes a holding circuit configured to perform a holding operation of setting an output voltage to a voltage level of the input voltage, based on the sampling operation and an amplification operation of a second amplifier.

A power converter having a load transition detecting mechanism is provided. A comparator of the power converter compares an output voltage of the power converter or a divided voltage thereof with a reference voltage to output a comparison signal. A load transition detecting circuit of the power converter detects the comparison signal, and samples and holds some of a plurality of waveforms of the comparison signal. The load transition detecting circuit of the power converter calculates an average value of a plurality of parameters respectively of the sampled waveforms as a load steady state reference value. The load transition detecting circuit of the power converter compares the parameter of each of the plurality of waveforms of the comparison signal with the load steady state reference value to determine whether or not a load is in a steady state or in a transient state.

A system and method for measuring mutual inductance between adjacent first communication transmission line and second communication transmission line is disclosed. The system includes a mutual inductance measurement circuit that includes a coupling generator which biases the first communication transmission line with a current ramp signal; a sample and hold circuit which captures an induced voltage on the second communication transmission line using a switched capacitor storage element; a switched capacitor integrator configured to integrate the induced voltage onto an output voltage node; and a comparator configured to switch states once the switched capacitor integration has surpassed a reference trippoint.

The invention relates to a method and a device for controlling the commutation time for the control of a BLDC motor. In this case, a corrected voltage signal (U korrU ) is generated from the EMF at a motor terminal (U). A fourth integrator (Int 2U ) integrated in a commutation interval in which this motor connection (U) is not supplied with current by the control block (St), this corrected voltage signal (U korrU ) to an integrated sign signal (S 2U ). A first integrator (Int 1U ) integrates the corrected voltage signal (U korrU ) to a threshold signal (S 1U ). A comparator (CMP 2U ) compares the threshold signal (S 1U ) with a default value (V U) and forms a commutation signal (A1). Depending on the commutation signal (A1), the commutation time of an assigned output of a control block (St) connected to the assigned motor terminal (U, V, W) is changed. A second summer (SU 2U ) adds the default value (V U ) with the associated integrated sign signal (S 2U ) to the reload value (S 3U ). The reload values ​​(S 3U ) is stored in a sample and hold circuit (SaH U ) triggered with the edge of the commutation signal (A1) and stored as a default value (V U ) is used for the said comparator. The generation of the new default value (V U ) depends on the current memory value of the sample and hold circuit (SaH U ).

The invention provides a sample-and-hold circuit and a multiplication digital-to-analog converter employing the same. The sample hold circuit is provided with a first input end, a second input end, a first output end and a second output end, the first input end receives a first input signal, and the second input end receives a second input signal. The sample hold circuit includes an operational amplifier, first and second switched capacitor circuits, and a level shift circuit. The operational amplifier has first and second input nodes and first and second output nodes. The first switched capacitor circuit is coupled to the first input terminal, the first output terminal and the first input node. The second switched capacitor circuit is coupled to the second input terminal, the second output terminal and the second input node. The level shift circuit is configured to level shift a voltage of the first output node and a voltage of the second output node according to at least the first input signal and the second input signal.

A sample and hold circuit includes a pixel level connection coupled to a pixel cell. In a voltage domain global shutter operation, a reset voltage and a signal voltage are sampled and stored in a reset capacitor and a signal capacitor sequentially. In readout, the stored signal voltage is read out first to a comparing circuit to determine the best gain factor for the analog to digital converter (ADC) circuit to fully utilize the conversion range of the ADC to achieve a better signal to noise ratio. Once the better gain is determined and set for the ADC by comparing the signal voltage with a pre-determined threshold voltage, the same signal voltage is converted directly to become a digital signal value by the ADC. Then, the stored reset voltage is converted to a digital reset value by the ADC without changing the gain factor, to shorten the readout time.

Reduce the time required from the start of the sample to the completion of outputting the converted data. [Solution] The successive approximation AD conversion circuit (1) comprises a sample-and-hold circuit (2) configured to sample and hold an analog input signal, a D / A converter (3) configured to convert a digital signal into an analog voltage, a comparator (4) configured to compare the output of the sample-and-hold circuit with the output of the D / A converter, and a control circuit (5) configured to generate the digital signal based on the output of the comparator and supply it to the D / A converter, determine each bit of the digital output signal based on the output of the comparator, and output the digital output signal serially in order from the determined bits.

An image sensor comprises: a plurality of sample-and-hold circuits that sample and hold a plurality of signals input from a plurality of different pixels; a plurality of converters that convert the signals held in the plurality of sample-and-hold circuits to currents corresponding to potentials of the signals, respectively; a switch that connects / disconnects the plurality of converters; and a plurality of output circuits wherein, in a case where the switch connects the plurality of converters, the currents converted by the plurality of converters are added and output from one of the plurality of output circuits, and, in a case where the switch disconnects the plurality of converters, the currents converted by the plurality of converters are output from the plurality of output circuits, respectively.

The present invention discloses an OPA driving circuit based on a shared resistor chain DAC, belonging to the technical field of optical detection and measurement. It includes a resistor chain, a switch array control module, a sample and hold module, an output stage, and a phase modulation module. One end of the resistor chain is connected to the switch array control module, and the other end of the switch array control module is connected to the input end of the sample and hold module and the output stage. The output end of the sample and hold module and the output stage is connected to the phase modulation module, and the phase modulation module is used to control the deflection phase of the OPA antenna under the control of the driving voltage. By using a shared DAC architecture, the power consumption of the multi-channel OPA driving circuit is reduced, the circuit scale is reduced, hardware resources are saved, and the integratability of the OPA lidar system is improved.

The invention relates to the technical field of optical communication, in particular to a test circuit and method for testing burst RSSI (Received Signal Strength Indicator) sampling hold time. By adjusting the delay time of the reset signal relative to the trigger signal, the time for completing the sampling process of the chip can be measured, so that whether the sampling and holding function of the chip is qualified or not is judged, and the blank that the specific sampling completion time of a plurality of sampling and holding chips cannot be tested is filled. During a chip mass production test or a chip verification test, whether the function of the sampling hold circuit is qualified or not can be tested more conveniently.

The invention relates to a sample and hold circuit with low droop rate for a battery power supply system. The sample and hold circuit may include an operational amplifier including a first operational amplifier input, a second operational amplifier input, and an operational amplifier output. The sample and hold circuit may also include a first switch connected between the first operational amplifier input and a power supply node, a second switch connected between the second operational amplifier input and the power supply node, a first capacitor connected between the first operational amplifier input and a ground node, and a second capacitor connected between the second operational amplifier input and the ground node. A second capacitor connected to the second operational amplifier input, a third switch connected between the second capacitor and the sample input, and a fourth switch connected between the second capacitor and the operational amplifier output.

Provided is a touch signal detection apparatus configured to calibrate a quantization error of a touch signal including a first digital-to-analog converter (DAC) configured to provide a first calibration voltage, a first calibration amplifier configured to amplify and output a difference between a touch signal generated by detecting touch input and the first calibration voltage using gain greater than 1, a second DAC configured to provide a second calibration voltage, a second calibration amplifier configured to sample and hold a difference between output of the first calibration amplifier and the second calibration voltage, and an analog-to-digital converter (ADC) configured to convert output of the second calibration amplifier into a digital code, wherein bit resolutions of the first DAC and the second DAC are the same.

A sample and hold circuit may comprise an operational amplifier including a first op-amp input, a second op-amp input, and an op-amp output. The sample and hold circuit may also include a first switch connected between the first op-amp input and a supply node, a second switch connected between the second op-amp input and the supply node, a first capacitor connected between the first op-amp input and a ground node, a second capacitor connected to the second op-amp input, a third switch connected between the second capacitor and a sample input, and a fourth switch connected between the second capacitor and the op-amp output.

A system and method for a post-sampling selectable gain circuit in sample and hold (S / H) analog-to-digital converters (ADCs). The method includes scaling down or scaling up a reference voltage to generate a plurality of candidate voltages associated with a plurality of measurement accuracies of a sampler circuit, each candidate voltage of the plurality of candidate voltages is respectively associated with a respective measurement accuracy of the plurality of measurement accuracies. The method includes selecting, by a processing device and based on an input voltage for the sampler circuit, a particular candidate voltage from the plurality of candidate voltages that is associated with an optimal measurement accuracy of the plurality of measurement accuracies. The method includes generating a sampler voltage associated with the optimal measurement accuracy by operating the sampler circuit based on the particular candidate voltage or an additional voltage associated with the particular candidate voltage.

The present invention inhibits interference of time-interleaved AD converters.　An AD conversion circuit (TD1) is provided with a plurality of time-interleaved AD converters (AD1 to AD4) and a plurality of sample-and-hold circuits (SH1 to SH4; SW1, SC1, GW1, . . . , SW4, SC4, and GW4) that sample and hold an analog input (AI) and a reference potential (VS) of each of the plurality of AD converters (AD1 to AD4).

A circuit includes a current source, a first switch, a second switch, a sample and hold circuit, and an analog-to-digital converter (ADC). The current source has a current input coupled to an input terminal configured for resistor connection, a first current output, and a second current output. The first switch has a first terminal coupled to the first current output, and a second terminal. The second switch has a first terminal coupled to the second current output, and a second terminal. The sample and hold circuit has an input coupled to the second terminal of the first switch and the second terminal of the second switch, and an output. The ADC has an input coupled to the output of the sample and hold circuit.

A switch control circuit configured to control a first switch having a first terminal to which a first voltage is applied, and a second switch having a first terminal connected to a second terminal of the first switch and a second terminal to which a second voltage lower than the first voltage is applied. The switch control circuit includes: a first sampling / holding circuit configured to sample and hold a switch voltage generated at a connection node between the first switch and the second switch when the second switch is turned off; a first comparison circuit configured to compare the switch voltage sampled and held by the first sampling / holding circuit with a first constant voltage; and a first dead time adjustor configured to adjust a dead time when the switch voltage rises according to an output of the first comparison circuit.

The invention relates to a high-precision and low-holding-error sampling holding circuit, and belongs to the field of integrated circuits. The circuit comprises an input-stage operational amplifier, a logic voltage comparator, a logic enable control switch and an output-stage operational amplifier. The non-inverting input end of the input-stage operational amplifier receives an input signal, and the inverting input end of the input-stage operational amplifier receives a feedback signal. The two ends of the logic enabling control switch are connected with the output end of the input-stage operational amplifier and the non-inverting input end of the output-stage operational amplifier respectively. The output end of the output-stage operational amplifier is connected with the inverted input end and is connected with the inverted input end of the input-stage operational amplifier through a feedback resistor; the logic enable control switch is controlled to be turned on and turned off according to voltage signals input by the normal-phase input end and the inverted-phase input end of the logic voltage comparator; wherein the output-stage operational amplifier adopts a JFET tube as an input tube. According to the invention, the voltage drift of the sampling hold circuit during long-time working in the hold mode can be suppressed, and the hold error is reduced.

The invention relates to a positive feedback gain compensation circuit applied to a sample hold circuit, which comprises a first positive feedback compensation unit, a second positive feedback compensation unit, a first logic control unit and a first sub ADC unit, and is characterized in that the V1 end and the V2 end of the first positive feedback compensation unit are respectively connected with the positive ends of the differential input end and the differential output end of an operational amplifier; the V1 end and the V2 end of the second positive feedback compensation unit are respectively connected with the negative ends of the differential input end and the differential output end of the operational amplifier; an output signal of the first logic control unit is respectively accessed to the first positive feedback compensation unit and the second positive feedback compensation unit; and an output signal of the first sub-ADC unit is connected with an input end of the first logic control unit. According to the positive feedback gain compensation circuit applied to the sample hold circuit, the requirement for the gain of an operational amplifier in the sample hold circuit can be lowered, and meanwhile the problem that the open-loop gain of the operational amplifier introduces a nonlinear error along with the change of the output amplitude is solved.

A switched-capacitor circuit includes a sample and hold stage including an input coupled to a circuit input and including an output. The circuit includes an amplification stage including an input coupled to the output of the sample and hold stage and including an output. The circuit includes an output stage including an input coupled to the output of the amplification stage and an output coupled to the circuit output. The circuit includes a feedback stage including a first terminal coupled to the circuit output, a second terminal coupled to the input of the amplification stage and including a third terminal.