The invention discloses a foreground calibration circuit for an
input offset voltage of an SAR ADC
comparator. The foreground calibration circuit comprises a power supply input circuit, an input geminate
transistor circuit, a latch
comparator, an SAR successive approximation register and a Res DAC resistance
voltage division type digital-to-analog converter. The output end of the power input circuit is electrically connected with the power end of the input geminate
transistor circuit; an analog input
signal VIN and a reference
voltage signal VREF are input into the input end of the input geminate
transistor circuit, and the output end of the input geminate transistor circuit is electrically connected with two input ends of the latch
comparator; the two output ends of the latch comparator are electrically connected with the input end of the SAR successive approximation register, and the output end of the SAR successive approximation register is electrically connected with the input end of the Res DAC resistance
voltage division type digital-to-analog converter; the output end of the Res DAC resistance voltage division type digital-to-analog converter outputs a CALIP
signal and a CALIN signal to a grid
electrode of an adjusting tube in the input geminate transistor circuit, so that the adjusting tube generates compensation current to compensate the current difference of two input geminate transistors in the input geminate transistor circuit, and offset voltage is calibrated.