Dynamic comparator

Abstract

The invention provides a dynamic comparator. The dynamic comparator comprises a pre-amplification circuit, a dynamic latch circuit and an output-stage circuit which are connected in sequence, wherein the pre-amplification circuit comprises a first-stage amplification unit adopting an input detuning storage technology and a second-stage amplification unit adopting an output detuning storage technology; the dynamic latch circuit is used for amplifying the output signal of the pre-amplification circuit, and transforming the amplified signal into a digital logical output level; the output-stage circuit is used for outputting the digital logical output level at a latched phase, and outputting logic zero at a rest phase. The dynamic comparator provided by the invention adopts a detuning canceling technology and a structure isolating kickback noise in the pre-amplification circuit, thus effectively reducing the input detuning voltage, and greatly meeting the demands for design of high speed and high precision analog-digital convertors.

Description

technical field [0001] The invention relates to a comparator, in particular to a dynamic comparator. Background technique [0002] The comparator is an important constituent unit of the pipeline A / D (analog / digital) converter, and its performance has an important influence on the pipeline A / D converter. With the development of the pipeline A / D converter towards high speed and high precision, the requirements for its internal sub-circuits, especially the comparator, are getting higher and higher. In the MDAC (multiplicative digital-to-analog converter) of the pipeline A / D converter, multiple internal comparators need to convert the input analog voltage signal of this stage into the logic level required by the subsequent circuit, and then through the D / A (digital / A) The converter converts the logic level signal into an analog voltage signal, and finally performs a subtraction operation to obtain the residual difference. Usually the propagation delay of the comparator occupi...

AI Technical Summary

Problems solved by technology

[0004] There are at least the following problems in the prior art: the general preamplified latch comparator only pays attention to reducing the kickback noise of the latch, but does not pay attention to the offset of the preamplifier, which seriously affects the accuracy of the comparator and limits the CMOS comparison. Application of high-speed and high-precision analog-to-digital converters

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