113 results about "Converter design" patented technology

A monitoring system includes a host having a plurality of sensor inputs for connection to sensors. A converter is designed to receive input signals from the sensor input and to convert the input signals from the sensors into digital signals. A processing system is configured to receive the digital signals and to generate alarm signals in response to selected ones of the received digital signals. An internally integrated voice/data modem is in operative association with the processing system. A phone connector is placed in operative association with the voice/data modem, to act as a port for transmission of the alarms to an external telephone network. A network connector is in operative association with the processing system and is designed to receive data in the form of alarms from the processing system and to act as a port for transmission of the alarm data to data network. The alarms are deliverable over phone lines as voice alarms, pager alarms and fax alarms, and are deliverable over a public or private network as e-mail alarms, SNMP trap alarms, and web page alarms. Remote status inquiries may be made via voice call and two-way e-mail operations.

The present invention provides a simplified method of controlling power among the various sources and loads in a power system. Power generating sources are each connected to a common DC bus through a converter designed to optimize power flow to the DC bus. A DC storage device is connected to the common DC bus through a power regulator designed to maintain a constant voltage on the DC bus. Further, an inverter may be provided to convert the DC voltage to an AC voltage for a customer load or for connection to the utility grid. Each power conversion device is independently controlled to provide a modular and simplified power control system.

A method and apparatus are disclosed for single-inductor multiple-output switching converter design. With the proposed freewheel switching control, this converter operates in a pseudo-continuous conduction mode (PCCM) and is capable of handling large load currents with a much smaller current ripple and peak inductor current, while retaining low cross regulation. It can also work in discontinuous conduction mode (DCM) for high efficiency at light loads. This design can be applied to have single or multiple outputs and for different types of DC-DC conversions.

The invention provides an ultrahigh-speed comparator with low offset, and belongs to the technical field of composite signal integrated circuits. The comparator comprises a preamplification circuit, a dynamic latch circuit and an output latch circuit which hare connected in sequence, wherein, the preamplification circuit comprises a fully differential input structure with a positive resistor and a negative resistor serially connected as load and is used for amplifying difference value between input signals and reference signals; the dynamic latch circuit is equipped with a bistable structure which is connected from head to tail by an inverter, and used for amplifying the output signals of the preamplification circuit and establishing preceding stage output to digital logic output level; and the output latch circuit is composed of two cross-coupled NMOS transistors and PMOS common source amplification input, and used for outputting preceding stage output in a latch time, and keeping output result of the dynamic latch circuit at high impedance state in a reset stage so as to reduce input offset voltage of the comparator, increase speed of the comparator and well meet requirements of high-speed analog-to-digital converter design.

The invention provides a dynamic comparator. The dynamic comparator comprises a pre-amplification circuit, a dynamic latch circuit and an output-stage circuit which are connected in sequence, wherein the pre-amplification circuit comprises a first-stage amplification unit adopting an input detuning storage technology and a second-stage amplification unit adopting an output detuning storage technology; the dynamic latch circuit is used for amplifying the output signal of the pre-amplification circuit, and transforming the amplified signal into a digital logical output level; the output-stage circuit is used for outputting the digital logical output level at a latched phase, and outputting logic zero at a rest phase. The dynamic comparator provided by the invention adopts a detuning canceling technology and a structure isolating kickback noise in the pre-amplification circuit, thus effectively reducing the input detuning voltage, and greatly meeting the demands for design of high speed and high precision analog-digital convertors.

A power converter equipped with a plurality of semiconductor modules, a cooling device, a control circuit board, a smoothing capacitor, and a discharging resistor. The discharging resistor mounted on the control circuit board in parallel connection to the smoothing capacitor. The control circuit board has fabricated thereon a timing controller working to control timings of on/off operations of the semiconductor modules, a driver coupled to control terminals of the semiconductor modules to control voltage applied to the control terminals, and a power supply circuit working to transform a voltage input to the control circuit board into operating voltages for the timing controller and the driver. The driver is disposed between at least one of the timing controller and the power supply circuit and the discharging resistor, thereby protecting the timing controller and/or the power supply circuit mounted on the control circuit board from thermal energy radiating from the discharging resistor.

An information handling system having an energy saving power converter that comprises a main converter for supplying power to the information handling system when in active operation, and an auxiliary converter for supplying standby power to the information handling system when in a sleep or shutdown mode of operation. The main converter is designed to supply the maximum amount of power required by the information handling system, and the auxiliary converter is designed to supply only enough power to maintain the information handling system in the sleep or shutdown mode of operation. The main converter goes into a standby or shutdown condition when not supplying power to the information handling system. The auxiliary converter is designed to draw a minimum amount of energy, only enough to maintain the information handling system in the standby or shutdown mode of operation. A voltage or current sensing logic is used to determine when the main converter should be active and when it should be in standby. A capacitor in the power converter stores enough energy so that the information handling system does not experience transients when the main converter goes back and forth between the active and standby conditions. Power blocking diodes may be used to prevent reverse power flow between the main converter and the auxiliary converter. A plurality of converters may be used for minimum standby power and maximum power conversion efficiency.

An image-sensing element has an array of photodiodes or other photodetecting elements and performs sigma-delta analog-to-digital conversion on the outputs of the photodetecting elements. The sigma-delta analog-to-digital converters have components divided between pixel-level and row-level structures, with each row-level structure connected to its pixel-level structures to define a multiplexed-input-separated sigma-delta analog-to-digital converter. The converter can include an integrator or can rely on an integration effect of the photodetecting element. The feedback required for sigma-delta analog-to-digital conversion can involve digital-to-analog converters located at each row-level structure or at each pixel-level structure.

The invention discloses a dual-Sepic buck-boost output parallel combined inverter, which comprises two buck-boost Speic DC/DC circuits that are connected in parallel at the output side, and which can realize the buck-boost single-phase inversion and expand the buck-boost single-phase inversion in a three-phase system to realize the three-phase inversion output. The inverter has the basic function of realizing buck-boost inversion; when the direct-current voltage at the input side is lower or the change range is larger, the dual-Sepic buck-boost output parallel combined inverter still can realize the inversion function; two high-frequency switching tubes adopt a non-complementary work manner and do not work simultaneously, therefore, the bridge through problem is prevented; the circuit parameter designing principle can be designed according to the mature direct-current Sepic converter designing principle; the inductive current works under the continuous state and reduces the influence of the EMI (Electro-Magnetic interference). The invention is mainly applied to the field of renewable energy source or new energy source generation with lower direct-current voltage, faster change or larger fluctuation range, such as photovoltaic power generation, a small Wind turbine generator system, fuel cell generation, and the like.

A power converter utilizes a high frequency capacitor and a bulk capacitor coupled across the DC terminals to reduce high frequency effect and voltage overshoot, leading to space and cost savings in power converter design. Each capacitor may be physically coupled adjacent the gate driver board via clips, clamps, and/or fasteners.

A power converter design is disclosed with a novel approach to thermal management which enhances the performance and significantly reduces the cost of the converter compared to prior art power converters. The invention minimizes the heating of one power component by another within the power converter and therefore enables the power converter to work at higher power levels. Essentially, the power converter uses a heatsink having a high length to width ratio, a linear array of power components thermally coupled to the heatsink parallel to the long axis of the heatsink and a heat removal system which produces the highest cross sectional thermal flux perpendicular to said long axis. In addition, a number of ancillary thermal management techniques are used to significantly enhance the value of this basic approach. A specific circuit design for the power converter is not disclosed or discussed as the invention can be applied to any number of power converter electrical topologies. What is addressed is the specific thermal management of the three primary component groups found in any power converter; semiconductor devices, magnetic components and capacitors. The invention uses specific geometries and power component arrangements as well as strategic use of advanced thermal materials.

Techniques pertaining to multiple-input comparator and power converter designs are disclosed. According to one aspect, the present invention discloses a multiple-input comparator comprising a pair of differential transistors connected by a resister. The gate terminals of the transistor pair serve as the input terminals of the comparator for receiving external voltage for comparison. The terminal of the resistor serves as the current input terminal and is either connected to a current source or a current sink. A power inverter utilizing the multiple-input comparator is also disclosed. The power inverter comprises a power switch driven by a PMW signal, a voltage sampling circuit, an error amplifier and a multiple-input PWM comparator.

A bidirectional power converter circuit is controlled via a hysteresis loop such that the bidirectional power converter circuit can compensate for variations and even changes in transmit and receive coil locations without damaging components of the system. Because the bidirectional power converter is capable of both transmitting and receiving power (at different times), one circuit and board may be used as the main component in multiple wireless power converter designs. A first bidirectional power converter is employed in a sealed battery unit having no external electrical contacts. A second bidirectional power converter is employed in a corresponding cart bidirectional power converter assembly. The battery unit and the cart bidirectional power converter assembly cooperate to wirelessly transmit power from the battery unit to a load of the cart bidirectional power converter assembly and from a power source to the battery unit via the cart bidirectional power converter assembly.

The formation of an assembled unit consisting of an annular capacitor [a wound, metallized dielectric capacitor in the shape of a closed path ring] with other power conversion components arranged and attached in manners uniquely allowed by the ring design will allow higher density converter designs [power/unit volume]. The resulting short connection paths between the capacitor element and the switching semiconductors also provide a very low inductance path that minimizes voltage spikes on the switching semiconductors as a result of turn-off di/dt. The capacitor serves as a short time current source and sink for the switching semiconductors. With the described configuration the RMS current seen by the capacitor can be made more volumetrically uniform enabling more uniform capacitor rise. The single capacitor configured as described also mitigates bus resonance problems often observed in prior art when multiple discrete capacitors are connected in parallel.

Designs and methods for devices that prevent accidental or inadvertent lateral removal of a guidewire from the guidewire entry tool of a rapid exchange catheter. A first device takes the form of a funnel sized and shaped to slide into the guidewire entry tool. Another illustrative device is shaped and adapted to slide into the guidewire exit slot of the guidewire entry tool, blocking the slot until the converter is removed. In further embodiments, guidewire entry tools include a guidewire exit slot allowing for selective movement of a guidewire laterally from within a catheter. The slot may be designed with structures adapted to prevent inadvertent lateral movement of a guidewire from within the slot. The slot may be formed in a zigzag shape or may include a number of protrusions. Alternatively, the guidewire entry tool may include a split ring that rotates from a first position to a second position, the first position allowing lateral removal of a guidewire and the second position preventing such removal.

The invention discloses a high-speed high-resolution digital acquisition device and a processing method of a controllable triggering period signal. The high-speed high-resolution digital acquisition device is characterized in that 1+N analogue-to-digital converters are arranged in the high-speed high-resolution digital acquisition device, and the input end of each analogue-to-digital converter is provided with a time delayer in a connecting manner, thus 1+N time delayers corresponding to the 1+N analogue-to-digital converters are arranged in the high-speed high-resolution digital acquisition device, wherein the output end of each analogue-to-digital converter is connected with the input end of a large programmable logic device. The invention has the advantages that: an AD (Analog-to-Digital) acquisition control and pre-processing unit consisting of an FPGA (Field Programmable Gate Array) and multiple paths of AD converters are utilized, thus the sampling time resolution of high-speed digital acquisition is largely increased, and the high-speed high-resolution digital acquisition processing method of the controllable triggering period signal, disclosed by the invention, has remarkable substantial characteristics and remarkable improvement compared with the prior art.

The invention relates to a DC/DC conversion circuit and a power supply device. The DC/DC conversion circuit comprises a push-pull conversion unit and a buck conversion unit being a buck conversion circuit. The push-pull conversion unit includes one or more parallel push-pull converters connected to a direct-current power supply; with open-loop control of soft switching, the push-pull converters works near a frequency of a resonance point and carry out outputting to the buck conversion circuit. The output voltage and/or current of the DC/DC conversion circuit are/is controlled by adjusting a drive signal of the buck circuit. At the front push-pull stage, the open-loop working mode of resonant soft switch series connection is employed and the output voltage and current of the whole converter are controlled by adjusting the back-stage buck conversion circuit, thereby improving the working frequency and efficiency of the converter and reducing the size and cost of the converter. Switching tubes and rectifier tubes work in a soft switch state, so that the voltage stress of the power tube is reduced and reliability of the converter design is improved.

The invention discloses a multifunctional energy storage converter design method based on a double deviation compensation control algorithm, and the method comprises specific steps: firstly, designinga multifunctional energy storage converter network topology, and then employing a current detection method based on a CSI filter, and obtaining a three-phase circuit P-according to a three-phase circuit P-; Obtaining a to-be-compensated local reactive power according to the Q theory; deriving an inner ring reference current; the reference current is used as the input of an inner ring controller;the inner loop controller outputs current to generate an IGBT driving signal under the action of a pulse width modulation link; therefore, the current output of the inverter is adjusted; and finally,an inner loop controller based on a double deviation compensation control algorithm is invented, and a self-adaptive controller based on multi-parameter decoupling identification is added into the double deviation compensation controller, so that the output current of the multifunctional energy storage converter can quickly and accurately track the inner loop reference current, and finally, the purpose of electric energy quality control is achieved.

The invention discloses a four order single loop local negative feedback Sigma-Delta modulator, belonging to the technical field of CMOS analog-to-digital converter (ADC) design. The modulator comprises a high-pass filter and a quantizer which are connected; the high-pass filter is used for filtering noise signals in input signals and determining signal transmission functions and noise transmission functions of the input signals; the quantizer is used for carrying out quantification treatment on the input signals filtered by the high-pass filter. By using the high-pass filter to determine the noise transmission functions and signal transmission functions of the Sigma-Delta modulator, the invention better restrains noises in a tape and is suitable for ADC design with low oversampling frequency and high precision; in addition, using Verilog-A hardware language to establish behavioural modeling, the invention can precisely simulates circuit function, in particular in simulation of mixed-signal circuits, thus greatly shortening simulation time and improving simulation efficiency.

A battery module and an arrangement including a number of battery modules connected in series are disclosed. An energy store has a positive and a negative connection. A boost converter has a first and a second converter output. The energy store is connected at the positive connection of the energy store to a first connection and at the negative connection of the energy store to a second connection. The first converter output is connected to a first compensation connection and the second converter output is connected to a second compensation connection. The converter is designed to draw energy from the energy store and to provide the energy to the converter outputs of the converter in the form of current.