183 results about "Low offset" patented technology

The invention provides an ultrahigh-speed comparator with low offset, and belongs to the technical field of composite signal integrated circuits. The comparator comprises a preamplification circuit, a dynamic latch circuit and an output latch circuit which hare connected in sequence, wherein, the preamplification circuit comprises a fully differential input structure with a positive resistor and a negative resistor serially connected as load and is used for amplifying difference value between input signals and reference signals; the dynamic latch circuit is equipped with a bistable structure which is connected from head to tail by an inverter, and used for amplifying the output signals of the preamplification circuit and establishing preceding stage output to digital logic output level; and the output latch circuit is composed of two cross-coupled NMOS transistors and PMOS common source amplification input, and used for outputting preceding stage output in a latch time, and keeping output result of the dynamic latch circuit at high impedance state in a reset stage so as to reduce input offset voltage of the comparator, increase speed of the comparator and well meet requirements of high-speed analog-to-digital converter design.

A respiratory device is provided with a display showing a respiration signal related to a breathing pattern of a patient. This signal is derived from the difference between a sensed signal indicative of the respiration and airflow generated by the device and a baseline signal. The parameter is adjusted so that the respiration signal is restricted to a predetermined dynamic range. A short term average of the respiration signal (taken over about 0.5 seconds) and a long term average of respiration signals (taken over about 12 seconds) are calculated based on the CPAP measure. These averages are used to monitor the dynamic change in the respiration signal. If a large variation in either average is detected, the baseline is set to a value selected to rapidly reduce the respiration signal to a lower offset.

A multi-stage, low-offset, fast-recovery, comparator system and method for: reducing the input offset voltage of the zeroing amplifier by a factor essentially equal to gain of the zeroing amplifier; reducing the input offset voltage of the combined main and zeroing amplifiers by a factor essentially equal to the product of the gains of the main and zeroing amplifiers; and amplifying the input signal to the amplification stage in accordance with the gain of the main amplifier to generate an amplified high-resolution signal.

A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect transistors (FETs) is coupled to a low-offset dynamic comparator and is respectively selected to provide a plurality of FET pairs. For each FET pair, a voltage offset to obtain a comparator output transition is identified and recorded. The recorded voltage offset for each FET pair is compared with a margin threshold value. Each FET pair having an identified voltage offset less than the margin threshold value is discarded or disabled for PUF response generation use.

In a communications system, data is multiplexed onto a transmission medium at a transmitter and demultiplexed from the transmission medium at a receiver. The clock applied to the transmitter and receiver is a multiplying delay-locked loop in which a delay line provides a multiplied clock which is applied back to its input. A delay adjustment circuit including a proportional phase comparator of low offset adjusts delay in the delay line.

The invention discloses a CMOS comparator with low power consumption, low offset voltage and low return noise, belonging to the technical field of the radio communication system. The CMOS comparator comprises a preposing amplifier, a pair of switch tubes, a positive feedback latch unit, a CMOS phase inverter and an SR latch unit, wherein the preposing amplifier adopts a PMOS tube to serve as the input differential pairs, a diode is connected with an NMOS tube and is connected with a circuit structure which is in positive feedback connection with the NMOS tube in parallel to serve as the load so as to reduce the offset voltage of the comparator; the pair of the switch tubes is inserted between the preposing amplifier and the positive feedback latch unit so as to reduce the return noise of the comparator; and the positive feedback latch unit adopts a cross-coupling CMOS inverter circuit structure, a reset pipe is connected between regenerating nodes, thereby not only reducing the power consumption but also increasing the regenerating speed. The comparator has good properties of low power consumption, low offset voltage and low return noise, does not need to adopt the offset canceling technique, and can be widely applied to a low power consumption high-speed AD converter with 6 to 8 medium and high accuracy of a radio communication system.

Circuits and methods to achieve a low-noise and low offset continuous sigma-delta modulator used e.g. for battery management are disclosed. Continuous integration of input is enabled by special switching principle of three parallel integrators. Precharging of integrator output in so called pre-run mode minimizes integrator leakage and non-ideal effects by connecting a Gm in pre-run mode either to input voltage or to a reference voltage depending this Gm is being used in a following clock period. Parasitic effects due to switching at first integration capacitor are minimized by using buffer amplifiers tracking the voltage on integration capacitors.

An amplifier circuit includes an pair of input transistors, the drains of which are connected to emitters of first and second cascode transistors. First and second controlled current sources are connected to the emitters of the first and second cascode transistors, respectively, and third and fourth controlled current sources are connected to the collectors thereof. A bias circuit controls the 4 controlled current sources in response to the emitter voltage of a pair of input transistors of an output stage the inputs of which are connected to the drains of the first and second cascode transistors.

The invention discloses a magnetic sensor device with low electric offset and high sensitivity, a method thereof, and a magnetic sensing system. The magnetic sensing system includes: a magnetic component proximate a movable mechanical component; and a magnetic sensor configured to determine a movement of the mechanical component based on a magnetic field produced by the magnetic component. The magnetic sensor includes: a low-offset magnetic sensing element; a high-sensitivity magnetic sensing element; and an offset compensation circuit configured to: determine a zero-crossing of a sensing field from an output of the low-offset magnetic sensing element; sample an offset value of the high-sensitivity magnetic sensing element at the zero-crossing; and subtract the offset value from an output of the high-sensitivity magnetic sensing element.

An operational amplifier with a first stage differential input circuit having low aspect ratio devices of size chosen to achieve a low offset voltage, and an output stage having high aspect ratio devices able to operate at higher frequencies than the input stage, provides an amplifier with low static offset and requiring only a small compensation circuit due to the wide separation of frequency response poles. Adding a third stage gives a high gain design that can be stabilized with nested miller compensation. Adding a second differential input circuit of the same type as the first, and a level shifter, provides rail-to-rail operation without disturbing the low offset properties.

An operational amplifier with two differential input stages is used to separately achieve low offset voltage and broad bandwidth characteristics. One input stage addresses dc and low frequency signals while the other addresses broadband frequencies. All transistors forming the dc stage are biased in the sub-threshold region. Following the two differential input stages, the signal paths are recombined in a capacitive cross-over network that provides outputs for subsequent amplification. The cross over frequency is adjustable from 15 kHz to 50 kHz using small practical values for the cross-over capacitor. The gain balance between the two input stages is adjustable by resistors and/or predetermined width/length ratios of the operational amplifier transistors.

An operational amplifier with two differential pairs coupled to different current sources. The gate terminals of the transistors in the first differential pair are used as input terminals providing common mode input for most of the rail-to-rail voltage. The bulk terminals of the transistors in the second differential pair are used as input terminals providing common mode input for the remainder of the rail-to-rail voltage to thereby accomplish full rail-to-rail common mode. By using the bulk terminals of the field effect transistors in the second differential pair, rather than the gate terminals, as the input terminal, the operational amplifier may be constructing in a single well, thereby being compatible with standard digital CMOS processes. Alternatively, the bulk-driven transistors may be replaced with gate-driven depletion type transistors. The high voltage transistors in the output stage further reduce the offset voltage of the operational amplifier.

The invention provides a low-offset band-gap reference voltage source. The voltage source comprises a reference voltage generation circuit and an offset voltage elimination circuit, wherein the reference voltage generation circuit receives a power supply voltage and generates a reference voltage; the offset voltage elimination circuit is used for eliminating the influence of the offset voltage ofan operational amplifier in the reference voltage generation circuit on the reference voltage, so that the reference voltage output by a band-gap reference voltage source is not influenced by temperature variation, offset voltage or other elements, and a reference voltage with higher accuracy and better stability can be acquired.

A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion. The single-ended output of the second stage may serve as the input into a latch, which may be a bistable set-reset (SR) latch configured to increase the gain and response time while protecting against multiple switching, with the single-ended output of the latch configured as the output of the comparator.

A hub assembly for a tilt rotor includes a yoke having a plurality of yoke arms located substantially orthogonal to a central axis of the hub assembly. An inboard pitch change bearing assembly substantially surrounds a yoke arm of the plurality of yoke arms. An outboard pitch change bearing assembly is located at the yoke arm. The inboard pitch change bearing assembly and the outboard pitch change bearing assembly are operably connectable with a rotor blade to allow pitch change of the rotor blade relative to the yoke about a pitch change axis.

Various embodiments provide a processing module that calibrates a current-mode baseline correction system to account for features in an input device that lead to “offset” in output of a charge integrator used for sensing presence of an input object. The offset is a difference between a common mode voltage, which is the average voltage output of the charge integrator over a sensing cycle and a mid-rail voltage midway between high and low power supply voltages. Calibration is performed by adjusting an N-side and/or P-side current flow duration parameter until common mode voltage falls within a low offset window in which the offset is deemed to be sufficiently close to the mid-rail voltage. The resulting duration parameters are stored and used for current-mode baseline corrections when operating an associated sensor electrode for capacitive sensing.

The invention discloses a low-offset full-motion comparator. Influences of offset voltage on a comparator are substantially reduced by adding a preamplifier circuit and an offset eliminating circuit to compensate the offset voltage at an input end of the comparator. Compared with conventional comparators with preamplifier circuits, the low-offset full-motion comparator has the advantages that a preamplifier of a full-motion structure is adopted without consuming static current so that power consumption is lowered.