304results about How to "Reduce parasitic effects" patented technology

A micro electro-mechanical (MEMS) device assembly is provided. The MEMS device assembly includes a first substrate that has a plurality of electronic devices, a plurality of first bonding regions, and a plurality of second bonding regions. The MEMS device assembly also includes a second substrate that is bonded to the first substrate at the plurality of first bonding regions. A third substrate having a recessed region and a plurality of standoff structures is disposed over the second substrate and bonded to the first substrate at the plurality of second bonding regions. The plurality of first bonding regions provide a conductive path between the first substrate and the second substrate and the plurality of the second bonding regions provide a conductive path between the first substrate and the third substrate.

An interconnect assembly including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact member are located in the plurality of through holes. The contact members include proximal ends that are accessible from the second surface, distal ends extending above the first surface, and intermediate portions engaged with an engagement region of the substrate located between the first surface and the recesses. Retention members are coupled with at least a portion of the proximal ends to retain the contact members in the through holes. The retention members can be made from a variety of materials with different levels of conductivity, ranging from highly conductive to non-conductive.

The present invention relates to MicroElectroMechanical Systems (MEMS), devices and applications thereof in which a proof mass is caused to levitate by electrostatic repulsion. Configurations of electrodes are described that result in self-stabilized floating of the proof mass. The electrical properties of the electrodes causing floating, such as currents and/or voltages, typically change in response to environmental perturbations affecting the proof mass. Measuring such currents and/or voltages allow immediate and accurate measurements to be performed related to those perturbations affecting the location and/or the orientation of the proof mass. Additional sensing electrodes can be included to further enhance sensing capabilities. Drive electrodes can also be included that allow forces to be applied to the charged proof mass resulting in a floating, electrically controllable MEMS device. Several applications are described including accelerometers, inertial sensors, resonators and filters for communication devices, gyros, one and two axis mirrors and scanners, among other devices. Several fabrication methods are also described.

Optical MEMS scanning micro-mirror comprising:—a movable scanning micro-mirror (101) pivotally connected to a MEMS body (102) substantially surrounding the lateral sides of the micro-mirror;—an transparent prism (500, 600) substantially covering the reflection side of the micro-mirror;—wherein said prism has its outer face non-parallel to the micro-mirror neutral plane N-N, thereby providing a dual anti-speckle and anti-reflection effect, namely against parasitic light. The invention also provides the corresponding micro-projection system and method for reducing speckle.

A method (and structure) of making an electronic interconnection, includes, for a signal line to be interconnected, using a plurality of bonding wires configured to provide a controlled impedance effect.

The utility model discloses a planar capacitance resonator and the related preparation method, comprising a resonance body, a sensor electrode, a driving electrode and a related supporting substrate. The resonator is a suspended structure, and is fixed on the substrate through an anchor point; each of the sensor electrode and the driving electrode comprises an electrode plate and a solder pad, the electrode plates of the sensor electrode and the driving electrode are arranged on the two side of the resonance body separately and keep a clearance from the resonance body, the clearance between the plates performs as the media to form the capacitor structure; the solder pads of the sensor electrode and the driving electrode are fixed on the insulating medium layer, and the solder pads are provided with metal electrodes; the insulating medium layer are fixed on the substrate. The clearance between the any two electrodes of the capacitors is narrower than 100nm. The utility model has the advantages of extremely high dynamic performance, the harmonic resonance frequency exceeding 100 MHz, and the Q factor up to 105.

Circuits and methods to achieve a low-noise and low offset continuous sigma-delta modulator used e.g. for battery management are disclosed. Continuous integration of input is enabled by special switching principle of three parallel integrators. Precharging of integrator output in so called pre-run mode minimizes integrator leakage and non-ideal effects by connecting a Gm in pre-run mode either to input voltage or to a reference voltage depending this Gm is being used in a following clock period. Parasitic effects due to switching at first integration capacitor are minimized by using buffer amplifiers tracking the voltage on integration capacitors.

The invention concerns a heterojunction bipolar transistor comprising a support, and epitaxially grown from said support, at least: one collecting, respectively emitting, layer; at least one base layer; and at least one emitting, respectively collecting, layer. The collecting, respectively emitting, layer comprises: at least one first undercoat contacted with said base layer, substantially of similar composition as said emitting, respectively collecting, layer; and at least one second undercoat on the side opposite said base layer relative to said first undercoat.

Clock signal distribution systems with reduced parasitic loading effects are provided. A reference clock is frequency-divided to produce a lower frequency clock signal. A delay-locked loop (DLL) circuit locks to the lower frequency clock signal, and outputs a corresponding lower frequency clock signal for distribution over a long trace. Power consumption caused by parasitic capacitance of the trace is thereby reduced. Parasitic effects associated with clock jitter are also reduced. A frequency multiplying phase-locked loop (PLL) circuit locks to the lower frequency clock signal, and outputs at least one clock signal having a higher frequency than the lower frequency signal.

The present invention discloses a power divider, wherein a transmission line includes a sub-2 connector, two branch ports of the connector are connected to two output main branches separately, more than two branch lines for communicating the two output main branches are arranged between two output main branches, the branches are designed so that a difference of a sum of a path from a node A to a node B11 and a path from the node A to a node B12, and a path from the node B11 to the node B12 is (Lambadaj/2)*(2p +1) + (Lambadaj/2)*Zeta, and the branches of other nodes are designed so that a difference of a sum of a path from a node Bk1 to a node B(k-1)1 and a path from the node B(k-1)1 to a node B(k-1)2 as well as a path from the node B(k-1)2 to a node Bk2, and a path from the node Bk1 to the node Bk2 is (Lambadai/2)*(2m+1) + (Lambadai/2) * Delta. The output and input of the invention are matched well, there is a good separation between two output ends, and overcomes autoeciousness effects of Wilkinson power divider caused by insulation electric resistances and a problem that a phase of a signal outputted from a directly-connecting end is inconsistent to that of a signal outputted from a coupling end of a branch line electric bridge power divider.

A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

A dual-gate thin film transistor (DG-TFT) and associated fabrication method are provided. The method comprises: forming a first (back) gate in a first horizontal plane; forming source/drain (S/D) regions and an intervening channel region in a second horizontal plane, overlying the first plane; and, forming a second (top) gate in a third horizontal plane, overlying the second plane. The S/D regions and intervening channel region have a combined length, smaller than the length of the first gate. A substrate insulating layer is formed over the substrate, made from a material such as SiO2. A first gate insulation layer is formed over the first gate. Amorphous silicon (a-Si) is deposited over the first gate insulation layer and crystallized. The S/D and channel regions are formed from the crystallized Si layer. A second gate oxide layer is formed over the channel region.

The invention discloses a flexible-substrate-based passive wireless pressure sensor with a self-packaging function. The pressure sensor comprises an upper flexible substrate, an upper metal layer, a middle flexible substrate, a lower metal layer and a lower flexible substrate, which are sequentially arranged from top to bottom and fixedly connected. An electric through hole and a cavity are formed in the middle flexible substrate. The upper metal layer comprises a planar inductance coil and a capacitor upper polar plate positioned on the middle part of the planar inductance coil. An inner connector of the planar inductance coil is connected with the capacitor upper polar plate. The lower metal layer comprises a capacitor lower polar plate opposite to the upper plate capacitor and an interconnecting wire connected with the capacitor upper polar plate. The sizes of the capacitor upper polar plate and capacitor lower polar plate are the same. An outer connector of the planar inductance coil of the upper metal layer is connected with the interconnecting wire of the lower metal layer through a conductive medium column in the electric through hole. The cavity of the middle flexible substrate is positioned between the capacitor upper polar plate and capacitor lower polar plate. The pressure sensor has the high performance of self packaging, non-contact, high sensitivity and high quality factor.

A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process.

The invention belongs to the semi-conductor power device technical field. A SOI layer of the device is thinner (1to 2um); a grid oxide layer is thick (100 to 800nm); a grid field plate gets across a grid and extends above a drift region. An active expansion region positioned below the thick grid oxide layer and connected with a source region can be also arranged in the body of the device to assure the more effective formation of the whole device. The grid oxide layer of the invention is thicker, can bear high grid-source voltage and meet the need of a level displacement circuit; the SIO layer is thinner, can decrease the parasitic effect of the device and reduce consumption; through adding the grid field plate striding over the grid on the surface of the power device, the depletion of the drift region can be increased, the electric field peak value on the silicon surface at the tail end of the grid is decreased, the breakdown characteristic of the device is improved, further more the concentration of the drift region is helped to improve, and the on-state resistance of the device is decreased. The invention has the advantages of low parasitic effect, fast speed, low power consumption, strong radiation-resistant ability and so on, and is compatible with the standard process. By adopting the invention, various high-voltage, high-speed and low conducting loss devices of excellent performance can be produced.

The invention provides a multilayer interconnection structure of wafer level package, a manufacturing method and application thereof. The multilayer interconnection structure is used for microwave multi chip modules. The invention is characterized by using benzocyclobutene (BCB) as a dielectric layer, realizing the multilayer connection structure of a metal/organic polymer by combining wafer levelprocessing technics such as photoetching, electroplating, mechanical polishing and the like and embedding integrated varied passive devices and transmission lines for interconnection. The whole process is matched with IC process, is completed on the basis of wafer level and has higher integration of packaging and lower high-frequency transmission loss. The structure can effectively integrate varied function device units, reduce the interconnection loss among the devices and improve the properties of the whole module while improving the density and integration of packaging and reducing the cost of packaging.

A power semiconductor package structure includes a carrier, a first power chip, a second power chip, a first conductive sheet, a second conductive sheet and a third conductive sheet. The first power chip has a first surface and a second surface opposing to the first surface. A first control electrode and a first main power electrode are disposed on the first surface, and a second main power electrode is disposed on the second surface. The second surface is disposed on the carrier, and electrically connected to the carrier through the second main power electrode. The second power chip has a third surface and a fourth surface opposing to the third surface. A third main power electrode is disposed on the third surface, and a fourth main power electrode is disposed on the fourth surface. The fourth surface is disposed on the first power chip. The first conductive sheet is electrically connected to the first main power electrode and the fourth main power electrode. The second conductive sheet is electrically connected to the third main power electrode. The third conductive sheet is electrically connected to the first control electrode. At least a part of the first control electrode is non-covered by the second power chip along a projection direction, which is perpendicular to the carrier.

A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.

A method of fabrication of a device includes forming a first metallization layer that is coupled to a logic device of the device. The method further includes forming a second metallization layer that is coupled to a magnetoresistive random access memory (MRAM) module of the device. The second metallization layer is independent of the first metallization layer.

A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A conductive structure is disposed within the through holes A plurality of discrete contact members are located in the plurality of the through holes, within the conductive structure. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. The conductive structure can be electrically coupled to circuit geometry. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to desired circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.

The invention discloses a method for making substrate, which includes providing a core board having inner circuits on both upper and lower sides; forming a storage space on the core board; embedding an element in the storage space and forming an insulation layer to coat the element, core board and the inner circuit of upper and lower sides; forming plural holes on the insulation layer to expose plural electrodes of the elements; forming plural through holes to drill through the insulation layer and the core board; making conductive membrane on the surface of the insulation layer and the side walls of the through holes; forming conductive layer on the conductive membrane; patterning the conductive layer to form outer layer circuit; forming anti-welding layer on the outer layer circuit.

A switch controller includes a primary side including signal transmission circuitry to transmit signals representative of desired transitions of a switch. A signal transformer galvanically isolates the primary side from a secondary side but inductively couples signal transmission circuitry to signal reception circuitry. A switch is coupled to switch a low impedance onto a primary side winding of the signal transformer during pauses between transmissions of the signals representative of the desired transition of the switch. The secondary side includes signal reception circuitry, a drive signal generator to generate a drive signal in response to valid signals received by the signal reception circuitry, and a validation circuit that includes a first comparator, a timer, and a second comparator to compare a timed duration with a threshold duration, and to output to the drive signal generator signals indicative of the validity of particular signals received by the signal reception circuitry.