38results about How to "Reduce parasitic effects" patented technology

The invention provides a GaN monolithic integrated device and a preparation method thereof, and belongs to the technical field of semiconductor devices. According to the invention, the GaN monolithic integrated device is obtained by integrating the high-density capacitor with the deep groove structure and the GaN HEMT device. According to the GaN monolithic integrated device, the parasitic effect can be greatly reduced or eliminated, and the circuit reliability is improved; moreover, compared with a planar MIM capacitor, the high-density capacitor with the deep groove structure has the advantage that the capacitance density is improved by more than 100 times; in addition, the structure is equivalent to thinning the substrate, and the heat dissipation capability of the integrated device can also be improved.

The invention relates to the technical field of laser, in particular to an on-chip series edge-emitting semiconductor laser array and a process method. The on-chip series edge-emitting semiconductor laser array sequentially comprises a semi-insulating substrate, a non-doped buffer layer, a P-type heavily doped layer, a P-type tunnel junction layer, an N-type tunnel junction layer, an N-type cladding, an N-type waveguide layer, an active region, a P-type waveguide layer, a P-type cladding and a P-type cover layer from bottom to top. Table surfaces on the two sides of each light-emitting unit are deeply etched to the P-type heavily doped layer, and a lateral current diffusion suppression groove is formed between the bottoms of any two adjacent light-emitting units. An on-chip series edge-emitting semiconductor laser array structure is adopted, the parasitic effect is reduced through coplanar electrode design, upper and lower electrodes can be prepared through a single process to reduce the cost, lateral current diffusion suppression grooves are formed between light-emitting units to reduce crosstalk, the light-emitting units are connected in series to work under the same injection current, and the light-emitting efficiency is improved. The requirements of a driving circuit can be effectively reduced, and light-emitting uniformity is improved.

The invention relates to a preparation method of a multi-chip interconnection packaging structure and the multi-chip interconnection packaging structure. The preparation method of the multi-chip interconnection packaging structure comprises the following steps: providing a packaging substrate and a plurality of chips; a substrate circuit is arranged in the packaging substrate; providing an interconnection chip; a chip interconnection circuit is arranged in the interconnection chip; forming a plurality of grooves in one side of the packaging substrate; mounting interconnection chips in the plurality of grooves in a one-to-one correspondence manner, wherein the thickness of the interconnection chips is smaller than or equal to the depth of the grooves; a plurality of chips are inversely arranged on the side, where the interconnection chips are exposed, of the packaging substrate, the interconnection chips are connected with at least two chips at the same time, and meanwhile the chips are connected with the substrate circuits respectively. According to the preparation method of the multi-chip interconnection packaging structure, the height of the packaging structure can be reduced, the process can be simplified, the reliability and the yield of the packaging structure can be improved, the test cost can be reduced, and the parasitic effect between the chips can be reduced.

The invention relates to a signal control circuit based on a transverse tandem photoelectric detection unit structure and a control method, and belongs to the field of photoelectric detection and control. The circuit comprises a transverse tandem detection unit structure and a post-stage signal processing circuit, wherein the post-stage signal processing circuit comprises a plurality of resistor units, a bipolar transistor and an MOS (Metal Oxide Semiconductor) tube; according to the method, an optical signal is converted into an electric signal through a transverse tandem type detection unit structure, and charge release and voltage signal output processing are carried out through a post-stage signal processing circuit. When light enters the transverse tandem type detection unit structure, the output tube is switched on; when no photo-generated current exists, the output tube is switched off; and the output tube can output a voltage control signal meeting the amplitude requirement when being switched on or switched off so as to control the working state of a rear-end circuit. By combining the photoelectric detection unit and the signal processing circuit, monolithic integration and process fusion of the silicon-on-insulator process are realized, the parasitic effect between elements can be effectively reduced, and the interconnection scheme of discrete devices is upgraded.

The present invention relates to a GaN power chip with junction temperature monitoring and over-temperature protection capabilities, comprising: a power device, a first ohmic contact structure, a second ohmic contact structure and a temperature sensor diode which are sequentially distributed laterally on a two-dimensional electron gas structure and electrically isolated from each other; the power device comprises a source, a drain and a gate; the first ohmic contact structure comprises a first ohmic contact electrode and a second ohmic contact electrode which are spaced apart; the second ohmic contact structure comprises a third ohmic contact electrode and a fourth ohmic contact electrode which are spaced apart; the temperature sensor diode comprises a cathode, an anode and a first part of a P-GaN layer; the first ohmic contact electrode is used for grounding, the second ohmic contact electrode and the third ohmic contact electrode and the gate are connected in parallel, the fourth ohmic contact electrode and the cathode are connected in series and used for outputting a voltage, and the anode is used for connecting a power supply voltage. The GaN power chip can monitor the junction temperature change of the power device in situ, and can also realize an over-temperature intelligent protection mechanism.

The application relates to a full GaN power electronic monolithic integrated circuit and a preparation method thereof, which comprises, from bottom to top, an insulating composite substrate, an AlN layer, a Si layer, a GaN / AlGaN buffer layer, a GaN layer and an AlGaN layer; a 2DEG layer is formed between the GaN layer and the AlGaN layer; the AlGaN layer is etched, a p-GaN layer is grown; a p-GaN layer gate portion is etched and filled with a passivation layer, and a gate metal is grown; source metal and drain metal are respectively grown on both sides of the p-GaN layer gate area; a deep groove is arranged between a driving circuit and a low-voltage tube, between a high-voltage tube and the low-voltage tube, and a medium is filled in the deep groove; and the full GaN power electronic monolithic integrated circuit is obtained through a top via and an interconnection process. The application can realize high efficiency and low power consumption, low parasitic effect, and reduce leakage current and switching loss.

The invention discloses a capacitive voltage division type voltage transformer suitable for broadband voltage measurement and a measurement method, and relates to the technical field of power grid broadband voltage measurement, the transformer mainly comprises a high-voltage capacitor and a low-voltage capacitor which are connected in series, a neutral point measurement coil and an impedance transformer. The measurement method relates to calculation in multiple aspects such as capacitance voltage division, inductance coil induction and circuit impedance matching, and accurate voltage measurement can be realized in a broadband range of 10Hz-1MHz. Compared with the prior art, the measuring precision is improved, the dynamic response characteristic and the broadband measuring capacity are good, the performance is stable and reliable, the structure is simple, and installation and maintenance are easy.

The present application relates to a kind of vertical channel field effect transistor and its preparation method, belong to semiconductor device technical field.It includes: silicon oxide substrate, its one side is provided with high platform;Wherein, high platform each side is provided with multilayer film structure;First guide groove on the first side of multilayer film structure and first guide groove on the second side of adjacent multilayer film structure are communicated;First guide groove is perpendicular to silicon oxide substrate;Multiple first dielectric layer, is set to the surface of silicon oxide substrate;Wherein, first dielectric layer both sides are provided with second guide groove;Second guide groove is communicated with the nearest first guide groove;First guide groove and second guide groove are provided with nanowire;Source electrode, is set to the side of high platform away from silicon oxide substrate;Multiple gate electrode, each gate electrode is set to the third side of each multilayer film structure, and is connected with dielectric layer.The present application realizes single nanowire high-density multi-independent channel, improves structure utilization.

The invention discloses a monolithic integrated diode amplitude limiting unit based on quasi-vertical MPSs and a preparation method thereof. The amplitude limiting unit comprises two silicon-based GaN quasi-vertical MPSs located on a silicon substrate, and a forward amplitude limiting diode and a reverse amplitude limiting diode are formed; the passivation layer covers the two MPSs and the silicon substrate; the thin film protection resistor is located in the passivation layer; the first interconnection metal connects the first end of the resistor with the cathode of the reverse amplitude limiting diode; the second interconnection metal forms a voltage input end, a voltage output end, a first reference voltage end and a second reference voltage end, the cathode of the forward amplitude limiting diode is connected with the first reference voltage end, and the anode of the forward amplitude limiting diode, the cathode of the reverse amplitude limiting diode and the first end of the thin film protection resistor are connected with the voltage output end. And the anode of the reverse amplitude limiting diode is connected with a second reference voltage end, and the second end of the resistor is connected with the voltage input end 1. The diode amplitude limiting unit provided by the invention has relatively high voltage resistance and can be applied to a high-power condition.

A semiconductor device (100) for controlling an electric current flowing between a source terminal (102) and a drain terminal (104) and a method for forming such a device are disclosed. The semiconductor device is formed from a layer stack of GaN layers, wherein a vertical junction field effect transistor JFET structure (120) and a lateral high electron mobility transistor HEMT structure (130) are provided to control the electric current.

The utility model discloses a novel small-size multi-layer chip type power divider, which adopts a miniaturized multi-layer chip type structure manufactured by an LTCC (Low Temperature Co-Fired Ceramic) technology, has the advantages of high reliability, low insertion loss, high isolation, small size, light weight, easiness in integration, low cost and the like, and is suitable for large-scale production. Therefore, the application is very wide, and the size can be reduced to 0.65 mm * 0.50 mm * 0.35 mm. On the basis of the LTCC (Low Temperature Co-fired Ceramic) technology, a traditional Wilkinson power divider lumped parameter model design is adopted, a capacitor and an inductor adopt an up-and-down structure, the capacitor is arranged on the lower layer to conveniently form a grounding capacitor with GND (Ground), parasitic inductance introduced by a connecting line is reduced, the inductor is arranged on the upper layer to reduce parasitic effect between the inductor and the capacitor, and thus the reliability of the power divider is improved. The middle parts are connected through point columns.

The invention relates to the technical field of micro electro mechanical systems, in particular to an MEMS pressure sensor chip capable of working in an extreme environment and a manufacturing method of the MEMS pressure sensor chip. The pressure sensor comprises an SOI silicon-on-insulator substrate, a piezoresistive resistor, a middle silicon nitride insulation isolation layer, a through hole layer, an organic epoxy insulation packaging layer, a sensor film layer and a conductive material assembly used for connection. Four piezoresistive resistors are formed by ion implantation and are symmetrically distributed on the thin film layer to form a Wheatstone bridge structure. The sensor film layer is square, the size of the sensor film layer is smaller than that of the substrate, the sensor film layer is I-shaped, the thermal stress concentration effect is reduced, cracks or deformation is avoided, the sensor film layer and the substrate jointly form a vacuum cavity, and high structural stability is kept. The insulating packaging layer is connected with the through hole layer, and the through holes are connected with the insulating layer through the conductive material of the opening of the insulating layer. The sensor provided by the invention can keep higher measurement precision and sensitivity in an extreme temperature environment.

The invention provides a packaging structure. A conductive substrate of the packaging structure is arranged on a support. The first, second, and third bond pads are disposed on the bracket, and the first and second bond pads are separated from the conductive substrate, while the third bond pad is connected to the conductive substrate. The laterally diffused metal oxide semiconductor transistor is arranged on the conductive substrate and comprises a first drain electrode, a first grid electrode and a first source electrode. The depletion mode III-V transistor is disposed on the conductive substrate and separated from the laterally diffused metal oxide semiconductor transistor, and includes a second drain, a second gate, and a second source. The first drain electrode, the first grid electrode and the first source electrode are respectively connected with the second source electrode, the first bonding pad and the conductive substrate connected with the third bonding pad through corresponding bonding wires, and the second drain electrode and the second grid electrode are respectively connected with the second bonding pad and the conductive substrate connected with the third bonding pad through corresponding bonding wires. The efficiency of the switching device can be improved.

The present invention provides a wide bandgap terahertz Schottky diode and a preparation method thereof, belonging to the technical field of semiconductor devices. The Schottky diode comprises a substrate, a buffer layer, a channel layer, a barrier layer and a P-type NiO terminal which are stacked in sequence. The channel layer and the barrier layer form a heterojunction, and a two-dimensional electron gas is formed at the interface contact between the two. Anode grooves are etched on both sides of the barrier layer and the channel layer, and the bottom of the anode groove is located in the channel layer; the anode is arranged in the anode groove and forms a Schottky contact with the two-dimensional electron gas. The P-type NiO terminal is located on both sides of the surface of the barrier layer away from the channel layer, close to the anode groove, and the anode extends to the surface of the P-type NiO terminal away from the barrier layer and covers the P-type NiO terminal. The Schottky diode has the characteristics of small on-resistance, small junction capacitance, large cut-off frequency and larger nonlinear range.

The invention relates to a multi-band filtering array antenna. Comprising a localized surface plasma and surface wave transmission gate of a single-layer structure, and an antenna patch assembly, the localized surface plasma is a polygon, and a first medium unit is arranged along the side length of the polygon; the number of the surface wave transmission grids corresponds to the number of the first medium units, second medium units are arranged along the single sides of the long edges of the surface wave transmission grids, and the positions of the second medium units are respectively opposite to the positions of the first medium units; the number of the antenna patch assemblies is one less than that of the surface wave transmission grids; the ports of the surface wave transmission gates are extended and then are connected with the antenna patch assemblies, and the ports of the surface wave transmission gates which are not connected with the antenna patch assemblies are used as output ends. The local surface plasma and the surface wave transmission gate are combined to serve as the multi-band filter, then the multi-band filter is connected with the antenna patch assembly to form the multi-band filtering array antenna, and needed multi-band signals can be obtained at the output end.

The embodiment of the invention discloses an audio amplifier chip controlled through digital input and an audio amplifier. The audio amplifier chip comprises an input port, a DAC, a positive voltage power supply, a gate drive unit, a half-bridge circuit, a negative voltage control mechanism algorithm and a negative voltage generation circuit, and the half-bridge circuit is formed by connecting two switching tubes in series; wherein the input port is used for receiving a digital input audio signal, and the input port is respectively connected with the voltage generation circuit and the gate driving unit through the DAC; the negative voltage generation circuit is used for generating negative voltage according to a negative voltage control mechanism algorithm and a digital input audio signal; the gate driving unit is used for generating a PWM signal according to a digital input audio signal; the duty ratio of the pulse width modulation signal is determined according to the voltage output by the positive voltage power supply, the negative voltage and the output signal of the audio amplifier chip; and applying a pulse width modulation signal with a duty ratio to the grid electrode of the switching tube. The embodiment of the invention can reduce the device cost and improve the performance of the audio amplifier.

An on-chip transformer includes a primary coil and a secondary coil, each of which includes multiple metal layers; all metal layers are stacked in the height direction of the primary coil and the secondary coil; each metal layer includes a plurality of independent metal rings with the same structure; the metal rings are configured as a spiral structure diffused from the inside to the outside; the top metal layer in the primary coil is provided with N input terminals; the top metal layer in the secondary coil has (N+1) output terminals, where N is an integer; the signal enters through the input terminal and then outputs from the output terminal. The present invention also proposes a manufacturing process for preparing the above-mentioned on-chip transformer. The present invention has a large coupling area and a small occupied area, and is also suitable for half-bridge or full-bridge DC-DC converters, and can achieve output of any proportion by adjusting the voltage by boosting, bucking or equalizing, balancing the resistance and reducing the parasitic effects in the coil.

The present application is directed to the field of power device packaging technology, and specifically relates to a power module structure, a power module package, and a method for manufacturing the package. The power module structure includes: a lead frame, a first chip is welded on the lead frame; a second chip, the second chip is arranged on the first chip, and is coupled and connected to the first chip through a conductive adhesive. The package includes a substrate, a positioning hole is provided on the substrate, and the power module structure as described in the first aspect of the present application is arranged in the positioning hole; a metal wire is provided on the substrate around the positioning hole, and the lead end of the power module structure is connected to the metal wire; a lower heat sink, the lower heat sink is arranged under the substrate, and is used to dissipate heat from the power module structure. The present application provides a power module structure and a package thereof, which can improve the response speed of the device while reducing the size of the device.

The present invention provides a multi-channel Schottky diode with a three-dimensional fishbone-shaped anode and a preparation method thereof, belonging to the technical field of semiconductor devices. The Schottky diode comprises a substrate, a buffer layer, a multi-channel structure and a cap layer, as well as an anode and a cathode stacked in sequence; the multi-channel structure comprises a channel layer and a barrier layer stacked alternately in sequence; the cathode is arranged on both sides of the cap layer and the multi-channel structure, and forms an ohmic contact with the multi-channel structure; a structure composed of a cap layer and a multi-channel structure located between two cathodes is provided with a plurality of anode grooves arranged at intervals, and the anode is deposited in the anode groove and on the surface of the cap layer between two adjacent anode grooves, so that the anode as a whole forms a three-dimensional fishbone-shaped structure with an anode field plate; the anode forms a Schottky contact with the multi-channel structure. The Schottky diode has the characteristics of small parasitic effect, small on-resistance, large breakdown voltage and small turn-on voltage.

The invention discloses a nonvolatile memory. A device unit structure comprises a vertical channel region and a gate structure. The gate structure covers one of the side surfaces on both sides of the width edge of the vertical channel region. The gate structure comprises a selection gate and a storage gate. A first gate dielectric layer is arranged between the selection gate and the vertical channel region in a spaced mode, and a first dielectric layer is arranged between the selection gate and the semiconductor substrate in a spaced mode. The storage gate is located at the top of the selection gate and spaced by a second dielectric layer. And a second gate storage medium layer is spaced between the storage gate and the vertical channel region. The surface of the vertical channel region covered by the gate structure is used for forming a vertical channel, a second vertical channel part is controlled by the storage gate, when charges are stored in the second gate storage medium layer, the storage bit is' 0 ', and otherwise, the storage bit is' 1 '. The size of the device can be reduced, so that the size miniaturization of the device can be conveniently realized; the storage stability can be improved; the service life can be prolonged; the working bias voltage can be reduced; and the reading and erasing speeds are increased.

The application discloses a self-capacitance fingerprint detection circuit and method, comprising a target pixel, a fingerprint pixel, an adjacent pixel, a switch network, a local operational amplifier, a first voltage source and a second voltage source; the target pixel and the adjacent pixel are connected with the local operational amplifier through the switch network; the first voltage source is connected with the target pixel and the adjacent pixel through the switch network; the elimination of the parasitic effect and the detection of the fingerprint are realized through three steps of detection electrode initialization, parasitic electrode reset and transfer of finger charge; the parasitic effect between the target pixel detection electrode and the parasitic electrode is completely eliminated without charging and discharging the circuit outside the target pixel detection electrode, the fingerprint sensitivity is improved, the circuit is simplified, and the power consumption is saved.

The utility model discloses a kind of power modules, including circuit board assembly and power chip assembly;Wherein, circuit board assembly includes first circuit board, third circuit board and the second circuit board being arranged between the two, power chip assembly includes the first power chip being arranged between first circuit board and second circuit board and the second power chip being arranged between third circuit board and second circuit board;Second circuit board is equipped with metal component, first power chip and second power chip are electrically connected with the metal component;First circuit board is equipped with the first insulating heat-conducting component for the heat dissipation of first power chip, and third circuit board is equipped with the second insulating heat-conducting component for the heat dissipation of second power chip.The power module of the utility model has the advantages of small packaging area and low parasitic effect.

The present invention belongs to the field of chip heat dissipation technology, and relates to a high aspect ratio microchannel heat sink and its preparation method and application. The heat sink is provided with a microchannel for cooling the working medium in and out, the microchannel has a high aspect ratio, and a plurality of staggered ribs are arranged in the microchannel, and the radial cross section of the rib gradually decreases from both ends to the middle along the axial direction. The heat sink provided by the present invention can improve the heat dissipation performance of the microchannel.

This invention discloses an optoelectronic integrated device and its fabrication method, comprising: multiple ordered basic units, each basic unit including a multi-quantum-well MicroLED and a vertical GaN MOSFET; a bonding dielectric layer is provided on the top layer of the sapphire substrate, and the bottom layer of the sapphire substrate is the light-emitting surface of the device; the multi-quantum-well MicroLED is disposed on the top layer of the bonding dielectric layer; the vertical GaN MOSFET is disposed above the multi-quantum-well MicroLED, and the drain region of the vertical GaN MOSFET and the N-region of the multi-quantum-well MicroLED are connected in series through a shared diode N-GaN structure layer; the light-emitting device and the driving electronic device of this invention are fabricated on the same chip, which not only enables mass production using existing GaN process platforms, reducing production costs, but also has significant advantages such as small size, high speed, and high reliability; the GaN MOSFET adopts a novel vertical structure design, which can greatly shorten the channel length of the driving transistor, which is of great significance for improving the performance and integration density of the integrated device.

The invention provides a high-reliability electric signal vertical lead-out method of a vacuum sealing MEMS chip, which comprises the following steps: S1, carrying out metal layer or dielectric layer deposition, photoetching and etching on the bottom surface of a vertical lead layer of the MEMS chip to form a bonding pattern layer; wherein the vertical lead layer is a TGV layer or a TSV layer; s2, performing alignment eutectic bonding sealing packaging on the silicon wafer containing the silicon microstructure and the bonding pattern layer; wherein a sealing support sheet is arranged at the bottom of the silicon wafer; and S3, depositing a metal film layer on the top surface of the bonded vertical lead layer, and forming an electrode bonding pad through photoetching and wet etching, so that the electrode bonding pad is conducted with a silicon lead of the silicon wafer. A graphical bonding sealing process is combined with the TSV or the TGV containing the metallized filler with good conductivity, so that the air tightness process requirements of the metallized filled TGV and the TSV are favorably relaxed, and a process scheme which gives consideration to the high vacuum sealing performance of the MEMS chip and the high-reliability vertical extraction of an electric signal is provided.

The invention discloses an integrated packaging chip structure, and relates to the technical field of integrated photoelectronics. The integrated packaging chip structure comprises an optical signal transmitting layer, a substrate, an optical signal receiving layer and a printed circuit board which are stacked, wherein a first matching circuit chip is arranged on the surface, far away from the substrate, of the optical signal receiving layer and is used for amplifying a signal received and detected by the optical signal receiving layer; the printed circuit board is provided with a groove, and the first matching circuit chip is embedded into the groove to be connected with the printed circuit board.

The invention relates to an SOI-based MIS p-GaN HEMT half-bridge integrated circuit and a preparation method thereof. The SOI-based MIS p-GaN HEMT half-bridge integrated circuit comprises an SOI substrate, an AlN layer, a GaN layer, an AlGaN layer, a p-GaN layer and a second insulating dielectric layer which are sequentially arranged from bottom to top. The SOI substrate comprises substrate silicon, a first insulating medium layer and top silicon; etching the p-GaN layer and the second insulating dielectric layer, growing a third insulating dielectric layer, and preparing a grid electrode; source electrode metal and drain electrode metal respectively grow on two sides of the grid electrode; field plate metal grows above the source electrode metal and the grid electrode metal and is filled with a fourth insulating dielectric layer; a deep groove is formed in the middle of the circuit and penetrates through the fourth insulating medium layer, the third insulating medium layer, the AlGaN layer, the GaN layer, the AlN layer, the top silicon layer and the filling insulating medium. Filling the top with a fifth insulating dielectric layer; and obtaining a half-bridge integrated circuit through a top through hole and an interconnection process. According to the invention, the parasitic effect can be reduced, and leakage current and switching loss are reduced.

The invention discloses a Vcm-based capacitor switch sequential circuit and a Vcm-based capacitor switch sequential method. A first array first capacitor bank, a second array first capacitor bank,..., an ith array first capacitor bank, a first array second capacitor bank, a second array second capacitor bank,..., a jth array second capacitor bank, a first array dummy capacitor bank and a second array dummy capacitor bank in the switch sequence circuit respectively comprise two capacitors which are connected in parallel and have the same capacitance value, according to the improved capacitor array structure, each capacitor is divided into two equal capacitors, the two equal capacitors can be connected with different potentials through a lower electrode plate to achieve three different voltage connection methods, namely Vref, 1 / 2 Vref and GND, the equivalent circuit structure of the capacitor array structure is basically consistent with Vcm-based, but Vcm is equal to 1 / 2 Vref through the arrangement of the two equal capacitors, and the equivalent circuit structure of the capacitor array structure is not equal to GND. The improved Vcm-based capacitor switch time sequence does not need an additional circuit to generate a common-mode level Vcm, does not need a complex bootstrap switch structure, reduces the power consumption and the area, and is suitable for the design of a low-voltage SAR ADC (Synthetic Aperture Radar Analog to Digital Converter).

This invention discloses an arithmetic logic circuit suitable for balanced ternary systems, comprising a unary balanced ternary operation circuit, a balanced ternary half-adder circuit, a balanced ternary full-adder circuit, and a balanced ternary multiplier circuit. Single-input logic conversion is achieved through the combination of polarized ternary inverters and transistors. The half-adder consists of a basic unit and a transmission gate, realizing two-bit summation and carry output. The full-adder employs two cascaded half-adders and optimizes the carry path, significantly shortening the critical path and reducing the number of transistors. The multiplier uses the basic unit as the control core and combines it with a standard ternary inverter to achieve accurate multiplication. This invention overcomes the interconnection bottleneck of traditional binary logic, avoids the high hardware overhead of unbalanced ternary logic circuits in signed number calculations, and avoids the accuracy loss of approximate calculations in existing balanced ternary logic circuits. It has advantages such as simplified structure, low latency, low power consumption, and accurate operation, and is suitable for high-performance computing scenarios such as artificial intelligence, big data, and very large-scale integrated circuits.

The utility model discloses a power module with low stray inductance, which relates to the technical field of power modules and comprises a supporting substrate, an upper bridge arm unit and a lower bridge arm unit, and the upper bridge arm unit and the lower bridge arm unit are symmetrically arranged on the supporting substrate. The upper bridge arm unit comprises an upper bridge DBC substrate, the lower bridge arm unit comprises a lower bridge DBC substrate, and the upper bridge DBC substrate is electrically connected with the lower bridge DBC substrate; a positive power terminal is bonded on the upper bridge DBC substrate, a negative power terminal matched with the positive power terminal is bonded on the lower bridge DBC substrate, and the negative power terminal is adjacent to the positive power terminal and is overlapped with the positive power terminal. The power module can effectively reduce stray inductance and has high reliability.