18results about How to "Reduce parasitic effects" patented technology

The invention relates to a signal control circuit based on a transverse tandem photoelectric detection unit structure and a control method, and belongs to the field of photoelectric detection and control. The circuit comprises a transverse tandem detection unit structure and a post-stage signal processing circuit, wherein the post-stage signal processing circuit comprises a plurality of resistor units, a bipolar transistor and an MOS (Metal Oxide Semiconductor) tube; according to the method, an optical signal is converted into an electric signal through a transverse tandem type detection unit structure, and charge release and voltage signal output processing are carried out through a post-stage signal processing circuit. When light enters the transverse tandem type detection unit structure, the output tube is switched on; when no photo-generated current exists, the output tube is switched off; and the output tube can output a voltage control signal meeting the amplitude requirement when being switched on or switched off so as to control the working state of a rear-end circuit. By combining the photoelectric detection unit and the signal processing circuit, monolithic integration and process fusion of the silicon-on-insulator process are realized, the parasitic effect between elements can be effectively reduced, and the interconnection scheme of discrete devices is upgraded.

The application relates to a full GaN power electronic monolithic integrated circuit and a preparation method thereof, which comprises, from bottom to top, an insulating composite substrate, an AlN layer, a Si layer, a GaN / AlGaN buffer layer, a GaN layer and an AlGaN layer; a 2DEG layer is formed between the GaN layer and the AlGaN layer; the AlGaN layer is etched, a p-GaN layer is grown; a p-GaN layer gate portion is etched and filled with a passivation layer, and a gate metal is grown; source metal and drain metal are respectively grown on both sides of the p-GaN layer gate area; a deep groove is arranged between a driving circuit and a low-voltage tube, between a high-voltage tube and the low-voltage tube, and a medium is filled in the deep groove; and the full GaN power electronic monolithic integrated circuit is obtained through a top via and an interconnection process. The application can realize high efficiency and low power consumption, low parasitic effect, and reduce leakage current and switching loss.

The present application relates to a kind of vertical channel field effect transistor and its preparation method, belong to semiconductor device technical field.It includes: silicon oxide substrate, its one side is provided with high platform;Wherein, high platform each side is provided with multilayer film structure;First guide groove on the first side of multilayer film structure and first guide groove on the second side of adjacent multilayer film structure are communicated;First guide groove is perpendicular to silicon oxide substrate;Multiple first dielectric layer, is set to the surface of silicon oxide substrate;Wherein, first dielectric layer both sides are provided with second guide groove;Second guide groove is communicated with the nearest first guide groove;First guide groove and second guide groove are provided with nanowire;Source electrode, is set to the side of high platform away from silicon oxide substrate;Multiple gate electrode, each gate electrode is set to the third side of each multilayer film structure, and is connected with dielectric layer.The present application realizes single nanowire high-density multi-independent channel, improves structure utilization.

A semiconductor device (100) for controlling an electric current flowing between a source terminal (102) and a drain terminal (104) and a method for forming such a device are disclosed. The semiconductor device is formed from a layer stack of GaN layers, wherein a vertical junction field effect transistor JFET structure (120) and a lateral high electron mobility transistor HEMT structure (130) are provided to control the electric current.

The embodiment of the invention discloses an audio amplifier chip controlled through digital input and an audio amplifier. The audio amplifier chip comprises an input port, a DAC, a positive voltage power supply, a gate drive unit, a half-bridge circuit, a negative voltage control mechanism algorithm and a negative voltage generation circuit, and the half-bridge circuit is formed by connecting two switching tubes in series; wherein the input port is used for receiving a digital input audio signal, and the input port is respectively connected with the voltage generation circuit and the gate driving unit through the DAC; the negative voltage generation circuit is used for generating negative voltage according to a negative voltage control mechanism algorithm and a digital input audio signal; the gate driving unit is used for generating a PWM signal according to a digital input audio signal; the duty ratio of the pulse width modulation signal is determined according to the voltage output by the positive voltage power supply, the negative voltage and the output signal of the audio amplifier chip; and applying a pulse width modulation signal with a duty ratio to the grid electrode of the switching tube. The embodiment of the invention can reduce the device cost and improve the performance of the audio amplifier.

The application discloses a self-capacitance fingerprint detection circuit and method, comprising a target pixel, a fingerprint pixel, an adjacent pixel, a switch network, a local operational amplifier, a first voltage source and a second voltage source; the target pixel and the adjacent pixel are connected with the local operational amplifier through the switch network; the first voltage source is connected with the target pixel and the adjacent pixel through the switch network; the elimination of the parasitic effect and the detection of the fingerprint are realized through three steps of detection electrode initialization, parasitic electrode reset and transfer of finger charge; the parasitic effect between the target pixel detection electrode and the parasitic electrode is completely eliminated without charging and discharging the circuit outside the target pixel detection electrode, the fingerprint sensitivity is improved, the circuit is simplified, and the power consumption is saved.

The utility model discloses a kind of power modules, including circuit board assembly and power chip assembly;Wherein, circuit board assembly includes first circuit board, third circuit board and the second circuit board being arranged between the two, power chip assembly includes the first power chip being arranged between first circuit board and second circuit board and the second power chip being arranged between third circuit board and second circuit board;Second circuit board is equipped with metal component, first power chip and second power chip are electrically connected with the metal component;First circuit board is equipped with the first insulating heat-conducting component for the heat dissipation of first power chip, and third circuit board is equipped with the second insulating heat-conducting component for the heat dissipation of second power chip.The power module of the utility model has the advantages of small packaging area and low parasitic effect.

This invention discloses an optoelectronic integrated device and its fabrication method, comprising: multiple ordered basic units, each basic unit including a multi-quantum-well MicroLED and a vertical GaN MOSFET; a bonding dielectric layer is provided on the top layer of the sapphire substrate, and the bottom layer of the sapphire substrate is the light-emitting surface of the device; the multi-quantum-well MicroLED is disposed on the top layer of the bonding dielectric layer; the vertical GaN MOSFET is disposed above the multi-quantum-well MicroLED, and the drain region of the vertical GaN MOSFET and the N-region of the multi-quantum-well MicroLED are connected in series through a shared diode N-GaN structure layer; the light-emitting device and the driving electronic device of this invention are fabricated on the same chip, which not only enables mass production using existing GaN process platforms, reducing production costs, but also has significant advantages such as small size, high speed, and high reliability; the GaN MOSFET adopts a novel vertical structure design, which can greatly shorten the channel length of the driving transistor, which is of great significance for improving the performance and integration density of the integrated device.

The invention provides a high-reliability electric signal vertical lead-out method of a vacuum sealing MEMS chip, which comprises the following steps: S1, carrying out metal layer or dielectric layer deposition, photoetching and etching on the bottom surface of a vertical lead layer of the MEMS chip to form a bonding pattern layer; wherein the vertical lead layer is a TGV layer or a TSV layer; s2, performing alignment eutectic bonding sealing packaging on the silicon wafer containing the silicon microstructure and the bonding pattern layer; wherein a sealing support sheet is arranged at the bottom of the silicon wafer; and S3, depositing a metal film layer on the top surface of the bonded vertical lead layer, and forming an electrode bonding pad through photoetching and wet etching, so that the electrode bonding pad is conducted with a silicon lead of the silicon wafer. A graphical bonding sealing process is combined with the TSV or the TGV containing the metallized filler with good conductivity, so that the air tightness process requirements of the metallized filled TGV and the TSV are favorably relaxed, and a process scheme which gives consideration to the high vacuum sealing performance of the MEMS chip and the high-reliability vertical extraction of an electric signal is provided.

The invention relates to an SOI-based MIS p-GaN HEMT half-bridge integrated circuit and a preparation method thereof. The SOI-based MIS p-GaN HEMT half-bridge integrated circuit comprises an SOI substrate, an AlN layer, a GaN layer, an AlGaN layer, a p-GaN layer and a second insulating dielectric layer which are sequentially arranged from bottom to top. The SOI substrate comprises substrate silicon, a first insulating medium layer and top silicon; etching the p-GaN layer and the second insulating dielectric layer, growing a third insulating dielectric layer, and preparing a grid electrode; source electrode metal and drain electrode metal respectively grow on two sides of the grid electrode; field plate metal grows above the source electrode metal and the grid electrode metal and is filled with a fourth insulating dielectric layer; a deep groove is formed in the middle of the circuit and penetrates through the fourth insulating medium layer, the third insulating medium layer, the AlGaN layer, the GaN layer, the AlN layer, the top silicon layer and the filling insulating medium. Filling the top with a fifth insulating dielectric layer; and obtaining a half-bridge integrated circuit through a top through hole and an interconnection process. According to the invention, the parasitic effect can be reduced, and leakage current and switching loss are reduced.

This invention discloses an arithmetic logic circuit suitable for balanced ternary systems, comprising a unary balanced ternary operation circuit, a balanced ternary half-adder circuit, a balanced ternary full-adder circuit, and a balanced ternary multiplier circuit. Single-input logic conversion is achieved through the combination of polarized ternary inverters and transistors. The half-adder consists of a basic unit and a transmission gate, realizing two-bit summation and carry output. The full-adder employs two cascaded half-adders and optimizes the carry path, significantly shortening the critical path and reducing the number of transistors. The multiplier uses the basic unit as the control core and combines it with a standard ternary inverter to achieve accurate multiplication. This invention overcomes the interconnection bottleneck of traditional binary logic, avoids the high hardware overhead of unbalanced ternary logic circuits in signed number calculations, and avoids the accuracy loss of approximate calculations in existing balanced ternary logic circuits. It has advantages such as simplified structure, low latency, low power consumption, and accurate operation, and is suitable for high-performance computing scenarios such as artificial intelligence, big data, and very large-scale integrated circuits.

This invention relates to the field of filter heat dissipation technology, and provides a filter heat dissipation structure, including: a heat dissipation shell; the heat dissipation shell is partially attached to the peripheral wall of the filter magnetic ring; notches are respectively provided on the first and second sides of the heat dissipation shell corresponding to the filter magnetic ring, so that a portion of the filter magnetic ring is exposed through the notches; the first and second sides are opposite sides of the filter magnetic ring; the heat dissipation shell has an inner cavity for introducing coolant. The filter heat dissipation structure of this invention, by designing notches on the opposite sides of the heat dissipation shell corresponding to the filter magnetic ring, can effectively suppress parasitic effects between the heat dissipation shell and the filter magnetic ring, minimizing the impact of parasitic effects on filter performance. It effectively solves the problem in the prior art where metal heat dissipation cavities easily cause parasitic effects between the magnetic core and the metal cavity, leading to attenuation of the magnetic core's high-frequency performance, forward shift of the resonant point, and deterioration of the magnetic core's performance.

This invention provides a GGNMOS electrostatic discharge (ESD) protection device and its fabrication method, comprising: a P-type substrate, an N-type buried layer, a first N-type deep well, a second N-type deep well, and a first P-type well; the first N-type deep well and the second N-type deep well are further provided with a first N+ injection region and a fourth N+ injection region; the first P-type well is provided with a P-type semiconductor substrate and a gate region, a source region, and a drain region of a first NMOS, wherein the drain region of the first NMOS is widened; the first N-type deep well, the second N-type deep well, and the first N+ injection region, the fourth N+ injection region, and the N-type buried layer constitute an N-type isolation band; the P-type semiconductor substrate is connected to the source region of the first NMOS and serves as the cathode of the device, and the drain region of the first NMOS is connected to the first N+ injection region and the fourth N+ injection region on the first N-type deep well and the second N-type deep well and serves as the anode of the device; the gate region of the first NMOS is located between the second N+ and third N+ injection regions; the gate region of the first NMOS is connected to a coupling circuit of a first PMOS, a capacitor C, and an inverter.

This application provides a 2.5D bridging packaging method and a 2.5D bridging packaging structure, relating to the field of semiconductor technology. In this 2.5D bridging packaging structure, the adapter board has a first surface and a second surface disposed opposite to each other. The first surface has a first connection terminal, and the second surface has a second connection terminal. The bridging portion has a third surface and a fourth surface disposed opposite to each other. The third surface has a third connection terminal, and the fourth surface has a fourth connection terminal. A first chip bridges the adapter board and the bridging portion, and the first chip is electrically connected to both the first and third connection terminals. A functional component is connected to the fourth connection terminal. An insulator fills the gap between the adapter board and the bridging portion. A dielectric layer has a fifth connection terminal, and the second connection terminal is electrically connected to the fifth connection terminal. The dielectric layer is disposed on the surface of the insulator or on the side of the adapter board away from the insulator. This structure helps to mitigate leakage caused by parasitic inductance, which can lead to short circuits and overheating between wiring layers.

The utility model discloses a kind of chip top layer structures, comprising: multiple chip modules, each chip module includes multiple pins;And wiring unit, including multiple signal lines for being connected with the pin of multiple chip modules, wherein, wiring unit includes first wiring area and second wiring area, logic signal line, noise signal line and clock signal line in the multiple signal lines are arranged in the first wiring area, sensitive signal line and quiet signal line in the multiple signal lines are arranged in the second wiring area, first wiring area and second wiring area are isolated by continuous isolation band between it.This chip top layer structure of the utility model realizes the inhibition between coupling noise of sensitive signal line and noise signal line and clock signal line and parasitic effect between signal line in layout level, while significantly reduce wiring resource occupancy and design complexity.

The application relates to the technical field of filters, in particular to a high-rectangular-coefficient filter and a design method. The filter comprises resonant structures T1 / T2, input / output feeding structures and open-circuit branches arranged on a dielectric substrate; the two open-circuit branches are distributed in left-right axis symmetry, the open-circuit branches are connected with the input / output feeding structures, the input / output feeding structures are connected with the first resonant unit and the fourth resonant unit respectively; and the open-circuit branches are in L-shaped bending state, and a coupling relationship is formed between the open-circuit branches and the resonant structures T1 / T2. The application aims to improve the out-of-band suppression of the filter under the condition that the filter order and the size are unchanged.

This invention provides a thin-film piezoelectric acoustic wave resonator, its manufacturing method, and a filter. The thin-film piezoelectric acoustic wave resonator includes: a first substrate; an upper electrode, a piezoelectric sheet, and a lower electrode stacked sequentially from top to bottom on the upper surface of the first substrate; the upper electrode, the piezoelectric sheet, and the lower electrode have overlapping regions in a direction perpendicular to the surface of the piezoelectric sheet; in the overlapping regions, a first gap is provided between the piezoelectric sheet and the upper electrode, and a second gap is provided between the piezoelectric sheet and the lower electrode; an isolation cavity surrounds the outer periphery of the piezoelectric sheet, and at least one connecting bridge is provided between the piezoelectric sheet and the substrate; the first gap and the second gap are connected through the isolation cavity.

This application provides a 2.5D bridged packaging structure and a 2.5D bridged packaging process, relating to the field of semiconductor packaging technology. The process includes providing an adapter board; the adapter board has a first surface and a second surface disposed opposite to each other; forming a plurality of spaced first trenches on the first surface; forming a first wiring layer within the first trenches; forming second and third trenches on the second surface; forming a second dielectric layer and a second wiring layer within the second trenches, and forming a third dielectric layer and a third wiring layer within the third trenches, with a second metal layer disposed on the surface of the third dielectric layer; mounting a bridge chip; connecting the bridge chip to both the second and first metal layers; forming a heat dissipation trench on the side of the adapter board away from the third wiring layer; and mounting a heat sink in the heat dissipation trench. This process helps alleviate warpage, improves heat dissipation performance, and reduces leakage, short circuits, and overheating caused by parasitic capacitance and other phenomena.