The utility model discloses a kind of
chip top layer structures, comprising: multiple
chip modules, each
chip module includes multiple pins;And wiring unit, including multiple
signal lines for being connected with the pin of multiple chip modules, wherein, wiring unit includes first wiring area and second wiring area, logic
signal line,
noise signal line and
clock signal line in the multiple
signal lines are arranged in the first wiring area, sensitive signal line and quiet signal line in the multiple
signal lines are arranged in the second wiring area, first wiring area and second wiring area are isolated by continuous isolation band between it.This chip top layer structure of the utility model realizes the inhibition between
coupling noise of sensitive signal line and
noise signal line and
clock signal line and parasitic effect between signal line in
layout level, while significantly reduce wiring resource occupancy and design complexity.