Method and structure for controlled impedance wire bonds using co-dispensing of dielectric spacers

Abstract

A method (and structure) of making an electronic interconnection, includes, for a signal line to be interconnected, using a plurality of bonding wires configured to provide a controlled impedance effect.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention generally relates to wire bonding of devices to the next level of packaging or between devices within a package. More specifically, to improve wide bandwidth signal transmission, the parasitic inductance can be lowered and compensated with distributed capacitance by tightly spacing a plurality of bond wires and / or bond ribbons so that the resulting impedance can be controlled for wide bandwidth signal transmission. [0003] 2. Description of the Related Art [0004] Transition of signals between a device and the next level of packaging (e.g., a semiconductor device and package), or between devices is often achieved by using bond wires (also referred to herein as bonding wires). FIG. 1A shows a top view 100 and FIG. 1B shows a side view 101 of a typical round wire bonding technique. In this example, round wire 102 is bonded to pad 103 mounted on chip 104. SUMMARY OF THE INVENTION [0005] Bond wires c...

AI Technical Summary

Benefits of technology

[0008] In view of the foregoing exemplary problems, drawbacks, and disadvantages of the conventional methods, an exemplary feature of the present invention is to provide a structure and method for bonding an electronic connection in a chip transition so that high frequency parasitics in the signal transmission can be reduced.

[0009] It is another exemplary feature of the present invention to provide a technique in which only specific connections having wide bandwidth signals can be prepared to reduce high frequency parasitics.

[0011] In a second exemplary aspect of the present invention, described herein is a method of reducing high frequency parasitic effects in a chip transition by using the above-described method.

[0016] The present invention provides a technique in which product costs can be reduced without a sacrifice in electrical performance. Improved signal transmission at higher data rates permitted by this invention will allow lower cost bond wire technologies to be applied to digital systems with ever increasing clock frequencies. Alternatively, the lower cost bond wire system of the present invention could replace more expensive packaging configurations currently used for high speed digital systems.

Problems solved by technology

Although these solutions work, they are not applicable in all cases.

For example, these solutions are not efficient in the sense that the high frequency signals in the transition might involve only a few of the interconnections in the transition.

Therefore, the existing solutions become costly and inefficient to implement when only a minimal number of transition interconnections require special treatment for high frequency parasitic effects.

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