16results about How to "Reduce parasitic parameters" patented technology

The application discloses a single-phase full-bridge power module, comprising a substrate, a base island located on a first surface of the substrate, the base island comprising a first base island, a second base island and a third base island, a first power device, a second power device, a third power device and a fourth power device, the first power device and the second power device forming a first half-bridge unit, the third power device and the fourth power device forming a second half-bridge unit, the first half-bridge unit and the second half-bridge unit forming a single-phase full-bridge unit, the first power device and the third power device being located on the first base island, the second power device being located on the second base island, the fourth power device being located on the third base island, and the first base island semi-enclosing the second base island and the third base island. The single-phase full-bridge power module provided by the application adopts a reasonable layout to package power devices, reduces parasitic parameters, and improves the dynamic performance and loss of a circuit.

The invention discloses a silicon carbide intelligent power module with voltage and current dual-detection over-current protection, and relates to the technical field of semiconductors. In order to solve the problem that when an existing silicon-based intelligent power module (IPM) is matched with a silicon carbide metal-oxide-semiconductor field effect transistor, due to the fact that the over-current protection response speed is low, interference and false triggering are likely to happen, a dual over-current protection mechanism combining desaturation voltage detection and sub-current detection is adopted. And by mixing and integrating the silicon substrate and the silicon carbide power device, the performance requirements of different application scenes are considered. Three driving control chips, six IGBT chips, six fast recovery diode chips, one SiC MOSFET chip, two silicon carbide Schottky barrier diode chips and one patch sampling resistor are integrated in the module, and all the elements are packaged in the same insulation heat dissipation substrate and lead frame combined structure, so that high integration level, high reliability and fast overcurrent protection are realized; the method can be widely applied to the fields of household appliances, industrial control, new energy and the like.

The application discloses a gallium nitride soft switch high-voltage Buck voltage converter and belongs to the technical field of switching power supplies. The auxiliary soft switch link is introduced, the problem of large switching loss, high thermal stress, large voltage peak and high-frequency oscillation caused by the switching capacitor link in the traditional high-voltage Buck switching capacitor voltage converter is solved, the efficiency and reliability of the system are improved, further, the double-phase staggered parallel structure is introduced, the current output capacity of the power supply is improved, the application in a higher power scene can be realized, meanwhile, the gallium nitride transistor is adopted, compared with the traditional scheme, the switching frequency is improved, the passive element size is reduced, the PCB integration is improved, the system parasitic parameters are reduced, the dead time and duty cycle loss are reduced, and the system efficiency and power density are further improved.

The present application relates to a kind of vertical channel field effect transistor and its preparation method, belong to semiconductor device technical field.It includes: silicon oxide substrate, its one side is provided with high platform;Wherein, high platform each side is provided with multilayer film structure;First guide groove on the first side of multilayer film structure and first guide groove on the second side of adjacent multilayer film structure are communicated;First guide groove is perpendicular to silicon oxide substrate;Multiple first dielectric layer, is set to the surface of silicon oxide substrate;Wherein, first dielectric layer both sides are provided with second guide groove;Second guide groove is communicated with the nearest first guide groove;First guide groove and second guide groove are provided with nanowire;Source electrode, is set to the side of high platform away from silicon oxide substrate;Multiple gate electrode, each gate electrode is set to the third side of each multilayer film structure, and is connected with dielectric layer.The present application realizes single nanowire high-density multi-independent channel, improves structure utilization.

The application relates to the technical field of radio frequency microwave devices, in particular to a W-waveband wide-frequency RF MEMS multi-blade multi-pole switch which comprises a silicon substrate, a plurality of input / output ports and a MEMS cantilever beam switch unit, the MEMS cantilever beam switch unit is provided with a driving electrode, and the communication and disconnection of the radio frequency signal path between the corresponding input port and the output port can be controlled by applying voltage to the driving electrode. The application realizes the on-off of the radio frequency signal path by electrostatic driving control of the deformation of the cantilever beam, and the driving mode has the advantages of low power consumption, high speed and easy integration. Compared with the common single-blade structure, the application can realize more complex signal routing in a compact unit, improves the system integration and functional flexibility, realizes interference-free crossing by using the slot structure through the horizontal swing type structure and the vertical lifting type structure, significantly reduces the high-frequency parasitic effect, and ensures the transmission quality of the millimeter wave signal in the W waveband.

The invention discloses a super-junction integration method and a super-junction integrated chip, and belongs to the technical field of super-junction semiconductors, and the method comprises the steps: constructing a substrate layer; an integrated super-junction structure is formed on the substrate layer, the integrated super-junction structure defines an epitaxial layer and alternating P columns and N columns in the epitaxial layer, at least one isolation structure is arranged in the integrated super-junction structure, the isolation structure defines P beams, the P beams are located on the side, away from the substrate layer, in the epitaxial layer, and the bottoms of the P beams are connected with the corresponding P columns and N columns. The P beams and the P columns at the two sides enclose an isolation region at the top in the epitaxial layer; a super-junction MOS device and an isolation device are correspondingly formed on the integrated super-junction structure; the isolation region is constructed on the super junction structure and used for integrating the isolation device, the isolation device can be a low-voltage or medium-voltage control device, and integration of the super junction MOS chip and the control chip is achieved.

This invention relates to a flip-chip structure and underfill packaging method for miniaturized crystal oscillators. The structure includes a packaging substrate, a quartz crystal resonator, an oscillating IC chip, and a sealing cap. Both the resonator and the IC chip are flip-chip bonded to the substrate via conductive bumps, with the resonator bumps being higher than the IC chip bumps, forming a vibration gap. A low-modulus underfill adhesive layer is filled into the gap between the chip and the substrate to buffer stress and redistribute thermomechanical stress, ensuring the stability of the resonant frequency. The packaging method includes solder placement, chip mounting, reflow soldering, underfill adhesive injection and curing, and hermetically sealed packaging steps. This invention effectively suppresses frequency drift caused by temperature stress through the synergistic effect of the vibration gap design and the low-modulus adhesive layer, while achieving high integration, low electromagnetic interference, and high reliability in miniaturized crystal oscillator packaging through a fully flip-chip and sealed structure.

The application relates to the technical field of photoelectric communication, and provides a substrate, a TO-CAN assembly and a packaging method. The substrate is provided with a first conductive layer, the first conductive layer extends to the side surface of the substrate from the front surface of the substrate until the first conductive layer extends to the back surface of the substrate; a fourth conductive layer is arranged on a signal plate connected with the substrate, the fourth conductive layer and the first conductive layer are connected through a connecting agent to realize high-frequency signal line connection between the substrate and the signal plate. In the application, the high-frequency signal line connection is realized in the form of a dielectric transmission line. Compared with the prior art in which a row of parallel gold wires are used to realize high-frequency signal line connection, the process difficulty of the high-frequency signal line connection is reduced, the dependence on a gold wire bonding device is low, and the dielectric transmission line is used to realize the high-frequency signal line connection, so that the parasitic parameters in the high-frequency signal line are reduced.

This invention proposes a monolithically integrated microwave radiation system based on an optically triggered switch and its fabrication method, belonging to the field of high-power microwave technology. The system includes a driver wafer and a device wafer bonded together. The device wafer uses cubic boron nitride or hexagonal boron nitride as a substrate, on which a heterojunction optically triggered switch, a monolithic microwave integrated circuit, and a monitoring and protection module are integrated. The optically triggered switch is vertically integrated on the side of the monolithic microwave integrated circuit. Under the excitation of the optical pulse output from the driver wafer, it generates an electrical trigger signal, which is amplified by the monolithic microwave integrated circuit and outputs a microwave signal. This invention, through the synergistic design of an ultra-wide bandgap semiconductor substrate, a two-dimensional material heterojunction, three-dimensional integration technology, and full-dimensional on-chip monitoring, achieves chip integration from optical triggering, microwave amplification to intelligent protection on a nitride-based substrate, significantly improving power density, response speed, operating frequency, and reliability.

The invention discloses a grounding stacking integrated radio frequency front-end chip stacking structure and a preparation method thereof, and belongs to the technical field of radio frequency microsystems. Based on silicon-based packaging, radio frequency front-end chips including a power divider, a low-noise amplifier and a multifunctional chip are subjected to function division, and four-channel radio frequency chips are respectively subjected to silicon-based embedded packaging and are led out through silicon through holes (TSV). An upper layer chip packaging module and a lower layer chip packaging module which are used for packaging two channel radio frequency chips respectively are bonded and integrated in a back-to-back mode, and the radio frequency chips which are packaged differently on the upper layer and the lower layer are connected through TSV via holes. Fanout lead-out is carried out in a bottom layer radio frequency chip, so that high-density integrated stacking is realized. By the adoption of the integrated stacking structure, the packaging size can be greatly reduced, and compared with a traditional silicon-based embedded fan-out structure, the size can be further reduced, and the packaging weight is reduced.

The application discloses a high-side switch output negative voltage limiting circuit and method, and belongs to the technical field of electronic circuits. In order to solve the problem that the output end generates an excessively high negative voltage when a high-side switch drives an inductive load to be turned off, resulting in device breakdown, at least one Zener diode is connected in series between the gate of an NMOS power tube and the positive end of a power supply, wherein the cathode of the Zener diode is connected to the positive end of the power supply, and the anode is connected to the gate. When the gate voltage is lower than the difference between the positive end of the power supply by more than the total voltage stabilizing value of the Zener diode during turn-off, the Zener diode is reversely broken down, the gate voltage is clamped at a preset potential, the NMOS tube is turned on again, a discharge path from the source to the drain through the channel is formed, and thus the output negative voltage is limited within a safe range. The circuit is simple, low in cost, fast in response speed, high in reliability, and suitable for high-side driving of inductive loads in the fields of new energy vehicles and the like.

The invention discloses a packaging structure. The packaging structure comprises at least one rewiring layer; the conductive plug layer is electrically connected with the rewiring layer; the metal groove is located in the conductive plug layer, or the metal groove is formed by enclosing the conductive plug layer and one of the rewiring layers; the preprocessing chip is positioned in the metal groove; and at least one main chip which is in bonding connection with the preprocessing chip and the rewiring layer. The preprocessing chip is embedded into the metal groove, so that the packaging size can be obviously reduced. The heat generated by the preprocessing chip is directly conducted and dissipated by utilizing the heat conduction characteristic of the metal material, the heat dissipation bottleneck caused by traditional plastic package layer coating is broken through, the heat dissipation structure is suitable for chip integration scenes such as power devices with strict heat dissipation requirements, the heat management capability of the power devices is remarkably improved, stable and reliable operation of the preprocessing chip in a limited space is ensured, and the service life of the preprocessing chip is prolonged. And an effective solution considering both size optimization and thermal performance guarantee is provided for high-performance and high-integration-level system design.

The invention belongs to the field of motor driving and control, and particularly relates to a motor integrated motor driver based on thick film hybrid integration and chip binding. Comprising a motor body, a motor rear cover is arranged on one side of the motor body, a cavity is formed in the motor rear cover, and a thick film ceramic substrate is fixedly arranged in the cavity; the interconnection assembly is arranged on one side of the thick-film ceramic substrate and used for electric power intercommunication; a pouring sealant is arranged on one side of the motor rear cover, the motor rear cover is connected with the motor body through the pouring sealant and is directly bonded through a bare chip to be integrated with the thick film ceramic substrate, component packaging of a traditional driver and external cables between a PCB and the motor and the driver are eliminated, chip-level system integration is achieved, and the size is reduced compared with a traditional scheme. Meanwhile, due to encapsulation protection and no external connector arrangement, the fault hidden dangers such as electromagnetic interference and connector looseness are eradicated, and the vibration resistance, temperature and humidity resistance and operation reliability of the system are greatly improved.

This utility model relates to the field of power electronics technology and discloses a fully integrated intelligent power module, including a motor control IC chip, a driver IC chip, and a power MOSFET chip. The motor control IC chip, driver IC chip, and power MOSFET chip are integrated into the same package and connected by metal wire bonding. The PWM output pin of the motor control IC chip is connected to the input pin of the driver IC chip. The power MOSFET chip includes three PMOS transistors and three NMOS transistors, forming a three-phase bridge circuit structure. In this utility model, by integrating the MCU, driver IC chip, and power MOSFET chip into a single package and interconnecting them using internal metal wire bonding, the complex PCB traces such as external phase current sampling resistors found in traditional solutions are completely eliminated, resulting in a more streamlined external system and reduced system cost and layout complexity for the client.

The application discloses an air isolation opposite double PCB power supply structure, which splits power supply circuits into two parallel and opposite independent printed circuit boards according to function modules and strong and weak electric properties, forms an open pure air isolation gap between the boards, and realizes mechanical fixing and electrical interconnection across the gap through an insulating coated conductive support piece. The application completely separates strong and weak electric circuits from the physical layer, eliminates the substrate parasitic coupling interference of traditional multi-layer PCBs by using the low dielectric property of air, and simultaneously considers compactness and rationality of wiring, thereby significantly improving the power supply electromagnetic compatibility and operation stability, and being suitable for high-end customized purification power supply fields. The structure can be matched with a single-point RC coupling suspended star-shaped grounding to realize double-layer noise reduction of the whole machine.

Embodiments of the present application provide a wafer-level semiconductor structure and a preparation method. The wafer-level semiconductor structure comprises a wafer-level circuit layer; at least two power devices arranged on one side of the wafer-level circuit layer, the power devices comprising a high-side GaN device and a low-side GaN device; a control device arranged on the side of the wafer-level circuit layer on which the power devices are arranged; the wafer-level circuit layer is used to connect the control device and the power devices; along the thickness direction of the wafer-level semiconductor structure, the projection of the control device on the wafer-level circuit layer and the projection of the power devices on the wafer-level circuit layer do not overlap. The technical solution provided by the embodiments solves the problem that the existing packaging size is large, the current path is long, the parasitic parameter is large, and the signal quality of the packaging structure is affected.