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Method for manufacturing multi-slot PN junction capacitor with multi-electrode ultra-low inductance

A technology of low inductance and capacitors, applied in the field of making multi-slot PN junction capacitors with multi-electrode ultra-low inductance, can solve problems such as reducing parasitic inductance

Active Publication Date: 2011-07-06
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although it is practically impossible to completely eliminate the magnetic field introduced by the current, it can greatly reduce the parasitic inductance caused by the surface current, thereby greatly improving the performance of the capacitor

Method used

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  • Method for manufacturing multi-slot PN junction capacitor with multi-electrode ultra-low inductance
  • Method for manufacturing multi-slot PN junction capacitor with multi-electrode ultra-low inductance
  • Method for manufacturing multi-slot PN junction capacitor with multi-electrode ultra-low inductance

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Embodiment Construction

[0068] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0069] Generally speaking, an ideal capacitor that can be used for high frequency has the characteristics of low impedance, and the smaller the impedance value, the better the high frequency decoupling performance. Impedance is related to capacitance and inductance, and their relationship is given in Formula 1. From the following formula, we can see that increasing capacitance will reduce impedance, and capacitance can be increased by adding capacitors in series, but increasing the number of capacitors Requires more real estate on the integrated circuit board and increases costs for manufacturers and consumers.

[0070] Z = 1 jωC + jωL

[0071] Am...

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Abstract

The invention discloses a method for manufacturing a multi-slot PN junction capacitor with multi-electrode ultra-low inductance. Through a series of theoretical argumentation and assumption, the original semiconductor PN junction capacitor is improved, so that the improved capacitor has the characteristics of simple structure, large capacitance density, small parasitic parameter, simple manufacturing process and the like, and particularly can realize great reduction of series inductance to ensure that the capacitor works in a higher frequency range. The capacitor can be widely applied to decoupling, filtering, matching, preventing static and surge and the like in the high-frequency high-speed power electronic system.

Description

technical field [0001] The invention relates to the technical field of capacitor manufacturing, in particular to a method for manufacturing a multi-slot PN junction capacitor with multi-electrode ultra-low inductance. parasitic inductance for the purpose of increasing the operating frequency of the capacitor. Background technique [0002] As the operating frequency of integrated circuits is getting higher and faster, the noise problem of the circuit power supply network in the electronic system is becoming more and more serious, which will bring serious harm to the entire circuit, for example, due to the power supply network The existence of the inductance in the power supply is impossible to respond in time, so that the local waveform is deformed and the signal integrity is damaged. [0003] In addition, when the circuit is in a transient working state, an unstable pulse often passes through the integrated circuit, causing the circuit to be in an unstable state such as ove...

Claims

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Application Information

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IPC IPC(8): H01L21/78H01L21/02H01L21/28
Inventor 万里兮吕壵王惠娟
Owner NAT CENT FOR ADVANCED PACKAGING
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