Field-effect transistor and manufacturing method thereof

Abstract

The embodiment of the invention provides a field-effect transistor and a manufacturing method thereof and relates to the technical field of semiconductors. Parasitic parameters of the field-effect transistor can be reduced to improve the reliability of the field-effect transistor. The method comprises the steps as follows: a support structure with superlattice characteristics is formed on a semiconductor substrate; the support structure comprises first semiconductor material layers and second semiconductor material layers, which are alternately arranged; isolating layers are arranged at two sides of the support structure; a false gate structure covering the support structure is formed along the juncture of the isolating layers and the support structure; the length of the false gate structure in a gate length direction is smaller than those of the first semiconductor material layers in the gate length direction; areas except for sacrificial layers in the first semiconductor material layers are removed along the gate length direction to form insulating grooves; the dielectric constants of mediums filled into the insulating grooves are smaller than those of the first semiconductor material layers; and a source and a drain are formed in preset source region and drain region along the gate length direction and the source and the drain are isolated from the sacrificial layers through the insulating grooves.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of semiconductors, in particular to a field effect transistor and a manufacturing method thereof. Background technique [0002] At present, when making a field-effect transistor (Field-Effect Transistor, FET), take a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field-Effect Transistor) as an example, such as figure 1 As shown, the first semiconductor material layer 11 and the second semiconductor material layer 12 are generally stacked in sequence in the channel 100, as well as the dummy gate structure 13 located on the second semiconductor material layer 12, and the source and drain regions on both sides of the channel 100 After the source electrode 14 and the drain electrode 15 are formed by the doping process, the second semiconductor material layer 12 and the dummy gate structure 13 can be removed by an etching process, and then, as figure 2...

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Problems solved by technology

[0003] In the above manufacturing method, when the source electrode 14 and the drain electrode 15 are formed by a doping process, as figure 1 As shown, the source 14 (or drain 15) is in direct contact with the first semiconductor material layer 11 and the second semiconductor material layer 12 in the channel 100, so that a part of the impurity atoms diffuse to the second semiconductor material layer 12 and the first semiconductor material layer 12. The extension (Extension) region 22 is formed in the material layer 11, resulting in an increase in the parasitic parameters such as the parasitic capacitance of the subsequently formed MOSFET, and the GIDL (gated-induced drain leakage) of the MOSFET will also increase, which seriously affects the MOSFET. performance and reliability

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