494 results about "Netlist" patented technology

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

The invention discloses a PCB component layout method, device and equipment based on a multi-modal large model, and relates to the technical field of electronic design automation, the method comprises the following steps: carrying out quality screening on a plurality of PCB design files which have been laid out to obtain a qualified design file set; constructing a serialized training sample set based on the qualified design file set; each training sample sequence comprises a plurality of training samples arranged according to a layout logic sequence; each training sample comprises multi-modal data representing a current layout state and a real position coordinate of a next component to be laid out; based on the serialized training sample set, training the open-source multi-modal large model to obtain a PCB component layout model; and iteratively generating a layout file of the target PCB based on the netlist file of the target PCB and the PCB component layout model. The method is high in generalization capability and low in cost based on the PCB component layout model trained by the layout data, and can realize rapid layout of components of a new PCB.

The invention discloses a clock domain crossing circuit timing sequence closed-loop optimization method and system, and relates to the technical field of integrated circuit design, and the method comprises the steps: reading a circuit netlist and timing sequence constraints, recognizing a converged path, and carrying out the clustering analysis to form a plurality of path groups; establishing a time sequence analysis model, and dynamically calculating the maximum delay constraint of the data signal in the path group; matching and executing at least one time sequence optimization strategy for each path group; and carrying out closed-loop time sequence verification, retaining a legacy path set which does not meet the constraint, and repeatedly executing the time sequence optimization strategy until a convergence condition is reached or the maximum preset number of iterations is reached. According to the method disclosed by the invention, the cross-domain path needing to be optimized in the DMUX structure can be accurately positioned without manual intervention, so that the path identification efficiency is improved, constraint omission or grouping deviation caused by manual operation is avoided, design defects are reduced from the source, and the design reliability of a chip is improved.

The invention discloses an identification and verification method and system for a secondary drawing of a transformer substation, and belongs to the technical field of image identification, and the method specifically comprises the steps: analyzing a CAD vector diagram, obtaining four-corner references and pixel coordinates of a scanning graph, building initial mapping of pixels and engineering millimeter coordinates by taking an engineering millimeter coordinate system as a reference, and generating a unified intermediate representation model; constructing a terminal strip parameterization template based on the vector anchor point set and the visual anchor point set; a composite deformation field is calculated through vector-bitmap-vector closed-loop rendering calibration, terminal row alignment and terminal sequence binding are completed in the composite deformation field, and a terminal pixel position-terminal sequence-engineering millimeter coordinate consistent mapping table is formed; comparing the topological netlist to obtain an electrical node corresponding table; and performing source decomposition on the terminal position residual error based on the composite deformation field and generating a self-adaptive tolerance band, and finally executing wiring verification by taking the self-adaptive tolerance band, the electrical connectivity and the serial number consistency as criteria and outputting a verification report.

The invention provides a power consumption feature extraction method and system for a static random access memory standard cell library, electronic equipment and a storage medium, and the method comprises the steps: S1, reading a standard cell model file, a standard cell netlist and a standard cell time sequence path of a static random access memory, and constructing and generating an excitation waveform description file; s2, establishing a simulation file of the static random access memory standard unit, simulating the static random access memory standard unit, and respectively obtaining electrical characteristic data of an input pin and an output pin of the static random access memory standard unit; s3, analyzing the electrical characteristic data of the static random access memory standard unit, and obtaining a short-circuit power consumption time sequence path and a switching power consumption time sequence path existing in the static random access memory standard unit; and S4, respectively calculating power consumption values of each switching power consumption time sequence path and each short-circuit power consumption time sequence path. According to the method, the power consumption characteristics of the SRAM standard cell are extracted in the design stage of the standard cell library, and the precision and efficiency of power consumption analysis can be improved.

The invention discloses an FPGA (Field Programmable Gate Array) netlist-level hardware Trojan horse detection method based on a large language model, and relates to the technical field of integrated circuit safety and hardware Trojan horse detection, and the method comprises the following steps: constructing an original FPGA netlist into a text attribute graph containing textualized attributes, generating a path text sequence through bidirectional random walk, and carrying out two-way random walk on the path text sequence; constructing a corpus to pre-train a large language model; then, delimiting a local neighborhood by taking each node as a center, generating a path text set, extracting semantic vector representation of the path text set by utilizing a pre-training model, and further constructing a node-level training sample set; on the basis, supervised fine tuning is carried out by combining a classifier and CB-Focal Loss, and a final model is obtained; in the reasoning stage, representation construction and discrimination are carried out on nodes to be detected, and node-level hardware Trojan horse detection is achieved. According to the method, circuit topology and semantic information can be reserved at the same time, node-level hardware Trojan positioning is achieved, the detection precision and generalization ability are improved, and the automation degree is improved.

The invention discloses a power consumption prediction and optimization method in chip design, and relates to the technical field of chip design and energy efficiency optimizing.The method comprises the steps that a circuit netlist is analyzed, functional blocks are divided, and an association diagram is constructed; generating a typical working load containing a transient peak value and a steady-state interval based on actual application; calculating dynamic and static power consumption, and considering temperature sensitive leakage current; constructing a three-dimensional thermal model, gridding a chip, solving a heat conduction equation, and outputting temperature field distribution; three-level optimization of clock gating, DVFS and data flow reconstruction is carried out on the overtemperature area; the optimized parameters are imported into a simulation tool to verify the effect, and robustness is confirmed through Monte Carlo simulation. According to the method, the power consumption prediction precision and optimization pertinence are improved, the temperature distribution uniformity is improved, the power consumption and performance are balanced, the number of design iterations is reduced, and the chip reliability and energy efficiency ratio are enhanced.

A dynamic grid allocation system for power distribution in the development of integrated circuits in the sub-five-nanometer range, wherein the system comprises the following: a placement processor unit configured to receive a synthesized netlist comprising a variety of standard cells and macros, each associated with switching activity data derived from simulation or synthesis activity profiles, and to generate a spatial cell placement arrangement by grouping cells into microzones based on activity correlation, time sensitivity, and connection proximity; a power density calculation unit coupled to the placement processor unit and configured to calculate the local power density and instantaneous current demand for each microzone based on the spatial distribution of switching operations, capacity load, and effective switching frequencies; a dynamic network generation unit coupled to the power density calculation unit and configured to generate a multilayer power distribution network with variable network topology, where the width, spacing, via density and metal layer assignment of the power network are adaptively determined as continuous functions of the localized power density and power demand calculated for each microzone; a topology control processor configured to monitor voltage drop and electromigration data obtained from signoff analyses or predictive models in real time and dynamically adjust the power grid topology parameters to ensure compliance with predefined reliability thresholds for voltage drop and electromigration; a predictive current modeling unit configured to receive historical switching and voltage data, train a predictive model for transient current peaks, and provide predictive power boost instructions to the dynamic grid generation unit before power integrity violations occur; and A feedback synchronization controller is communicatively connected to the placement processor unit and the topology control processor, whereby the feedback synchronization controller continuously exchanges updated power density information and placement constraints, so that cell placement and network topology adapt together in real time, thereby minimizing routing congestion, ensuring a uniform voltage distribution, and guaranteeing compliance with electromigration and IR drop regulations under various activity conditions.

The invention relates to the technical field of circuit performance testing, in particular to an integrated circuit aging effect prediction and circuit life reliability evaluation method. The specific implementation process comprises the following steps: acquiring a physical design netlist and a basic process library, analyzing a test load into transient upset density, and generating a time-varying excitation flow in combination with layout geometric information; dividing an aging sensitive domain by using a double-track aging difference mechanism, and performing integration processing on the time-varying excitation flow to quantify a circuit aging parameter; performing full-chip time sequence simulation on the circuit aging parameter, and predicting a performance erosion index; and calculating a dynamic redundancy retraction vector, adjusting the reduction amplitude of the guard band, and converging the evaluation in a target design interval. According to the method, the time-varying excitation flow and the sensitivity partition topology are utilized, the multi-physical field coupling effect under the dynamic load is effectively captured, the problem of prediction distortion caused by static hypothesis is solved, and the balance of the chip area, the power consumption and the reliability service life is achieved through the dynamic redundancy retraction vector optimization design protection band.

The invention belongs to the field of electronic design automation, and discloses a multi-agent radio frequency circuit netlist generation method and system based on a large language model, and the method comprises the steps: preparing a data set, and constructing a knowledge base; the method comprises the following steps: receiving and analyzing a natural language demand of a user, combining a cue word project and an RAG mechanism, carrying out chained reasoning, introducing a radio frequency design rule, and converting the information into structured parameter information; combining RAG knowledge base retrieval and new topology generation, and fusing PDK process constraints to obtain candidate topologies and a simulation netlist; a simulation tool is called to execute parameter analysis, iterative optimization is conducted on parameters in combination with a closed-loop feedback mechanism, and a final netlist meeting user requirements is obtained. Automatic decomposition, parallel cooperation and high-speed iteration of design tasks are achieved through multi-agent cooperation and in combination with the radio frequency knowledge graph and the RAG; introducing physical constraints to enable the generated topological structure and parameters to meet the physical constraints; and a closed-loop simulation feedback mechanism is fused, so that the dependence on manpower is reduced.

The invention relates to the technical field of chip test vector intelligent generation scheme design, in particular to a failure analysis-oriented chip test vector intelligent generation method and system. The method comprises the following steps: acquiring a chip design netlist, a fault model and a known failure mode; analyzing potential design or manufacturing defects based on the information; and according to an analysis result, a targeted test vector capable of effectively exciting and isolating potential defects is automatically generated. The system comprises a corresponding input module, an analysis module and a generation module. According to the method, the design information, the fault model and the historical failure mode are intelligently fused, automatic and precise generation of the test vector is achieved, and the defects that a traditional method is insufficient in test coverage rate, low in failure positioning efficiency and limited in automation degree are overcome. According to the method, the test completeness and the failure analysis efficiency can be remarkably improved, the dependence on artificial experience is reduced, and an efficient technical means is provided for guaranteeing the reliability of the chip.

The invention relates to the technical field of strategy optimization, in particular to an ASIC (Application Specific Integrated Circuit) layout optimization method based on hybrid shaping programming, which comprises the following steps of: analyzing a circuit netlist, and establishing a signal path physical model containing static topological connectivity; a candidate layout scheme is generated based on the model, and layout state data describing the state of the candidate layout scheme is generated through physical effect simulation; based on the layout state data, calculating a signal processing performance index and a wiring cost value, and generating a group of dynamic shaping constraints for guiding subsequent layout according to the index and the cost value, the dynamic shaping constraints being quantitative adjustment of a path congestion perception graph in a signal path physical model; and updating the model through the constraint, evaluating the stability of a Pareto optimal boundary formed by the performance index and the cost value so as to judge convergence, and finally outputting a layout scheme associated with a stable state. According to the method, dynamic shaping constraints are generated through a strategy optimization algorithm, and global collaborative optimization of multiple targets such as time sequence and wiring performance is achieved.

The invention provides a high-speed communication chip macro placement method based on reinforcement learning. The high-speed communication chip macro placement method comprises the following steps: extracting static features and dynamic features from a netlist; fusing the static features and the dynamic features, and inputting the fused static features and dynamic features into a shared graph neural network based on a reinforcement learning architecture; the strategy network outputs action probability distribution according to the current environment state, and the legal action with the maximum probability value is selected for execution; the value network outputs accumulated value estimation of the current environment state; after the action is executed, instant rewards and next state information are obtained, and the strategy network and the value network are updated according to the obtained information; and constructing a multi-objective optimization function based on macro placement constraint. According to the method, through deep fusion of reinforcement learning and constraint modeling, the automation level and design quality of macro cell placement are improved, and therefore the requirements of a high-speed communication chip for low power consumption, high performance and compact area are met.

The invention relates to the technical field of field programmable gate array physical optimization, and discloses a field programmable gate array multi-resource division method, device and equipment, the method comprises the following steps: generating a hypergraph comprising vertexes and hyperedges based on a netlist, the hypergraph comprising one or more types of resources; carrying out first partition division on the hypergraph, and carrying out multi-level vertex combination; partitioning the hypergraph of the maximum merging hierarchy, dividing vertexes in the maximum merging hierarchy to each partition, and carrying out the following processing on the hypergraph of each hierarchy from the maximum merging hierarchy to the minimum merging hierarchy: moving a first vertex between the partitions in the target merging hierarchy, and meeting the multi-resource constraint of the partitions in the moving process; splitting the vertexes in the target merging hierarchy into the vertexes of the previous hierarchy of the target merging hierarchy; until a first hypergraph is obtained; moving a first vertex in the first hypergraph to obtain a first partitioning result; and carrying out partition division again until the position of each functional module is determined.

The invention discloses a circuit netlist conversion method, a circuit netlist conversion control method and a circuit netlist conversion control device. The method comprises the steps that a circuit netlist is obtained and analyzed, netlist intermediate data are constructed, the netlist intermediate data comprise netlist element data and netlist topological data, the netlist element data are used for representing electrical parameters of circuit elements, and the netlist topological data are used for representing the connection relation of the circuit elements; converting the netlist element data into schematic diagram element data according to an element configuration rule of the target electronic design automation tool; determining position information of the circuit elements and routing information between the circuit elements based on the netlist topological data, and generating schematic diagram layout data adaptive to the target electronic design automation tool; and according to the schematic diagram element data and the schematic diagram layout data, generating a circuit schematic diagram file through the target electronic design automation tool. The circuit netlist conversion method has the technical effect of improving the circuit netlist conversion efficiency.

The invention provides an FPGA lookup table merging and decomposing method and device, equipment and a medium, and relates to the technical field of integrated circuit netlist optimization. The method comprises the following steps: acquiring a mapped LUT network of an FPGA; then, candidate pair identification is carried out on the LUT network, conflict-free LUT candidate pairs with the optimal weight are selected to be merged, an LUT connection relation graph is constructed after merging, and a key path is identified; on the basis of the LUT connection relation graph, decomposing the LUT on a non-critical path into smaller cascaded LUT units according to a LUT priority sequence; and dynamically updating the network topology structure and time sequence information of the LUT connection relation graph after each decomposition to complete optimization of the FPGA netlist. According to the method, the number of LUTs can be remarkably reduced and the resource utilization rate of the FPGA can be improved on the premise of ensuring that the delay of the critical path is not changed.

The invention relates to the technical field of digital logic design, and discloses a hierarchical incremental logic synthesis method and device for multi-module design, and the method comprises the steps: building a node mapping relation between an original HDL hierarchical structure and an original network surface layer substructure; comparing the modified HDL hierarchical structure with the original HDL hierarchical structure, and identifying a target module which is changed; determining a module range, and constructing an HDL sub-design for the module range; performing logic synthesis on each HDL sub-design to generate a local department-level netlist; and integrating the local department-level netlist into the original comprehensive netlist to generate a comprehensive netlist after incremental updating. According to the method, the node mapping relation between the original HDL hierarchical structure and the original net surface layer substructure is established and utilized, so that the cross-boundary optimization behavior of the synthesizer is accurately tracked and compatible, the problem that the original structure is inconsistent with the net list structure is fundamentally solved, and the function correctness of incremental synthesis is ensured.

The invention discloses an address allocation method and electronic equipment, and relates to the technical field of address allocation, and the method comprises the steps: analyzing an electrical connection netlist, determining a plurality of link entities in a target link, constructing a link topology tree, and generating an address allocation rule set; determining logical addresses of a plurality of link entities; determining actual configuration addresses of a plurality of link entities; performing address conflict verification on the plurality of link entities based on the actually configured addresses and the logic addresses, and judging the link entities as address conflict entities if the link entities do not pass the address conflict verification; a set of modifiable variables and a set of minimum cost modification solutions are determined based on address information for the address conflicting entities. According to the method, the address can be automatically planned and allocated based on the electrical connection netlist, and conflict repair after address conflict verification is realized, so that the problems of insufficient utilization of address space, difficulty in timely discovery of path conflicts, low conflict positioning and repair efficiency and the like in related technologies are solved.

Some aspects utilize an iterative process to synthesis a logic network within an ASIC using lookup table (LUT) optimization techniques. The logic network may be represented by an And-Inverter graph (AIG), as described in more detail below. On each iteration, the current AIG representation of the logic network is mapped to a network of k-LUTs. A k-LUT is a lookup table that can represent any function of k variables. This network may then be improved using LUT optimization techniques. The improved network of k-LUTs is decomposed into a trial AIG representation, which may be further improved for example by applying Boolean-based optimization techniques. The current AIG representation may then be updated in accordance with the quality of the trial AIG representation produced by the current iteration. The final AIG representation from the iterations is synthesized to a netlist of standard cells.

The invention discloses an automatic layout method of a filter chip layout and computer equipment. The method comprises the following steps: reading circuit netlist information of a filter; searching a shortest signal path between input and output of the circuit as a main path, and extracting all circuit elements on the main path; performing initial layout on elements on the main path, and storing coordinates of the elements in a coordinate dictionary; an improved force steering algorithm is adopted to carry out layout on the remaining elements, and coordinates of the elements are stored in a coordinate dictionary; judging whether geometric overlap exists among the elements, if yes, eliminating the geometric overlap through adjustment, and meanwhile, ensuring that the connection relationship of the elements corresponds to the netlist; adding an input / output port and adding a scribing channel at the edge of the chip; and performing design rule check and comparison check of the layout and the schematic diagram, if the check is passed, outputting the layout, otherwise, returning to perform overlap detection and adjustment. The design efficiency can be improved, human errors are reduced, and the circuit performance is optimized.

A method for detecting non-convergence error in a transient circuit simulation wherein a circuit netlist and control statements associated with a circuit for the transient circuit simulation are received. A transient circuit simulation is performed responsive to a time point. Whether a non-convergence error has occurred during transient circuit simulation is determined. A transient debug mode is actuated responsive to determination of occurrence of the non-convergence error. The steps of performing the transient circuit simulation and determining whether a non-convergence error has occurred are repeated after actuation of the transient debug mode. Results of the transient circuit simulation are provided responsive to a determination of non-occurrence of a non-convergence error.

The invention discloses an ECO time sequence optimization method and device based on logic rewiring, and belongs to the technical field of ECO. The method comprises the following steps: receiving a design netlist and a function patch netlist; before introducing the physical layout information, performing logic-level rewiring optimization on the function patch netlist; integrating the optimized patch netlist with the overall design netlist and introducing physical layout information; identifying a time sequence critical path containing the patch module; carrying out rewiring optimization of physical perception on the premise of considering physical layout constraints; and verifying whether the optimization scheme meets a time sequence requirement or not. Through the two-stage rewiring optimization strategy, the ECO time sequence optimization capability is remarkably improved, the area and power consumption overhead are reduced, the time sequence convergence success rate is improved, and it is ensured that the optimization scheme can be physically achieved.

The invention discloses a critical path optimization method and device and an optimization strategy determination method and device in logic synthesis. The optimization method comprises the following steps: identifying an initial key path from a comprehensive result corresponding to an RTL code, deleting a buffer tree on the path, and recording the path as a target key path; identifying abnormal path segments from all the target key paths, grouping all loads corresponding to the target signal lines on each abnormal path segment according to the obtained actual fan-out number on each abnormal path segment, copying the drivers of the target signal lines according to a copying strategy, and connecting the copied drivers with the load groups based on a preset connection strategy; and circularly executing optimization operation on all the abnormal path segments, and obtaining an optimized gate-level netlist after the path optimization operation on all the target key paths is completed. According to the method, the key path can be accurately identified, the comprehensive result is directly optimized, repeated modification and debugging on the RTL level are effectively avoided, and the efficiency of the whole design process is improved.

The invention discloses a chip circuit state self-diagnosis method based on a graph neural network, and the method comprises the following steps: obtaining a chip netlist, layout and process information, collecting multi-source state data to construct a multi-domain coupling graph, and generating a multi-scale calculation tree based on a critical path; standardizing key node noise data, extracting noise fingerprints, constructing a noise consistency graph, and aligning the noise consistency graph with the multi-domain coupling graph to form node features; inputting the multi-scale calculation tree into an improved GFT model, and generating unified graph representation through structure token coding and feature fusion; constructing a multi-scale transition graph neural network, simulating multi-domain state propagation and outputting an abnormal score; anti-fact operation and reversible disturbance are applied to the high abnormal score nodes to generate an anti-fact state diagram, and a fault causal chain is constructed; and performing topological variation inversion based on the abnormal score and the causal chain to obtain a fault position, a fault type and a fault degradation trend. According to the invention, high-precision explainable chip fault self-diagnosis can be realized.

The invention discloses an SOC prototype verification logic division method and system based on resource constraints. The method comprises the steps that a to-be-verified SOC prototype is split into modules meeting the resource constraints of an FPGA; the split modules are tried to be combined in pairs to form modules meeting the resource constraint of the FPGA; 1 is added to the loop variable i of the finally obtained module according to the sequence of the number of the external connecting lines from large to small, and the FPGAs are distributed in the multi-FPGA verification platform; integrating the modules distributed with the FPGAs to generate a netlist file; and converting the netlist file into a bit stream file and downloading the bit stream file into the distributed FPGA. According to the method, the process of mapping SOC design to multiple FPGAs is achieved, logic division is rapidly achieved for the design, rapid time sequence convergence is achieved through reasonable arrangement of resources, the FPGA chip resource utilization rate is increased, and time sequence optimization iteration of a net list after integration is reduced.

The invention provides a cross-level error tracking and repairing method and system for a stacked chip system, and the method comprises the steps: marking a register, a signal or a state machine state when an RTL code is written during chip design, and keeping a first label written during the writing of the RTL code in a gate-level netlist when a comprehensive tool generates the RTL code into the gate-level netlist; when the gate-level netlist is converted into the physical layout in the physical implementation and layout wiring process, label information of marked objects on the gate-level netlist is reserved on the physical layout when the physical layout is generated; in the integrated design process of the chip, a new second label is injected for the interconnection channel in a packaging design tool; in the simulation analysis process, when it is found that a chip simulation result is abnormal, cross-level tracking and repairing are conducted on the position of an error through static time sequence analysis and power consumption analysis. The invention also provides a system for realizing the method. According to the method, error codes can be quickly positioned and repaired.

The invention provides a chip layout method and device based on a reinforcement learning network, equipment and a medium, and the method comprises the steps: determining layout evaluation data of a current layout scheme, solving a comprehensive evaluation model through employing a boundary intersection algorithm for the current layout scheme, and obtaining a layout evaluation compromise solution, and according to the difference between the layout evaluation data and the reference layout evaluation data, guiding the reinforcement learning network to determine a target unit which is not laid out and a corresponding layout strategy according to the circuit netlist characteristics, and then adding the target unit to the current layout scheme according to the layout strategy until all the units are laid out. According to the embodiment of the invention, the balance among a plurality of mutually constrained layout evaluation indexes (such as area, time delay, power consumption and the like) in the chip layout process can be realized.

The present application discloses a system and a method for performing a scan chain ECO, the method includes: receiving an original netlist input by a user as first input information, the original netlist contains original scan chain information; receiving a register modification list and a scan DEF file input by the user as second input information, wherein the register modification list is configured to indicate register information to be up-chained and / or register information to be down-chained; modifying the original netlist based on the first input information and the second input information, to complete up-chaining and / or down-chaining of a list of registers in the second input information to obtain a modified scan chain netlist; and receiving the modified scan chain netlist and returning the modified scan chain netlist to the user.

The invention relates to the technical field of electronic design automation and artificial intelligence, in particular to an AI-assisted multi-target PCB automatic design system and method, and the system comprises a user interface layer which is used for a user to input a request through a Web-based interface; the natural language analysis module is used for processing the request and generating a JSON (JavaScript Object Notation) containing function requirements; the device selection module queries an internal device database and suggests an ESP32-C3 MCU (Microprogrammed Control Unit), a compatible relay and a support circuit; the circuit generation module is used for creating a netlist and a schematic diagram file and comprises an MCU (Microprogrammed Control Unit), a relay driver and related passive elements; the layout optimization module runs a multi-target algorithm and is integrated with PCB design software; experimental verification shows that compared with a traditional one-way process, by means of the method, the requirement interpretation accuracy can be improved to 94.2% from 76.3%, the design intention preservation rate is improved to 89.5% from 42.7%, the requirement change adaptation time is shortened to 2.1 h from 8.4 h on average, and the requirement interpretation efficiency and accuracy are improved.