89 results about "Netlist" patented technology

This invention discloses a method for predicting standard cell transistor placement sequences based on a Transformer model, an electronic device, and a storage medium. Step 1: Construct training samples based on standard cell netlist information and corresponding existing placement results; train the placement model using these training samples to obtain a trained placement model. Step 2: Obtain the standard cell netlist information to be placed and the current placement MOS sequence, and construct the feature encoding of the current state. Step 3: Input the feature encoding of the current state and the decision space into the placement model to obtain the next standard cell transistor to be placed, and place it. Step 4: Repeat steps 2-3 until all standard cell transistors have been placed. This invention improves the efficiency, accuracy, and versatility of placement, while reducing design time and cost.

A novel data generation system is provided, which includes a first data processing device having a function of generating a netlist by converting a hardware description language into graph-structured data and performing arithmetic processing based on Monte Carlo tree search, a second data processing device having a function of converting the graph-structured data into matrix data using a graph neural network, and a third data processing device including a transformer model and generating a first command in accordance with an input token sequence. The first data processing device has a function of generating a random number, and as a command executed in the Monte Carlo tree search, the first command or a second command selected using a calculation formula of action selection is selected in accordance with a magnitude relationship between the random number and a specified value.

This application relates to the field of integrated circuit design automation technology, and provides a method and system for verifying analog circuit structures based on graph neural networks. The method includes: converting a SPICE netlist into a graph structure representation, where nodes correspond to devices and edges correspond to electrical connections, and extracting feature vectors containing device type, parameters, functional roles, connection types, and signal directions; encoding the circuit diagram using a graph attention network to obtain node embeddings and graph embeddings; performing multi-task prediction based on the embedding results, including node classification, graph classification, structure scoring, and error localization; and finally generating a verification report containing an error list, location information, and repair suggestions. This application achieves automatic detection and precise localization of errors in analog circuit structures, improving detection accuracy by a significant margin and possessing strong generalization capabilities.

The embodiment of the present disclosure provides an EDA netlist comparison method, system and computer storage medium, the EDA netlist comparison method comprises: the native file contained in the new version netlist file and the old version netlist file obtained is respectively analyzed and processed, new version decoding file and old version decoding file are obtained, each native file is parsed into a unified data structure, wherein the new version decoding file and the old version decoding file both include network set and device set;The network set and the device set corresponding to the new version decoding file and the old version decoding file are compared respectively, and a comparison result is obtained;The comparison result is used to identify the network change type and the device change type of the new version netlist file and the old version netlist file;Based on the device change type, the multi-attribute change intelligent merging is carried out for each device respectively, and a merging result is obtained;According to the comparison result and the merging result, a comparison report is generated.

The application discloses an automatic layout method of an analog integrated circuit and related devices, and the method comprises the following steps: obtaining circuit netlist information, device library information and layout canvas size data corresponding to an analog integrated circuit to be laid out; constructing a circuit hierarchical structure model based on the circuit netlist information, and performing sorting processing on the layout sequence of devices and sub-circuits through the circuit connection relationship in the circuit hierarchical structure model to form a corresponding layout sequence; performing layout processing on the current device and sub-circuit to be placed according to the layout sequence to obtain layout state information; generating a placement strategy of the current device and sub-circuit to be placed based on the layout state information and an available layout region set, and placing the current device and sub-circuit to be placed in the selected layout region according to the placement strategy until the top-level circuit layout is completed, so as to complete the automatic layout of the analog integrated circuit to be laid out. In the embodiment of the application, the layout quality and design efficiency are improved.

Providing a new data generation system. [Solution] The system includes a first data processing device that has the function of converting a hardware description language into graph structure data and generating a netlist by performing calculations based on Monte Carlo tree search; a second data processing device that has the function of converting the graph structure data into matrix data based on a graph neural network; and a third data processing device that has a transformer model and generates a first command according to the input token sequence. The first data processing device has the function of generating random numbers, and the command to be executed in Monte Carlo tree search is selected based on the relationship between the random number and a specified value, either as a first command or as a second command selected based on a calculation formula for action selection.

Method and system are provided for performing physical-aware logic synthesis. A synthesis environment receives an RTL design, associated design constraints, and one or more design flow and physical design parameter settings. The RTL design is synthesized into a gate-level netlist while incorporating physical design considerations. A scoring result is computed from a logic synthesis result including the synthesized gate-level netlist to provide a quantitative measure of design quality. In certain aspects, the scoring result includes a scattering metric that evaluates placement density of standard cell instances, rankings across multiple modules, PPA results, and runtime prediction estimates. In further aspects, the design parameters are iteratively adjusted using artificial intelligence, reinforcement learning, or machine learning agents to optimize design quality. The invention enables improved integration of logical and physical design stages at advanced semiconductor process nodes.

The application provides a three-mode redundant circuit netlist compiling method and device based on state machine conversion, belongs to the technical field of anti-radiation integrated circuit netlist compiling processing, and comprises the following steps: generating a netlist ASCII text stream and a keyword-regular set by inputting core source data suitable for an anti-radiation scene, triggering a lexical analyzer, forming an ordered lexical unit sequence through lexical analysis, constructing a state transition graph and checking the state transition graph, integrating the graph and a fragment, extracting a syntax tree, converting the syntax tree into a flow graph data structure, finally generating an IR intermediate representation mapped with SoC hardware, and outputting the IR intermediate representation. The three-mode redundant circuit netlist compiling method and device based on state machine conversion are used, so that the problems of low recognition efficiency, large cost and easy deletion of redundant logic in the process of processing a three-mode redundant circuit netlist by a traditional hardware compiler are solved.

A verification method for a layout of an integrated circuit performed by a computer device includes comparing a first netlist corresponding to a schematic diagram of the integrated circuit and a second netlist corresponding to a first layout of the integrated circuit, generating a second layout by applying a pre-input retarget rule to the first layout in response to determining that the first netlist and the second netlist correspond to each other, generating a first text file, including coordinate data for each of layers included in the first layout, from the first layout, generating a second text file, including coordinate data for each of layers included in the second layout, from the second layout, and outputting verification information indicating whether a difference between the first layout and the second layout corresponds to pre-stored feature data, based on the first text file and the second text file.

The embodiment of the invention discloses a radio frequency circuit intelligent generation and precision tuning method and device, equipment and a medium. The method comprises the steps that radio frequency circuit design requirement description information is processed, a radio frequency circuit constraint condition set is obtained, retrieval is conducted based on the radio frequency circuit constraint condition set, and radio frequency device feature information is obtained; inputting the radio frequency circuit constraint condition set and the radio frequency device feature information into a first model to obtain a radio frequency circuit design action sequence; executing the sequence to obtain a radio frequency circuit netlist and performing simulation; determining a performance mismatch deviation value based on the simulation result data and the radio frequency circuit constraint condition set; in response to the fact that the performance mismatch deviation value does not meet the preset convergence condition, tuning correction data are automatically determined, and the radio frequency circuit design action sequence is iteratively updated until the precise tuning requirement is met. According to the technical scheme provided by the embodiment of the invention, closed-loop automatic tuning from requirements to radio frequency parameters is realized, and the design efficiency and tuning precision of the radio frequency circuit are remarkably improved.

Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.

The application provides a network table query method and data packet processing method of a switch and related devices. A plurality of binary classifiers are set in the on-chip memory of a switch processor. According to the output values of the exact match table, the longest prefix match table and the access control list, the pre-operation results corresponding to the output values are generated through hash operation, and the pre-operation results are pre-stored in the plurality of binary classifiers corresponding to the exact match table, the longest prefix match table and the access control list. When the network table query of the switch is performed, the plurality of binary classifiers can be used to output the output values of the switch network table in parallel based on the pre-operation results. The scheme realizes the isomorphism of the storage structures of the exact match table, the longest prefix match table and the access control list, and can dynamically allocate the storage resources of the on-chip memory when the network table query is performed, so as to adapt to the network table query in different time and different scenes.

This invention discloses an accelerated method and apparatus for precise probabilistic simulation in combinatorial equivalence checking, relating to the fields of electronic design automation (EDA) and high-performance computing. The method includes: parsing the input circuit combinational logic netlist to form an EPS operator graph and corresponding data distribution configuration, transmitting this data to a GPU; starting the GPU to distribute the EPS operator graph to a processing unit array for EPS calculation based on the data distribution configuration using a data flow-driven approach; and collecting the running status information of each round of calculation and feeding it back to the CPU for dynamic optimization of the next round of calculation. This method can transform circuit calculation tasks into data flow-driven EPS operator graphs and execute them on the GPU, efficiently utilizing the GPU's massively parallel computing capabilities to overcome performance bottlenecks. The pipelined task advancement based on superblocks and the dynamic optimization mechanism based on performance reports can adapt to the computational characteristics of different circuit structures, balance the load, optimize resource allocation, and significantly shorten the verification cycle of combinatorial equivalence checking.

The application relates to an electromagnetic simulation grid generation method and device and an electronic device, wherein the electromagnetic simulation grid generation method comprises the following steps: cutting a GDSII layout file according to a process technology file to generate a two-dimensional layout file; stretching the two-dimensional layout file according to the process technology file to generate a three-dimensional geometric model, and establishing a mapping relationship between a two-dimensional graph and a three-dimensional entity; wherein the two-dimensional graph contains a graphic label added for a target object; determining a target three-dimensional entity corresponding to the graphic label of the target object according to a netlist file in combination with the mapping relationship, and creating a port surface at an endpoint of the target three-dimensional entity; constructing an air box surrounding the three-dimensional geometric model; adding an electromagnetic grid to a region represented by each three-dimensional entity, the port surface and an air domain of the air box of the three-dimensional geometric model to generate an electromagnetic simulation grid file, so as to solve the problem of too much manual intervention in the conversion process from a GDSII layout to a simulation grid.

This application provides a chip layout optimization method, comprising: acquiring a netlist of the chip, the netlist including information of multiple logic units and the connection relationships of the multiple logic units; setting the multiple logic units and the lines connecting the multiple logic units on multiple bare die discs (DIEs) to form an initial layout of the multiple DIEs; optimizing the layout of the first DIE according to a first dataset and the initial layout of the first DIE, wherein the first DIE is any one of the multiple DIEs, and the first dataset includes the layout costs of the multiple DIEs. Embodiments of this application can obtain the relationship between the layout costs of the multiple DIEs based on the first dataset, enabling the first DIE to compare its first cost with the layout costs of other DIEs on the chip in real time during the iteration process and adjust its own iteration speed, thereby reducing the dispersion between the layout costs of the multiple DIEs and thus obtaining a chip with a higher power performance average (PPA) index.

This invention provides a process mapping method and system based on priority cut sets to solve the problems of huge computational resource consumption and poor scalability caused by exhaustive cut enumeration in existing process mapping methods. The invention first obtains the logical network to be mapped; then, it optimizes the network through multiple iterative mapping passes. In each pass, for each node in the network, candidate cut sets are generated by merging a finite number of priority cut sets of its fan-in nodes, and new priority cut sets are selected from the candidate cut sets according to a dynamic priority ranking criterion; finally, a mapped netlist is generated based on the finally determined representative cut sets. This invention avoids exhaustive search by only calculating and storing a small number of optimal cut sets, significantly reducing the time and space complexity of the algorithm. At the same time, the multi-pass iteration and dynamic optimization strategy ensures high-quality mapping results, making it particularly suitable for the design of large-scale, complex integrated circuits.

An FPGA-oriented DSP placement optimization method for CNN accelerators includes the following steps: S1. DSP path information extraction: converting a designed netlist into a graph representation, and carrying out data-path DSP node identification and data-path DSP graph building; and S2. datapath-driven DSP placement: distributing data-path DSP nodes to specific positions on an FPGA according to an extracted data-path DSP graph. According to the invention, automated extraction and building of data-path DSP graphs are carried out by means of graph neural network (GCN)-based DSP node classification and min-cost flow (MCF) model optimization algorithms, and compact placement and cascade constraint optimization are used in combination, thereby greatly improving the timing performance and computing efficiency of the placement and also significantly improving the clock frequency and throughput. Therefore, the method provides a universal and efficient FPGA placement solution for multiple CNN accelerator architectures.

This invention relates to the field of integrated circuit technology, specifically to an encoding representation method suitable for analog integrated circuit topology generation and parameter optimization. The method includes the following steps: encoding the analog integrated circuit; converting the circuit encoding into an adjacency matrix to represent circuit connection relationships; extending the encoding to support analog integrated circuit topology generation; and extending the encoding to support analog integrated circuit parameter optimization. This encoding representation method for analog integrated circuit topology generation and parameter optimization, while fully representing the analog integrated circuit, proposes an adjacency matrix to represent the circuit topology structure and serve as the input and output of the topology generation algorithm. It is applicable to analog integrated circuit topology generation and parameter optimization, and can fully represent the information required for circuit topology generation and parameter optimization. This invention has the advantages of strong integration integrity, support for mutual conversion with netlists, and adaptability to circuit topology generation and parameter optimization.

The hardware Trojan detection method and system based on low activity and low observation node joint analysis belong to the technical field of integrated circuit security, and solve the problem of how to improve the accuracy of identifying high-concealment hardware Trojan; the gate-level netlist is abstracted into a signal propagation directed graph, the nodes in the low activity candidate trigger node set are taken as the starting nodes, the nodes in the low observation candidate load node set are taken as the target nodes, the effective signal propagation path from the starting node to the target node is searched in the directed graph, and if the effective signal propagation path exists, it is determined as a high-risk hardware Trojan potential link; the application proposes a method for identifying high-concealment hardware Trojan potential signal link based on gate-level netlist static analysis, which does not depend on the golden reference model, and does not need to know the Trojan feature library, and is especially suitable for third-party IP core access security detection, backdoor review and logic credibility verification scenes.

The application discloses a circuit netlist intelligent correction method and system based on a three-layer verification mechanism. The method constructs a progressive architecture through a syntax verification layer, a PDK compliance verification layer and a circuit integrity verification layer, comprehensively detects the SPICE circuit netlist, the circuit integrity verification layer analyzes the signal flow direction and polarity from input to output based on a graph structure, and performs contrast detection in combination with basic circuit unit templates such as differential pairs and current mirrors, and an intelligent decision engine performs hierarchical processing according to error types: format pairing abnormalities are directly corrected, parameter boundaries or polarity adjustments generate correction suggestions for confirmation, and topological defects of missing basic units or signal transmission path breaks are fed back to an AI engine for regeneration, and after correction, the correctness is ensured through closed-loop re-verification, and the efficiency and accuracy of netlist verification are significantly improved.

One method includes capturing a photon emission microscopy (PEM) image of an integrated circuit (IC) and identifying emission sites in the PEM image, where emission sites are associated with leakage current. A set of common networks connecting multiple emission sites is located using layout data and / or netlist data from computer-aided design (CAD) data. A critical network connecting a threshold number of emission sites is identified from this set of common networks based on the layout data and / or netlist data. The critical network is cross-mapped by a processor to netlist data in the CAD data. A specific device with output pins connected to the critical network is identified based on the netlist data. The specific device identified based on the netlist data is cross-mapped by the processor to layout data, where the critical network connects at least two devices, including the specific device, at the identified emission sites.

This invention discloses a reinforcement learning simulation step size control method based on closed-loop adaptive noise injection and entropy increase optimization strategy, belonging to integrated circuit computer-aided design technology. Specifically, the method involves: first, inputting the circuit netlist and interacting with the simulator using file read / write; next, establishing two new network output layers to convert the deterministic actions of the policy network's output into a probability distribution; then, obtaining the entropy regularization term based on the probability density function and weight coefficients, and adding it to the policy loss function; next, generating Gaussian-distributed exploration noise and adjusting the standard deviation of the noise at each step using a PID controller; finally, adjusting the policy network parameters using a gradient update method and injecting the exploration noise into the output actions to obtain the final time step. Using this invention helps enhance the simulation stability of pseudo-transient analysis, improves simulation efficiency, and provides a new method for DC analysis.

This invention discloses an FPGA netlist synthesis method and system based on multi-tool collaboration. The method includes: acquiring the parent layer design code of the FPGA to be synthesized; identifying logic modules in the parent layer design code that cannot be synthesized using a first synthesis tool, as these modules to be split; separating the modules to be split into a second design part, and using the remaining part of the parent layer design code as the first design part, retaining the black-box interface definitions of the modules to be split in situ within the first design part; independently synthesizing the first design part using the first synthesis tool to generate a first netlist; selecting a suitable second synthesis tool to independently synthesize the second design part to generate a second netlist; and filling the entities corresponding to the second netlist into the black-box positions of the first netlist to generate a parent layer netlist file. This method solves the problem of synthesis failure caused by a single synthesis tool's incompatibility with multiple languages ​​and IP sources, and avoids the forced porting of unmodifiable code.

This invention discloses a large-scale power grid simulation method, program product, and storage medium based on algebraic multigrid optimization. The method includes: parsing the netlist of a large-scale power grid to establish a power grid topology matrix; extracting global feature vectors based on the netlist and the power grid topology matrix; compressing the power grid topology matrix to obtain a compressed feature matrix; constructing and training a regression model, which is used to predict the solution time based on the compressed feature matrix, global feature vectors, and coarsening parameters; using the minimum output of the regression model as the objective function, and employing simulated annealing to find the optimal coarsening parameters; establishing a power grid simulation system Ax = b; and solving the power grid simulation system using the algebraic multigrid method with the optimal coarsening parameters to obtain the power grid unknown vectors, thus realizing large-scale power grid simulation. This invention improves solution efficiency and reduces memory consumption while ensuring accuracy.

The application discloses a traffic generation device. A traffic model is encapsulated into a first data packet by a software processor, and a routing network table is encapsulated into a second data packet, which are respectively stored into corresponding first and second storage modules by a packet distribution circuit in a hardware processor. A traffic generation circuit parses the traffic model in the first data packet from the first storage module, and independently generates an initial message and corresponding index information. A routing processing circuit quickly obtains corresponding routing entries from the second storage module according to the index information and returns in real time, so that the routing access operation and the data packet generation operation are decoupled and executed in parallel at the hardware level. The routing processing circuit and the traffic generation circuit realize accurate cooperation through the index information, so that the real-time query process of the routing network table no longer blocks the message generation pipeline, thereby effectively solving the problems of message loss and traffic distortion caused by external storage access delay.

This invention discloses a rapid assessment method for soft error rate caused by single-event effects based on an analytical function library. It addresses the problems of low efficiency and difficulty in supporting large-scale circuit evaluation in traditional TCAD simulation. The method constructs and calibrates device models based on process design kits to obtain accurate electrical characteristics of the calibration device model. Based on multidimensional key irradiation variables, dense TCAD sampling and parametric fitting are performed on the calibration device to construct a response function library. Based on the actual integrated circuit layout, particle transport simulation under radiation conditions is performed in Geant4 to extract the secondary particle set. The corresponding transient current is rapidly synthesized by querying the response function library and interpolating. The current is injected into the SPICE circuit netlist for simulation to determine whether single-event upset has occurred and to calculate the soft error rate. This method achieves an order-of-magnitude improvement in simulation efficiency while maintaining accuracy, making it suitable for rapid radiation resistance assessment and design hardening of complex integrated circuits.

This invention relates to the field of FPGA, and particularly to an FPGA chip and a method, apparatus, device, and storage medium for constructing its top-level netlist. The method includes: acquiring a preset model file; integrating at least one lowest-level logic unit into a basic logic unit based on the model file; integrating the at least one basic logic unit and a configuration memory into a grid cell; arranging multiple grid cells vertically to integrate them into a logic sequence cell; arranging multiple logic sequence cells horizontally to integrate them into a logic resource region cell; and arranging multiple logic resource region cells in an array to obtain a top-level netlist. Through the above method, the layout of the FPGA top-level netlist of this invention is reasonable and meets the requirements of large-scale FPGA chips.

This invention discloses a logic synthesis mapping method based on FPGA dual-output lookup tables. First, the target circuit netlist is preprocessed and structurally normalized, mapping logic nodes to single-output lookup tables of a unified format. Then, through primitive normalization, each lookup table unit is converted into native lookup table primitives consistent with the target FPGA technology library, forming a standardized lookup table netlist. An inverted index is constructed, and candidate lookup table pairs with shared inputs are generated using index relationships. Structural and functional constraints are sequentially performed on the candidate pairs to filter out mergeable lookup table pairs. After sorting them using a resource cost function, a merge mapping is performed sequentially, concatenating them into a six-input dual-output lookup table and generating corresponding initialization parameters. This method can reduce the number of lookup tables and input pin pressure while maintaining logical functional correctness, and can be integrated as an independent optimization step into various FPGA synthesis and place-and-route tools.

A method of analyzing an integrated circuit (IC) is provided. An original netlist of the IC is obtained according to a layout and a schematic of the IC. A first simulation is performed with the original netlist to obtain electrical properties of devices in the IC. A thermal analysis is performed on the IC according to the electrical properties, to obtain a localized temperature parameter of each of the devices. A second simulation is performed according to the original netlist and the localized temperature parameter of each of the devices. The localized temperature parameter of each of the devices is determined according to a voltage and a current of the device during the first simulation.