1027 results about "Netlist" patented technology

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

The present invention relates to the technical field of calculation, estimation or counting. Disclosed is a critical path sorting method based on a graph neural network. The method comprises: first, obtaining a potential critical path set in a netlist by means of a static timing analysis tool; next, converting a netlist file comprising circuit function information into a graph data structure, and obtaining an initial training set on the basis of a relevant process configuration file; then, inputting the initial training set into a graph neural network for training to obtain a critical unit prediction model, wherein the critical unit prediction model consists of three parts, namely, a deep structure auto-encoder, a nonlinear attribute auto-encoder and a joint error reconstruction module; and finally, quantifying the criticality of each path in the potential critical path set on the basis of critical unit information and a path criticality calculation algorithm in the netlist, and obtaining a critical path sequence under process awareness. According to the method, critical paths in circuits influenced by process deviations can be effectively sorted, providing valuable reference for circuit optimization.

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

The present application relates to the technical field of chip design, and provides a chip layout and training method, an electronic device, a storage medium, and a chip system. According to the method, generalization of the layout method across different chip netlists can be improved. The method comprises: determining first relative position information, wherein the first relative position information is relative position information between different units among units laid-out in a sample chip; determining a first input of a graph neural network to be trained, wherein the first input is obtained on the basis of a first netlist corresponding to the sample chip; obtaining a first output by means of the graph neural network; performing encoding on the basis of the first output to obtain second relative position information; calculating a loss function value on the basis of the first relative position information and the second relative position information; and optimizing a trainable parameter in the graph neural network on the basis of the loss function value.

The invention discloses a perceptually optimized wiring time sequence prediction method for a digital integrated circuit, electronic equipment and a storage medium, and the method comprises the steps: constructing a heterogeneous graph according to a circuit netlist, fusing the heterogeneous graph with feature vectors corresponding to all units and interconnection lines, inputting the fused heterogeneous graph into a trained heterogeneous graph neural network, and obtaining graph network embedding; inputting the feature matrix of the layout into the trained convolutional neural network to obtain convolutional network embedding; splicing graph network embedding and convolutional network embedding to obtain multi-modal local embedding; constructing a feature sequence of the path according to a connection relationship between a logic unit and an interconnection line in the path by multi-modal local embedding, and inputting the feature sequence of the path into the trained Transform network to obtain a path delay residual prediction value after wiring; and adding the path delay value after layout and the path delay residual prediction value after wiring, and finally obtaining a path delay prediction value after wiring. According to the method, the path delay after wiring can be accurately and efficiently predicted before wiring.

The invention discloses a Multi-Point CTS-based chip clock design optimization method, and relates to the technical field of chip clock design optimization, and the method comprises the following steps: using a hardware description language VHDL to compile RTL codes describing circuit behaviors, using a DC EDA tool of Synopsys to convert the RTL codes into a logic netlist, using a standard algorithm H-Tree to construct a preliminary clock tree structure layout, and using the standard algorithm H-Tree to construct the logic netlist. Obtaining a primary clock tree topological graph; a Multi-Point CTS method is introduced, a plurality of clock sources are adopted to optimize the initial clock tree topological graph, and an optimized clock tree topological graph is obtained; a static time sequence analysis tool PrimeTime is adopted to analyze the optimized clock tree topological graph, and a time sequence analysis result is obtained; identifying the longest path from a clock source to a register in the optimized clock tree topological graph according to a time sequence analysis result, marking the longest path as a critical path, and finding the optimal position for placing a buffer in the critical path by adopting a heuristic search algorithm; and calculating a difference value between the actual delay and the maximum allowable delay of the optimized clock tree topological graph by using PrimeTime again.

The invention provides a circuit logic synthesis method for FPGA mapping based on reinforcement learning, and aims at solving the problem that in a traditional netlist optimization method, a circuit is not seen in model optimization, and the capacity is insufficient. The method comprises the following steps: firstly, constructing a logic comprehensive data set, and then preprocessing the data set to obtain statistical characteristics and a graph structure of a circuit; then, a logic comprehensive model based on reinforcement learning and aiming at FPGA mapping is constructed, pre-training is conducted through the preprocessed data set, and finally logic optimization is conducted on a circuit through the pre-trained logic comprehensive model based on reinforcement learning and aiming at FPGA mapping. According to the circuit feature extraction module, a GNN module is adopted to analyze a logic circuit and a netlist structure to obtain graph embedding, statistical features of the logic circuit and the netlist are analyzed through an FCN module, the features of the two parts are spliced to obtain an accurate enhanced representation state of the circuit, and the understanding capacity of a reinforcement learning model on different circuits is improved.

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

The invention belongs to the field of integrated circuit design, and particularly relates to a chip layout optimization method, system and device based on improved reinforcement learning. The method comprises the following steps: S1, constructing a layout optimization model comprising a feature coding module, a feature fusion module, an experience pool, a strategy network and a value network; the feature coding module is used for extracting a position mask, a line mask and a view mask of the netlist file; the feature fusion module extracts local features and global features and generates comprehensive features; the experience pool, the strategy network and the value network form a reinforcement learning framework. S2, using a large number of random netlists as sample data for training a layout optimization model; and S3, inputting a chart file to be optimized into the trained layout optimization model, outputting an optimized netlist file by the layout optimization model, and generating a corresponding optimized circuit layout chart according to the netlist file. The chip layout optimization method solves the problems that an existing chip layout optimization method is low in efficiency and insufficient in generalization.

The embodiment of the invention discloses a static time sequence analysis method and device based on layout features and electronic equipment. According to the scheme, the gate-level netlist of the circuit can be obtained, the time sequence diagram is established according to the gate-level netlist, the nodes and the directed edges in the time sequence diagram are filled with the first statistical characteristics respectively, the first layout characteristics of each connection network in the time sequence diagram are calculated, and the time sequence diagram is expanded according to the first layout characteristics; and constructing a static time sequence analysis prediction model based on the graph neural network and the convolutional neural network, and predicting the delay of a connecting line time sequence arc, the delay of a logic gate time sequence arc and the delay of a pin node in the expanded time sequence diagram, thereby determining a static time sequence analysis result. According to the method, the layout characteristics of the circuit are obtained by extracting and coding the nodes of the connection network, and the static time sequence analysis prediction model is modeled according to the layout characteristics, so that the prediction accuracy of the prediction model in the layout areas with different aspect ratios is improved.

The invention provides an EDA (Electronic Design Automation) software collaborative optimization method based on a memory compiler entity IP (Internet Protocol), which relates to the technical field of memorizers and comprises the following steps: acquiring IP layout information, and establishing a time sequence netlist model containing path time sequence and power consumption distribution; by adjusting the intensity of a data driver and a hierarchical structure of a decoder, setting multiple stages of buffers to realize time sequence convergence; determining a hot spot area based on power consumption distribution, and inserting a low-power-consumption unit capable of dynamically adjusting voltage frequency to realize local power consumption dynamic balance; the layout is updated, wiring is optimized, the optimized memory compiler IP layout is generated, and the circuit performance and reliability are improved.

Disclosed in the present application are an analog circuit netlist division method and system based on reinforcement learning. The method comprises: acquiring an analog circuit netlist; performing feature extraction processing on the analog circuit netlist, so as to obtain circuit features; performing classification processing on the circuit features on the basis of a hierarchical reinforcement learning algorithm, so as to obtain a classification result; and performing function labeling processing on the classification result, so as to obtain a modular circuit netlist. By means of the present application, automatic identification and classification can be performed on an analog circuit in combination with machine learning, so as to better adapt to different types of circuits and problems, thereby improving the quality and efficiency of division. The present application can be widely applied to the technical field of circuit division.

The invention provides a chip testability design program code generation device and method, and the device comprises a chip design file processing module which is used for receiving a chip design file; the testability design circuit generating and marking module is used for adding a test point and an observation point in a circuit of the chip according to a testability design rule of the chip; the resource dynamic calculation module is used for dynamically generating a pseudo netlist according to the flattening rule; the virtual device modeling module is used for modeling a virtual device and recording an FPGA model generated when the pseudo netlist is generated; the simulation and testability design collaborative optimization module is used for generating a simulation code of the verification platform according to the program code completion degree of the chip design file and performing simulation; and the design data sharing module is used for storing the shared chip design file. The invention further provides a method for implementing the device. According to the method, the efficiency of designing the chip test circuit can be improved, and the flexibility and usability of collaborative design of tools in different design stages of the chip are improved.

The invention discloses a PCB component layout method, device and equipment based on a multi-modal large model, and relates to the technical field of electronic design automation, the method comprises the following steps: carrying out quality screening on a plurality of PCB design files which have been laid out to obtain a qualified design file set; constructing a serialized training sample set based on the qualified design file set; each training sample sequence comprises a plurality of training samples arranged according to a layout logic sequence; each training sample comprises multi-modal data representing a current layout state and a real position coordinate of a next component to be laid out; based on the serialized training sample set, training the open-source multi-modal large model to obtain a PCB component layout model; and iteratively generating a layout file of the target PCB based on the netlist file of the target PCB and the PCB component layout model. The method is high in generalization capability and low in cost based on the PCB component layout model trained by the layout data, and can realize rapid layout of components of a new PCB.

The invention provides a chip layout and training method, electronic equipment, a storage medium and a chip system, relates to the technical field of chip design, and can improve the generalization of the layout method among different chip netlists. The method comprises the following steps: determining first relative position information; the first relative position information is relative position information between different units in the arranged units in the sample chip; determining a first input of a to-be-trained graph neural network; the first input is obtained based on a first netlist corresponding to the sample chip; obtaining a first output through a graph neural network; executing coding based on the first output to obtain second relative position information; calculating a loss function value according to the first relative position information and the second relative position information; and optimizing trainable parameters in the graph neural network according to the loss function value.

The invention provides an analog integrated circuit layout method, device and equipment, a medium and an integrated circuit, and the method comprises the steps: obtaining an original layout diagram corresponding to the ith iteration based on the netlist information and a strategy network model of each electronic element needing to be arranged; when it is determined that i does not reach the first preset value, obtaining a value parameter of the original layout diagram corresponding to the ith iteration, updating a model parameter of the strategy network model based on the value parameter of the original layout diagram corresponding to the ith iteration, increasing i by 1, returning to execute the ith iteration calculation, and when it is determined that i reaches the first preset value, updating the model parameter of the strategy network model based on the value parameter of the original layout diagram corresponding to the ith iteration. Determining the original layout diagram corresponding to the ith iteration as a first intermediate layout diagram of each electronic component; and based on the netlist information of each electronic component, correcting the first intermediate layout diagram to obtain a target layout diagram of each electronic component. According to the invention, the reasonability and efficiency of the analog integrated circuit layout are effectively improved, and an automatic solution is provided for the analog integrated circuit layout.

The invention relates to the field of electronic design automation (EDA), and provides an AMS circuit automatic design method using a large language model. The method aims at solving the problem that an existing AMS circuit design is insufficient in automation degree, and mainly comprises the steps that a schematic circuit diagram and text description are extracted from literatures, and a data set containing the schematic circuit diagram, a netlist and annotation information is constructed; performing connectivity detection on the schematic circuit diagram, and extracting a netlist; carrying out annotation processing to obtain annotation information; constructing a knowledge graph for storing circuit information; obtaining a design strategy by using a large language model, and describing a circuit architecture; according to the design strategy and the local annotation, relevant circuits and test platforms are retrieved, a complete circuit topology is assembled, and simulation is carried out; size optimization is carried out based on constraints, and a Bayesian optimization algorithm is used for solving; and if the initial topological structure cannot meet the performance target, carrying out topological reconstruction. According to the invention, the automation level and efficiency of analog and mixed signal circuit design are improved.

A method (of manufacturing a semiconductor device) includes migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, the migrating including: expanding a first version of the first netlist and a first precursor of the second netlist correspondingly to form a second version of the first netlist and a second precursor of the second netlist; before conducting (A) placement and routing (P&R) of a layout diagram corresponding to the second netlist or (B) a static timing analysis of the layout diagram; performing a logic equivalence check (LEC) between the second version of the first netlist and the second precursor of the second netlist, thereby identifying migration errors, and revising the second precursor of the second netlist to reduce the migration errors, thereby resulting in a third precursor of the second netlist.

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention discloses a clock domain crossing circuit timing sequence closed-loop optimization method and system, and relates to the technical field of integrated circuit design, and the method comprises the steps: reading a circuit netlist and timing sequence constraints, recognizing a converged path, and carrying out the clustering analysis to form a plurality of path groups; establishing a time sequence analysis model, and dynamically calculating the maximum delay constraint of the data signal in the path group; matching and executing at least one time sequence optimization strategy for each path group; and carrying out closed-loop time sequence verification, retaining a legacy path set which does not meet the constraint, and repeatedly executing the time sequence optimization strategy until a convergence condition is reached or the maximum preset number of iterations is reached. According to the method disclosed by the invention, the cross-domain path needing to be optimized in the DMUX structure can be accurately positioned without manual intervention, so that the path identification efficiency is improved, constraint omission or grouping deviation caused by manual operation is avoided, design defects are reduced from the source, and the design reliability of a chip is improved.

A system (100) for context-aware timing ECO generation using hierarchical and flat design mapping, comprising: a design data acquisition module configured to import hierarchical and flat design data including netlists, timing reports, physical layouts, and design constraints; a contextual timing analysis module configured to detect timing violations in both hierarchical and flat design contexts; a hierarchical-flat mapping engine configured to establish bidirectional correspondence between hierarchical and flat representations of the design; an ECO opportunity identification module configured to identify optimal modification points based on timing improvement potential and minimal design disturbances; an ECO generation and optimization module configured to create optimized ECO scripts taking into account timing, power, and area constraints; a verification and validation module configured to confirm functional equivalence, compliance with design rules, and timing completion; and an ECO implementation and reporting module configured to integrate the validated ECO into the main design database and generate traceable change reports; where the system operates to generate context-aware ECOs that maintain design consistency in both hierarchical and flat design views.

The invention discloses a circuit level optimization method based on NAND and XOR majority logic, which comprises the following steps of: analyzing target design circuit information to obtain an NAND graph AIG; logic optimization with the optimization node number as the target is executed on the AIG; the AIG after node number optimization is logically converted into an XOR majority logic diagram XMG; logic optimization with the optimization logic hierarchy as the target is executed on the XMG obtained through logic conversion; the XMG after logic hierarchy optimization is logically converted into an AIG; logic optimization with the optimization logic hierarchy as the target is executed on the AIG obtained through logic conversion; and executing time delay-oriented process mapping on the AIG after logic hierarchy optimization, and generating and outputting a process gate-level netlist. According to the method, the logic optimization processes of the AIG and the XMG are effectively combined, the local optimization problem in optimization is improved, the adaptability to a specific design target is enhanced, the optimization efficiency and effect of large-scale circuit design are improved, and a better circuit after logic optimization is obtained.

Disclosed is an AI-based automated circuit generation method. The method includes obtaining design metrics; capturing a dependency relationship among design metrics by using an attention mechanism, extracting features by using a multi-layer Transformer structure to obtain an overall structure and a high-level feature representation of a circuit, and matching the high-level feature representation with a standard circuit netlist template based on the overall structure of the circuit to obtain a current circuit netlist; simulating the current circuit netlist to obtain a simulation report, and extracting error information from the simulation report; and correcting the current circuit netlist based on the error information, simulating a corrected circuit netlist again, looping until there are no errors in the simulation report, and outputting a final circuit netlist. The present invention solves the problems that the existing method has limitations and is difficult to quickly, automatically and flexibly design a complex circuit.

The invention discloses an identification and verification method and system for a secondary drawing of a transformer substation, and belongs to the technical field of image identification, and the method specifically comprises the steps: analyzing a CAD vector diagram, obtaining four-corner references and pixel coordinates of a scanning graph, building initial mapping of pixels and engineering millimeter coordinates by taking an engineering millimeter coordinate system as a reference, and generating a unified intermediate representation model; constructing a terminal strip parameterization template based on the vector anchor point set and the visual anchor point set; a composite deformation field is calculated through vector-bitmap-vector closed-loop rendering calibration, terminal row alignment and terminal sequence binding are completed in the composite deformation field, and a terminal pixel position-terminal sequence-engineering millimeter coordinate consistent mapping table is formed; comparing the topological netlist to obtain an electrical node corresponding table; and performing source decomposition on the terminal position residual error based on the composite deformation field and generating a self-adaptive tolerance band, and finally executing wiring verification by taking the self-adaptive tolerance band, the electrical connectivity and the serial number consistency as criteria and outputting a verification report.

The invention provides a rapid modeling simulation method based on a time domain hybrid finite element method and a circuit simulator SPICE. The rapid modeling simulation method is used for analyzing transient linear / nonlinear and passive / active complex microwave network circuit models on a PCB. The method comprises the following steps of: constructing an electromagnetic module of a microwave network circuit in computer aided design software, writing an SPICE netlist of the circuit module, and realizing interaction between the electromagnetic module and the circuit module through voltage and current defined on a lumped port, so as to obtain a complete circuit structure; in the electromagnetic part, a modal order reduction technology based on a second-order Arnoldi algorithm is adopted to reduce the order of a wave equation to a low-dimensional Krylov subspace for solving, and the data interaction process of the electromagnetic part and the circuit part in each time step length is obviously accelerated; in the time domain hybrid finite element method, the tree-cotree technology is adopted to overcome the problem of low-frequency breakdown or high-density breakdown occurring in the time domain finite element method; a circuit simulator SPICE enables a joint simulation algorithm to be powerful, and a complex multi-port circuit can be simulated.

The invention provides a stacked chip architecture modeling method and a stacked chip architecture modeling system. The method comprises the following steps: dividing an on-chip chip to be modeled into a plurality of core particles; the method comprises the following steps of: modeling a chip by adopting a three-stage joint modeling mode, and respectively executing core size level modeling, medium level modeling and substrate level modeling; arranging the placement positions of the core particles according to the factors of the time sequence of the key path, the bus length and the super-long path; according to the connection relation between the interior and the exterior of the core particle, and according to the weights of the internal netlist and the external netlist of the core particle or user input information, optimizing the positions of the internal elements of the core particle, and adjusting the positions of the micro convex points mapped by the elements; and carrying out automatic wiring based on the arrangement position of each core particle, removing a network with conflicts in wiring, carrying out labyrinth wiring on an area in which wiring is removed, and searching an optimal wiring path. The system is used for implementing the method. The invention provides a one-stop chip design EDA tool, and the design precision of the chip can be improved.

The invention discloses a parasitic parameter extraction method based on supervised learning decision, which predicts a method which meets the precision requirement and has the shortest parasitic parameter extraction time from a plurality of parasitic parameter extraction technologies. The method comprises the following steps: reading a layout file; scanning and dividing the layout file into modules; extracting a density voltage matrix by all modules, flattening the density voltage matrix to serve as an input vector, and transmitting the input vector to a multi-layer sensor (MLP); predicting a parasitic parameter extraction technology which accords with precision and is shortest in time through MLP; each module executes the predicted parasitic parameter extraction technology; and generating an extraction netlist. According to the method, the advantages of the existing parasitic parameter extraction technology are fully exerted, and the respective defects are avoided.

The invention discloses an analog IC netlist layout collaborative optimization method and system based on a reinforcement learning algorithm, and the method comprises the steps: generating an initial netlist of an analog IC, and inputting the initial netlist into a pre-built simulation platform; generating an analog IC circuit layout according to the initial netlist of the analog IC, and performing simulation through a simulation platform; the reinforcement learning agent builds a graph neural network to execute an optimization task based on a pre-built analog IC netlist multilateral heterogeneous graph, generates an optimized analog IC netlist and sends the optimized analog IC netlist to the simulation platform; a new analog IC circuit layout is generated according to the optimized netlist of the analog IC, the simulation platform simulates the optimized netlist of the analog IC and the new analog IC circuit layout, and the analog IC circuit layout is further optimized through a reinforcement learning agent; and continuously interactively optimizing the reinforcement learning agent and the simulation platform until a final parameter combination meeting the performance index is obtained. According to the invention, the efficiency and performance of circuit optimization are greatly improved.

The invention provides a power consumption feature extraction method and system for a static random access memory standard cell library, electronic equipment and a storage medium, and the method comprises the steps: S1, reading a standard cell model file, a standard cell netlist and a standard cell time sequence path of a static random access memory, and constructing and generating an excitation waveform description file; s2, establishing a simulation file of the static random access memory standard unit, simulating the static random access memory standard unit, and respectively obtaining electrical characteristic data of an input pin and an output pin of the static random access memory standard unit; s3, analyzing the electrical characteristic data of the static random access memory standard unit, and obtaining a short-circuit power consumption time sequence path and a switching power consumption time sequence path existing in the static random access memory standard unit; and S4, respectively calculating power consumption values of each switching power consumption time sequence path and each short-circuit power consumption time sequence path. According to the method, the power consumption characteristics of the SRAM standard cell are extracted in the design stage of the standard cell library, and the precision and efficiency of power consumption analysis can be improved.