860 results about "Netlist" patented technology

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

The present invention relates to the technical field of calculation, estimation or counting. Disclosed is a critical path sorting method based on a graph neural network. The method comprises: first, obtaining a potential critical path set in a netlist by means of a static timing analysis tool; next, converting a netlist file comprising circuit function information into a graph data structure, and obtaining an initial training set on the basis of a relevant process configuration file; then, inputting the initial training set into a graph neural network for training to obtain a critical unit prediction model, wherein the critical unit prediction model consists of three parts, namely, a deep structure auto-encoder, a nonlinear attribute auto-encoder and a joint error reconstruction module; and finally, quantifying the criticality of each path in the potential critical path set on the basis of critical unit information and a path criticality calculation algorithm in the netlist, and obtaining a critical path sequence under process awareness. According to the method, critical paths in circuits influenced by process deviations can be effectively sorted, providing valuable reference for circuit optimization.

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

The invention discloses a perceptually optimized wiring time sequence prediction method for a digital integrated circuit, electronic equipment and a storage medium, and the method comprises the steps: constructing a heterogeneous graph according to a circuit netlist, fusing the heterogeneous graph with feature vectors corresponding to all units and interconnection lines, inputting the fused heterogeneous graph into a trained heterogeneous graph neural network, and obtaining graph network embedding; inputting the feature matrix of the layout into the trained convolutional neural network to obtain convolutional network embedding; splicing graph network embedding and convolutional network embedding to obtain multi-modal local embedding; constructing a feature sequence of the path according to a connection relationship between a logic unit and an interconnection line in the path by multi-modal local embedding, and inputting the feature sequence of the path into the trained Transform network to obtain a path delay residual prediction value after wiring; and adding the path delay value after layout and the path delay residual prediction value after wiring, and finally obtaining a path delay prediction value after wiring. According to the method, the path delay after wiring can be accurately and efficiently predicted before wiring.

The invention provides a circuit logic synthesis method for FPGA mapping based on reinforcement learning, and aims at solving the problem that in a traditional netlist optimization method, a circuit is not seen in model optimization, and the capacity is insufficient. The method comprises the following steps: firstly, constructing a logic comprehensive data set, and then preprocessing the data set to obtain statistical characteristics and a graph structure of a circuit; then, a logic comprehensive model based on reinforcement learning and aiming at FPGA mapping is constructed, pre-training is conducted through the preprocessed data set, and finally logic optimization is conducted on a circuit through the pre-trained logic comprehensive model based on reinforcement learning and aiming at FPGA mapping. According to the circuit feature extraction module, a GNN module is adopted to analyze a logic circuit and a netlist structure to obtain graph embedding, statistical features of the logic circuit and the netlist are analyzed through an FCN module, the features of the two parts are spliced to obtain an accurate enhanced representation state of the circuit, and the understanding capacity of a reinforcement learning model on different circuits is improved.

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

The invention provides an EDA (Electronic Design Automation) software collaborative optimization method based on a memory compiler entity IP (Internet Protocol), which relates to the technical field of memorizers and comprises the following steps: acquiring IP layout information, and establishing a time sequence netlist model containing path time sequence and power consumption distribution; by adjusting the intensity of a data driver and a hierarchical structure of a decoder, setting multiple stages of buffers to realize time sequence convergence; determining a hot spot area based on power consumption distribution, and inserting a low-power-consumption unit capable of dynamically adjusting voltage frequency to realize local power consumption dynamic balance; the layout is updated, wiring is optimized, the optimized memory compiler IP layout is generated, and the circuit performance and reliability are improved.

Disclosed in the present application are an analog circuit netlist division method and system based on reinforcement learning. The method comprises: acquiring an analog circuit netlist; performing feature extraction processing on the analog circuit netlist, so as to obtain circuit features; performing classification processing on the circuit features on the basis of a hierarchical reinforcement learning algorithm, so as to obtain a classification result; and performing function labeling processing on the classification result, so as to obtain a modular circuit netlist. By means of the present application, automatic identification and classification can be performed on an analog circuit in combination with machine learning, so as to better adapt to different types of circuits and problems, thereby improving the quality and efficiency of division. The present application can be widely applied to the technical field of circuit division.

The invention discloses a PCB component layout method, device and equipment based on a multi-modal large model, and relates to the technical field of electronic design automation, the method comprises the following steps: carrying out quality screening on a plurality of PCB design files which have been laid out to obtain a qualified design file set; constructing a serialized training sample set based on the qualified design file set; each training sample sequence comprises a plurality of training samples arranged according to a layout logic sequence; each training sample comprises multi-modal data representing a current layout state and a real position coordinate of a next component to be laid out; based on the serialized training sample set, training the open-source multi-modal large model to obtain a PCB component layout model; and iteratively generating a layout file of the target PCB based on the netlist file of the target PCB and the PCB component layout model. The method is high in generalization capability and low in cost based on the PCB component layout model trained by the layout data, and can realize rapid layout of components of a new PCB.

The invention provides an analog integrated circuit layout method, device and equipment, a medium and an integrated circuit, and the method comprises the steps: obtaining an original layout diagram corresponding to the ith iteration based on the netlist information and a strategy network model of each electronic element needing to be arranged; when it is determined that i does not reach the first preset value, obtaining a value parameter of the original layout diagram corresponding to the ith iteration, updating a model parameter of the strategy network model based on the value parameter of the original layout diagram corresponding to the ith iteration, increasing i by 1, returning to execute the ith iteration calculation, and when it is determined that i reaches the first preset value, updating the model parameter of the strategy network model based on the value parameter of the original layout diagram corresponding to the ith iteration. Determining the original layout diagram corresponding to the ith iteration as a first intermediate layout diagram of each electronic component; and based on the netlist information of each electronic component, correcting the first intermediate layout diagram to obtain a target layout diagram of each electronic component. According to the invention, the reasonability and efficiency of the analog integrated circuit layout are effectively improved, and an automatic solution is provided for the analog integrated circuit layout.

A method (of manufacturing a semiconductor device) includes migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, the migrating including: expanding a first version of the first netlist and a first precursor of the second netlist correspondingly to form a second version of the first netlist and a second precursor of the second netlist; before conducting (A) placement and routing (P&R) of a layout diagram corresponding to the second netlist or (B) a static timing analysis of the layout diagram; performing a logic equivalence check (LEC) between the second version of the first netlist and the second precursor of the second netlist, thereby identifying migration errors, and revising the second precursor of the second netlist to reduce the migration errors, thereby resulting in a third precursor of the second netlist.

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention discloses a clock domain crossing circuit timing sequence closed-loop optimization method and system, and relates to the technical field of integrated circuit design, and the method comprises the steps: reading a circuit netlist and timing sequence constraints, recognizing a converged path, and carrying out the clustering analysis to form a plurality of path groups; establishing a time sequence analysis model, and dynamically calculating the maximum delay constraint of the data signal in the path group; matching and executing at least one time sequence optimization strategy for each path group; and carrying out closed-loop time sequence verification, retaining a legacy path set which does not meet the constraint, and repeatedly executing the time sequence optimization strategy until a convergence condition is reached or the maximum preset number of iterations is reached. According to the method disclosed by the invention, the cross-domain path needing to be optimized in the DMUX structure can be accurately positioned without manual intervention, so that the path identification efficiency is improved, constraint omission or grouping deviation caused by manual operation is avoided, design defects are reduced from the source, and the design reliability of a chip is improved.

A system (100) for context-aware timing ECO generation using hierarchical and flat design mapping, comprising: a design data acquisition module configured to import hierarchical and flat design data including netlists, timing reports, physical layouts, and design constraints; a contextual timing analysis module configured to detect timing violations in both hierarchical and flat design contexts; a hierarchical-flat mapping engine configured to establish bidirectional correspondence between hierarchical and flat representations of the design; an ECO opportunity identification module configured to identify optimal modification points based on timing improvement potential and minimal design disturbances; an ECO generation and optimization module configured to create optimized ECO scripts taking into account timing, power, and area constraints; a verification and validation module configured to confirm functional equivalence, compliance with design rules, and timing completion; and an ECO implementation and reporting module configured to integrate the validated ECO into the main design database and generate traceable change reports; where the system operates to generate context-aware ECOs that maintain design consistency in both hierarchical and flat design views.

Disclosed is an AI-based automated circuit generation method. The method includes obtaining design metrics; capturing a dependency relationship among design metrics by using an attention mechanism, extracting features by using a multi-layer Transformer structure to obtain an overall structure and a high-level feature representation of a circuit, and matching the high-level feature representation with a standard circuit netlist template based on the overall structure of the circuit to obtain a current circuit netlist; simulating the current circuit netlist to obtain a simulation report, and extracting error information from the simulation report; and correcting the current circuit netlist based on the error information, simulating a corrected circuit netlist again, looping until there are no errors in the simulation report, and outputting a final circuit netlist. The present invention solves the problems that the existing method has limitations and is difficult to quickly, automatically and flexibly design a complex circuit.

The invention discloses an identification and verification method and system for a secondary drawing of a transformer substation, and belongs to the technical field of image identification, and the method specifically comprises the steps: analyzing a CAD vector diagram, obtaining four-corner references and pixel coordinates of a scanning graph, building initial mapping of pixels and engineering millimeter coordinates by taking an engineering millimeter coordinate system as a reference, and generating a unified intermediate representation model; constructing a terminal strip parameterization template based on the vector anchor point set and the visual anchor point set; a composite deformation field is calculated through vector-bitmap-vector closed-loop rendering calibration, terminal row alignment and terminal sequence binding are completed in the composite deformation field, and a terminal pixel position-terminal sequence-engineering millimeter coordinate consistent mapping table is formed; comparing the topological netlist to obtain an electrical node corresponding table; and performing source decomposition on the terminal position residual error based on the composite deformation field and generating a self-adaptive tolerance band, and finally executing wiring verification by taking the self-adaptive tolerance band, the electrical connectivity and the serial number consistency as criteria and outputting a verification report.

The invention provides a stacked chip architecture modeling method and a stacked chip architecture modeling system. The method comprises the following steps: dividing an on-chip chip to be modeled into a plurality of core particles; the method comprises the following steps of: modeling a chip by adopting a three-stage joint modeling mode, and respectively executing core size level modeling, medium level modeling and substrate level modeling; arranging the placement positions of the core particles according to the factors of the time sequence of the key path, the bus length and the super-long path; according to the connection relation between the interior and the exterior of the core particle, and according to the weights of the internal netlist and the external netlist of the core particle or user input information, optimizing the positions of the internal elements of the core particle, and adjusting the positions of the micro convex points mapped by the elements; and carrying out automatic wiring based on the arrangement position of each core particle, removing a network with conflicts in wiring, carrying out labyrinth wiring on an area in which wiring is removed, and searching an optimal wiring path. The system is used for implementing the method. The invention provides a one-stop chip design EDA tool, and the design precision of the chip can be improved.

The invention discloses an analog IC netlist layout collaborative optimization method and system based on a reinforcement learning algorithm, and the method comprises the steps: generating an initial netlist of an analog IC, and inputting the initial netlist into a pre-built simulation platform; generating an analog IC circuit layout according to the initial netlist of the analog IC, and performing simulation through a simulation platform; the reinforcement learning agent builds a graph neural network to execute an optimization task based on a pre-built analog IC netlist multilateral heterogeneous graph, generates an optimized analog IC netlist and sends the optimized analog IC netlist to the simulation platform; a new analog IC circuit layout is generated according to the optimized netlist of the analog IC, the simulation platform simulates the optimized netlist of the analog IC and the new analog IC circuit layout, and the analog IC circuit layout is further optimized through a reinforcement learning agent; and continuously interactively optimizing the reinforcement learning agent and the simulation platform until a final parameter combination meeting the performance index is obtained. According to the invention, the efficiency and performance of circuit optimization are greatly improved.

The invention provides a power consumption feature extraction method and system for a static random access memory standard cell library, electronic equipment and a storage medium, and the method comprises the steps: S1, reading a standard cell model file, a standard cell netlist and a standard cell time sequence path of a static random access memory, and constructing and generating an excitation waveform description file; s2, establishing a simulation file of the static random access memory standard unit, simulating the static random access memory standard unit, and respectively obtaining electrical characteristic data of an input pin and an output pin of the static random access memory standard unit; s3, analyzing the electrical characteristic data of the static random access memory standard unit, and obtaining a short-circuit power consumption time sequence path and a switching power consumption time sequence path existing in the static random access memory standard unit; and S4, respectively calculating power consumption values of each switching power consumption time sequence path and each short-circuit power consumption time sequence path. According to the method, the power consumption characteristics of the SRAM standard cell are extracted in the design stage of the standard cell library, and the precision and efficiency of power consumption analysis can be improved.

A fuzzy matching method based on a hierarchical graph Hash signature comprises the following steps: sorting buckets, and sequentially selecting the sorted buckets as initial buckets; performing extension layering on the initial bucket, and dividing a netlist into a hierarchical structure diagram; calculating a Hash signature for the hierarchical structure chart from bottom to top, and transmitting the Hash signature to the uppermost layer to obtain the Hash signature of each object in the initial bucket; dividing the initial bucket into a plurality of sub-buckets based on the hash signature; selecting to-be-matched sub-buckets and matching the sub-buckets; and the sub-buckets are re-divided, and matching iteration is carried out. According to the method, after the buckets are sorted, the initial buckets are selected in sequence to construct the hierarchical structure chart in a layered mode, the Hash signatures are calculated and transmitted, and the meaningful connection range is searched as much as possible based on Hash signature division and matching, so that errors of the matching result are reduced as much as possible, and meanwhile, the performance and accuracy of fuzzy matching are improved.

The invention discloses an automatic generation method for a standard cell layout with a switchable power consumption area, and relates to an LELE (Lithography-Etching-Lithography-Etching) technology, which is used for carrying out data preprocessing on a circuit netlist; respectively performing source-drain sharing operation on NMOS (N-channel Metal Oxide Semiconductor) tubes and PMOS (P-channel Metal Oxide Semiconductor) tubes in the preprocessed circuit netlist to obtain a layout with an optimal area; performing gate pairing operation on NMOS (N-channel Metal Oxide Semiconductor) transistors and PMOS (P-channel Metal Oxide Semiconductor) transistors in the preprocessed circuit netlist to form MOS (Metal Oxide Semiconductor) transistor pairs, and performing source-drain sharing operation on the MOS transistor pairs to obtain a layout with optimal power consumption; grid modeling is carried out based on design rule parameters of the process library, and a grid point canvas is established; and adding the layout with the optimal area and the layout with the optimal power consumption into the lattice point canvas, and simulating manual wiring through an A star algorithm to obtain a layout with the optimal index. According to two independent layout strategies, the grid layout is created in combination with a process design rule, and manual wiring is simulated by using an algorithm, so that the feasibility of the whole process of layout and wiring is realized.

The invention discloses an FPGA (Field Programmable Gate Array) netlist-level hardware Trojan horse detection method based on a large language model, and relates to the technical field of integrated circuit safety and hardware Trojan horse detection, and the method comprises the following steps: constructing an original FPGA netlist into a text attribute graph containing textualized attributes, generating a path text sequence through bidirectional random walk, and carrying out two-way random walk on the path text sequence; constructing a corpus to pre-train a large language model; then, delimiting a local neighborhood by taking each node as a center, generating a path text set, extracting semantic vector representation of the path text set by utilizing a pre-training model, and further constructing a node-level training sample set; on the basis, supervised fine tuning is carried out by combining a classifier and CB-Focal Loss, and a final model is obtained; in the reasoning stage, representation construction and discrimination are carried out on nodes to be detected, and node-level hardware Trojan horse detection is achieved. According to the method, circuit topology and semantic information can be reserved at the same time, node-level hardware Trojan positioning is achieved, the detection precision and generalization ability are improved, and the automation degree is improved.

The invention relates to a circuit diagram-to-netlist generation method and system based on deep learning and a product. The circuit diagram-to-netlist generation method comprises the following steps: S1, identifying devices in a circuit diagram through a YOLOv8 model to obtain position information and category of each device; identifying a straight line segment in the circuit diagram through a probabilistic Hough transform algorithm to obtain a starting point coordinate, an end point coordinate and an orientation corresponding to the straight line segment; and S2, generating corresponding text description information according to the position information, the category, the starting point coordinate, the end point coordinate and the orientation. According to the method, by effectively integrating multi-modal information and combining image and text data, comprehensive understanding of a circuit diagram is provided, the recognition accuracy and robustness are improved, even if a single component has a recognition error, the influence of noise on the whole model can still be reduced through final information fusion, and the recognition accuracy and robustness are improved. Therefore, misjudgment and missed judgment in recognition are reduced, and the recognition accuracy of the element and the connection relation is remarkably improved.

The invention discloses a method for automatically generating a circuit based on AI, and belongs to the field of circuit design, and the method comprises the steps: obtaining a design index; the method comprises the following steps of: acquiring design indexes, capturing a dependency relationship among the design indexes by utilizing an attention mechanism, extracting features by utilizing a multi-layer Transform structure to obtain an overall structure and advanced feature representation of a circuit, and matching the advanced feature representation with a standard circuit netlist template based on the overall structure of the circuit to obtain a current circuit structure; simulating the current circuit structure to obtain a simulation report, and extracting error information from the simulation report; and correcting the current circuit structure based on the error information, simulating the corrected circuit structure again, circulating until no error exists in the simulation report, and outputting a circuit schematic diagram and a simulation result. The method solves the problems that an existing method generally has limitation, and automatic design of a complex circuit is difficult to quickly and flexibly carry out.

The invention discloses a VLSI congestion prediction method and device based on dual multi-modal fusion, and a storage medium. The method comprises the steps of 1, obtaining layout information and netlist information of a to-be-predicted circuit; 2, constructing two-dimensional layout features based on grids and netlist features based on heterogeneous graphs according to the layout information and the netlist information; and step 3, inputting the two-dimensional layout features and the netlist features into the congestion prediction model to obtain a congestion map of the circuit to be predicted. According to the VLSI congestion prediction method and device based on dual multi-modal fusion and the storage medium provided by the invention, a high-quality and high-precision congestion prediction result can be quickly obtained in a complex large-scale integrated circuit design, layout is guided to realize wiring optimization, and wiring congestion is effectively reduced.

The invention provides a digital-analog hybrid simulation method and device.The method comprises the steps that a simulation modeling file is generated according to design information of an analog circuit of a chip, and the simulation modeling file comprises a digital netlist, device library configuration, device mapping configuration, simulation control parameters, simulation signal variables and digital-analog interface conversion rules; and performing digital circuit simulation according to the design information of the digital circuit of the chip and the simulation modeling file, and generating a digital-analog hybrid simulation result of the chip. According to the method provided by the invention, the compatibility between digital-analog hybrid simulation tools can be improved.

The invention provides a chip logic function verification method, computer equipment, a program product and a medium. The chip logic function verification method comprises the following steps: obtaining a division scheme of a back-end design for each sub-module of a chip, so that the chip is re-divided into a plurality of to-be-verified modules; obtaining an RTL design scheme corresponding to the to-be-verified module; keeping the port of the to-be-verified module unchanged, and obtaining a gate-level netlist corresponding to the RTL design scheme; physical implementation of the to-be-verified module is carried out through the gate-level netlist and an EDA tool, and a design netlist after physical implementation is obtained; according to the design netlist, obtaining the time sequence information of each to-be-verified module after the time sequence convergence and the first time delay from the port of each to-be-verified module to the target register, and respectively subtracting the first time delay from the preset time delay to mark the port of each to-be-verified module so as to perform logic function verification with the time sequence information on the to-be-verified module. According to the scheme, optimization of manpower and calculator resources in the whole design process can be achieved, and the efficiency of chip logic function verification is improved.

The invention discloses a combinational logic clustering optimization method and system based on reinforcement learning. The method comprises the following steps: S1, counting fan-out information of registers and combinational logic units in a circuit netlist; s2, according to the fan-out information, screening out registers and combinational logic units of which the fan-out quantity is greater than a first preset threshold and the worst time sequence path time sequence violation value of the output signal is smaller than a second preset threshold, and generating a target unit list; s3, acquiring fan-out combinational logic information of each unit in the target unit list; s4, on the basis of the fan-out combinatorial logic information, clustering operation is carried out on fan-out logic units on the basis of a reinforcement learning algorithm; s5, after logic clustering is completed, revising the netlist of the circuit; after the revision is completed, carrying out equivalence check; and S6, rearranging and wiring the circuit according to the modified netlist. The method can effectively reduce key path delay, optimizes circuit performance, and is especially suitable for large-scale integrated circuit design.

The invention provides an integrated circuit model verification method and system, computer equipment and a storage medium. The method comprises the steps that parameters in a model library are analyzed through a script, and model parameters needed by verification are automatically extracted; a standard configuration file format is obtained, the model parameters are loaded into a standard configuration file, and a simulation configuration file is generated; obtaining netlist file formats required by different simulators, and generating netlist files which comprise output instructions and are adaptive to different simulators in batches according to the simulation configuration file; calling each simulator to execute the corresponding netlist file for simulation, and outputting an intermediate file; analyzing the numerical data in the intermediate file, and generating a standard format file; and comparing the standard format files generated by different simulators to obtain a verification result. According to the scheme, batch parameter configuration, netlist generation, simulation execution and result processing of the integrated circuit model can be realized, so that the model verification efficiency is improved.