32 results about "Electronic circuit design" patented technology

A method and system for parasitic extraction in semiconductor layouts using spatial localization and point reduction, thereby improving efficiency of predictive models for identifying parasitic capacitance in electronic circuit design. Candidate physical layouts are generated from electrical design. Transistors and wiring are spatially modeled as three-dimensional structures. Geometrical points are identified from the three-dimensional structures being modeled and used as nodes in a neural network. A subset of the nodes is selected, and the subset is further limited to a limited region surrounding the given node to be evaluated. Nodes can have weighting based on relative geometrical position. Parasitic extraction is performed on the limited number of nodes for efficient evaluation of candidate layouts.

The present disclosure describes systems and methods for generating a superconducting electronic circuit design. The system includes a memory and a processor. The processor simulates a superconducting electronic circuit design using a first process variation to produce a first score and simulates the superconducting electronic circuit design using a second process variation to produce a second score. The processor, in response to determining that the first score is lower than the second score, simulates the superconducting electronic circuit design using the first process variation and a first design variation to produce a third score and simulates the superconducting electronic circuit design using the first process variation and a second design variation to produce a fourth score. The processor updates the superconducting electronic circuit design using the first process variation and the first design variation in response to determining that the third score is higher than the fourth score.

The invention discloses a temperature isolation sampling circuit, and relates to the field of electronic circuit design, and the circuit comprises a triangular wave circuit which generates a triangular wave with a fixed period according to a threshold value comparison result in a capacitor charging and discharging mode; the temperature sampling circuit is used for comparing the sampling voltage which is output by the thermistor voltage division circuit and changes along with the temperature with the triangular wave and outputting a PWM (Pulse Width Modulation) square wave signal of which the duty ratio changes along with the temperature; and configuring an optocoupler device to work in a switching state based on a non-linear region, and transmitting the PWM square wave signal to an isolation output circuit at a low-voltage side to realize electrical isolation transmission. The device supports electrical isolation and adapts to high-voltage occasions, and the isolation voltage range depends on selected isolation elements; according to the invention, the PWM is used for transmitting the temperature signal, when the temperature signal is interfered by an electromagnetic environment, the influence on the level amplitude does not change the duty ratio, and in addition, the cost of the device is also reduced.

The invention relates to the field of electronic circuit design, and discloses an anti-reverse connection power-on soft start circuit and method, which can realize dual protection functions of anti-reverse connection and soft start and improve the safety and reliability of the circuit. The circuit is simple in design and easy to implement, and the manufacturing cost can be reduced; moreover, the anti-reverse connection soft start circuit can cut off the power supply quickly when detecting that the polarity of the power supply is wrong, thereby preventing the current from flowing reversely, improving the safety of the circuit, and prolonging the service life of the circuit.

A, preferably computer-implemented, method of verifying a design of an electronic circuit, comprising the steps of: prompting a large language model, LLM, with a design description in a machine-readable form, for example a hardware description language, HDL, for the LLM to provide one or more expressions specifying an intended functioning of the design in a natural language, prompting the same or another LLM with the one or more expressions for the LLM to provide one or more properties of the design in a machine-readable property description, for example a hardware verification language, HVL.

The present application belongs to the technical field of electronic circuit design, and specifically relates to an electronic circuit intelligent design method based on Internet of Things technology, which comprises the following steps: collecting real-time state data of an electronic circuit design environment based on Internet of Things sensing technology, and performing data processing on the collected real-time state data; introducing a design rule library and a performance target constraint set to map the real-time design state data to a decision space, and determining an electronic circuit design under a current multi-dimensional state vector; performing joint analysis on the multi-dimensional state vector and the performance index response relationship based on the electronic circuit design under the current multi-dimensional state vector; and dynamically adjusting parameters in the multi-dimensional state vector according to the joint analysis result, thereby realizing adaptive optimization of the electronic circuit.

This application relates to the field of electronic circuit design technology, and in particular to a PCB layout optimization method suitable for signal transmission. This method acquires manufacturer-specific process capability parameters, constructs a manufacturing disturbance model including conductor geometric deviations, dielectric non-uniformity, and interlayer alignment errors, and embeds an electromagnetic simulation engine to form a dynamic signal integrity analysis model. Based on this, an adaptive layout constraint rule set is generated, driving the layout and routing algorithm to perform manufacturing robustness-oriented automatic routing. This solves the problem of signal integrity degradation in high-speed signal links on PCBs due to manufacturing fluctuations, pre-compensating for manufacturing-introduced non-ideals during the design phase, and improving the first-pass success rate and signal performance consistency of high-speed PCBs.

The invention discloses a trigger instruction configuration system, method and device and a storage medium, and relates to the field of chip manufacturing and chip testing, and the system comprises a signal sampling module which is used for obtaining all sequential logic signals of a to-be-tested electronic circuit design; the filtering execution module is used for acquiring an associated sequential logic signal related to a trigger condition in all sequential logic signals; the trigger generation module is used for generating a trigger instruction if it is determined that the associated sequential logic signal meets the trigger condition; and the debugging function module is used for executing debugging operation according to the triggering condition. According to the technical scheme provided by the embodiment of the invention, the configuration generation of the trigger instruction after the design compiling of the electronic circuit to be tested is realized, the configuration flexibility of the trigger signal is improved, meanwhile, the compiling process after the trigger signal is appointed is avoided, the configuration efficiency of the trigger instruction is improved, and the test time of the design of the electronic circuit to be tested is greatly saved.

The present disclosure provides a file processing method and apparatus a, which may obtain a first electronic circuit design file, wherein the first electronic circuit design file has an XML format, the first electronic circuit design file is converted to a second electronic circuit design file having a JSON format based on a conversion rule associating a first XML tag corresponding to an electronic circuit design element with a JSON attribute corresponding to the same electronic circuit design element, and generate an electronic circuit design based on the second electronic circuit design file using an electronic design automation (EDA) tool.

The invention belongs to the technical field of electronic circuit design, and discloses a differential signal Fanout structure for improving the integrity of a high-speed signal, and the structure comprises a PCB substrate; the differential signal pair is arranged on the PCB substrate, the differential signal pair comprises a P signal wire and an N signal wire, and the P signal wire and the N signal wire are respectively used for connecting chip pins; and a ground shield unit. By adopting layered fan-out and large-spacing decoupling design, crosstalk of high-speed differential signals is remarkably reduced, the limitation that tight coupling wiring must be conducted on the same layer in a traditional Fanout structure is broken through, P signals and N signals are arranged on the surface layer and the inner layer of a PCB respectively, and therefore the signal transmission efficiency is improved. By means of isolation of a vertical space, maximization of horizontal projection spacing is achieved (a decoupling spacing area is formed), inter-line coupling capacitance is remarkably reduced, far-end crosstalk is remarkably reduced through the structure, and the signal-to-noise ratio and eye pattern opening of a high-speed link are improved.

A system and method for power estimation for an electronic circuit design is disclosed. The method comprises receiving a request for performing power estimation for a first electronic circuit design of a first electronic device, wherein the request is indicative of one or more first nets in the first electronic circuit design. Further, one or more first attributes associated with at least one of the first nets in the first electronic circuit design are determined from the request based on the one or more first attributes of the first net, a capacitance model corresponding to the first net is identified, from a plurality of capacitance models stored in a database. The capacitance model of the first net is further used to perform the power estimation for the first electronic circuit design, and a power report file is generated based on the power estimation on an output device.

A method for manufacturing an electronic device comprising a non-planar layered item (10) having a non-planar electronic circuit (20) on top of it, wherein the planar electronic circuit (20') is designed to become a non-planar electronic circuit (20) after a molding process, and for each surface mount component (22), an optimal adhesive distribution is defined by determining a first load induced on the bond between the surface mount component and the planar layered item, and a second load induced on the portion of a conductive track located around a local curing area of ​​the planar layered item to which at least one adhesive is applied, wherein the optimal adhesive distribution is selected to obtain a bond having a first fracture threshold greater than the first load and to produce a second load below a predetermined second fracture threshold of the conductive track,

The invention discloses a gated clock conversion method and device, electronic equipment and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that each gated clock unit in electronic circuit design is obtained, and each gated clock unit is configured in each field programmable logic gate array; obtaining a truth table of each gated clock unit according to the logic expression of each gated clock unit, and splitting the truth table into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with an inconstant output result; and obtaining a sub-logic expression after the clock signal is deleted according to the target sub-truth table, and obtaining an enable signal of the sequential logic device according to the sub-logic expression. According to the technical scheme provided by the embodiment of the invention, not only is the conversion duration of the gated clock shortened and the logic comprehensive performance of the electronic circuit design greatly improved, but also the conversion complexity of the gated clock is reduced.

A computer-implemented method for evaluating power consumption of an electronic circuit design including at least one logic gate is disclosed. The method includes receiving one or more data files describing an electronic circuit design, describing waveform data describing signal activity describing a logic gate used in the electronic circuit design, and describing power consumption values of internal cells of the logic gate of the electronic circuit design (701). Waveform data is extracted from one or more data files describing signal activity at a main input of the electronic circuit design and describing outputs of registers and memories of the electronic circuit design (702). Simulation of the logic gate is performed using the extracted waveform data to generate analog waveform data describing analog logic transitions of the internal cells of the logic gate (703), and event-based evaluation of power consumption of the electronic circuit design is performed based on the extracted waveform data, the analog waveform data, and the power consumption value (704).

Methods and systems for detecting problematic floating nodes in an electronic circuit or electronic circuit design are presented. Floating node detection methods and systems use graph crawling techniques in combination with machine learning to perform an exhaustive search for floating nodes without requiring the use of expensive commercial simulation tools.

The application discloses a multi-channel output control multiplexer, and relates to the field of electronic circuit design, which can facilitate the cooperative use of multiple groups of output data in signal transmission, and specifically comprises a signal input control device, a selection device and a signal output control device. The principle is that the signal input control device analyzes M input enable signals into N input control signals, which are used for controlling the gating state of N input control units of the selection device; the signal output control device analyzes M output enable signals into N output control signals, which are used for controlling the gating state of N output control units of the selection device; M and N are positive integers greater than 1, and N is less than or equal to 2M. The selection device is connected with input signals at the input end of the N input control units, and the output ends of the N input control units are connected with each other and connected in parallel to the input ends of the N output control units, and the output ends of the N output control units are output signals.

The invention relates to the technical field of electronic circuit design, in particular to a PCB layout optimization method suitable for signal transmission, and the method comprises the steps: building a manufacturing disturbance model comprising conductor geometric deviation, medium heterogeneity and interlayer alignment error through obtaining the specific process capability parameters of a manufacturer, and optimizing the layout of the PCB; and an electromagnetic simulation engine is embedded to form a dynamic signal integrity analysis model, a self-adaptive layout constraint rule set is generated based on the model, and a layout wiring algorithm is driven to execute manufacturing robustness-oriented automatic wiring. Therefore, the problem that the signal integrity of a high-speed signal link of the PCB is degraded due to manufacturing fluctuation is solved, non-ideality introduced by manufacturing is compensated in advance in the design stage, and the one-time board throwing success rate and the signal performance consistency of the high-speed PCB are improved.

The invention relates to a tool for designing an electronic circuit comprising at least two electronic packages and a control unit, said design tool being notable in that: each electronic package comprises a functional electronic circuit configured to transform a functional input signal into a functional output signal; the at least two electronic packages are configured to interconnect so as to form an overall functional electronic circuit by electrical connection of the functional electronic circuits of said at least two electronic packages; the control unit is configured to generate a digital model of the overall functional electronic circuit. Abstract figure: Figure 6

The invention relates to the technical field of electronic circuit design and system-level power supply planning, and particularly discloses a current distribution tree dynamic planning and visualization system and method.The system integrates an electrical constraint intelligent tree data model and a dynamic interpolation algorithm, an optimal father node is screened through a multi-objective scoring function, and the optimal father node is optimized; by combining recursive backtracking adjustment and prospective redistribution, global automatic rebalance after new node insertion is realized, a dual-visual interface of an editable tree design view and a real-time linkage mulberry-based graph is adopted, current flow, margin distribution and bottleneck positions are visually presented, user interactive operation and immediate feedback are supported, and the method is suitable for large-scale popularization and application. The method has the function of exporting the standardized Excel project document by one key, and ensures the consistency of the design and the deliverable. According to the system, manual distribution adjustment of several hours is shortened to a second level, electrical constraint compliance is strictly guaranteed, design transparency and team cooperation efficiency are improved, design knowledge precipitation and reuse are achieved, and the system can adapt to multiple fields such as chips, PCBs and electric vehicle power distribution.

The invention relates to the technical field of electronic circuit design and simulation, and provides a circuit maximum load calculation method and system based on load regulation, and the method comprises the steps: obtaining an input excitation waveform and a target output threshold value in response to a circuit simulation calculation request, and initializing an iteration counter and a sample set according to an initial load value inputted by a user; predicting a target load value of next simulation based on existing data pairs in the sample set; performing simulation calculation on the target load value to obtain an output response value of the target node, adding the load value and the corresponding output response value as a data pair into a sample set, and updating an iteration counter; and outputting a maximum load calculation result of the circuit when a convergence condition is met. Through a double-layer prediction mode combining linear interpolation and least square polynomial fitting, high-precision load prediction and self-adaptive calculation are carried out under a limited sample condition; the problem of misjudgment or local fluctuation of the maximum load point is effectively avoided aiming at the complex condition that the output response is non-monotonous along with the load change.

The invention relates to a thermocouple signal simulation circuit design method, and belongs to the technical field of electronic circuit design. The method comprises a power supply module, an input module, a subtraction module, an isolation amplification module and a signal generation module. The power supply module provides two groups of + / -5V power supplies and 1.5 V voltage-stabilized power supplies which are isolated from each other; an input instruction signal of the circuit is a 4-20mA current signal or a 1-5V voltage signal; through the input module, instruction signals are uniformly converted into 1-5V voltage signals; after the signal is processed by the subtraction module and the isolation amplification module, a-0.181-1.118 V floating differential signal is obtained; and finally, the signal generation module amplifies the differential signal and outputs a thermocouple signal of-6 to 50 mV corresponding to the temperature measurement range of-200 to 1200 DEG C. By adopting the isolation power supply and the isolation module, a floating high-fidelity thermocouple analog signal is generated.

This disclosure provides a receiving circuit applicable to various high-speed interface standards, and is applied in the field of electronic circuit design technology. The method includes converting an input signal into a common-mode voltage using a modulation resistor circuit, comparing the common-mode voltage with a reference voltage in a common-mode voltage detection circuit, and outputting the input signal after passing through a folded amplifier and a first common-source amplifier if the common-mode voltage is less than the reference voltage; otherwise, outputting the input signal after passing through a second common-source amplifier. Thus, the receiving circuit can still operate normally even when the common-mode voltage changes from 0 volts to the power supply voltage, exhibiting constant transconductance, the ability to detect small swings, low noise, and a low bit error rate.

The invention discloses an electronic circuit design simulation verification method and device, electronic equipment and a storage medium, and relates to the field of chip manufacturing and chip simulation verification, and the method comprises a management control module which is used for managing trigger conditions in a signal processing module and a condition judgment module; the signal processing module is used for acquiring a key signal designed by the electronic circuit to be tested through the key signal acquisition channel and sending a target key signal related to a trigger condition to the condition judgment module; and the condition judgment module is used for sending a control instruction to the hardware simulation system to control the running state of the hardware simulation system if it is determined that the target key signal meets the triggering condition. According to the technical scheme provided by the embodiment of the invention, the structural complexity of the electronic circuit design to be tested is reduced, the dynamic configuration of the trigger condition is realized, the recompilation of the whole electronic circuit design to be tested is avoided, the verification time of the circuit design is saved, and the simulation verification efficiency of the electronic circuit design to be tested is improved.

The invention belongs to the field of electronic circuit design, and particularly relates to a redundancy switching circuit based on a D trigger, which is used for realizing reliable switching between redundancy controllers. According to the circuit, by utilizing the characteristic that the first port and the second port of the D trigger are always in a high-low level mutual exclusion state, it is ensured that output signals of the A controller and the B controller cannot be in a high level or a low level at the same time under different conditions, and therefore system conflicts or misoperation is avoided. The method is suitable for occasions needing redundancy control, such as the fields of aerospace, industrial automation and the like.

A method and system for managing gate level simulation of an electronic circuit is provided. The method includes identifying at least one circuit topology from a plurality of circuit topologies in an electronic circuit design based on a netlist and a timing data file. Further, one or more non-critical pins are determined from the identified circuit topologies based on a delay corresponding to each pin in the identified circuit topologies. A modified timing data file is generated based on the determination of the one or more non-critical pins. In the modified timing data file, the delay associated with each non-critical pin is set to zero. The method can further include performing a gate level simulation based on the modified timing data file.

The invention belongs to the technical field of electronic circuit design, and relates to an interface circuit system for an electrostatic coupling fringe electric field sensor, which is applied to monitoring of abrasive particles and fringe electric field signals in a lubricating oil loop, and comprises an IV conversion circuit, an isolation level circuit, a low-frequency processing channel and a high-frequency processing channel, the low-frequency processing channel comprises a low-pass filter circuit and a reverse-phase amplification circuit, and the high-frequency processing channel comprises a band-pass filter circuit and an amplitude conversion circuit; the input end of the IV conversion circuit is connected with the induction electrode and is used for converting a weak charge signal generated by the induction electrode into a voltage signal; the low-frequency processing channel is used for filtering high-frequency noise and amplifying a low-frequency electrostatic signal generated by the abrasive particles; the high-frequency processing channel is used for extracting and rectifying high-frequency fringe electric field signals generated after excitation is applied to the excitation electrode and extracting amplitude characteristics. Effective separation of high-frequency and low-frequency signals can be realized, and the signal-to-noise ratio is remarkably improved.

The application relates to the technical field of electronic circuit design and system-level power supply planning, and particularly discloses a current distribution tree dynamic planning and visualization system and method. The system combines an intelligent tree-shaped data model of electrical constraints and a dynamic interpolation algorithm, filters optimal parent nodes through a multi-target scoring function, realizes global automatic rebalancing after new node insertion in combination with recursive backtracking adjustment and forward-looking redistribution, adopts an editable tree-shaped design view + real-time linkage Sangui diagram dual-visualization interface, intuitively presents current flow, margin distribution and bottleneck positions, supports user interactive operation and instant feedback, has the function of one-key export of standardized Excel engineering documents, and ensures consistency of design and delivery. The system shortens manual distribution adjustment of hours to seconds, strictly guarantees compliance of electrical constraints, improves design transparency and team collaboration efficiency, realizes design knowledge sedimentation and reuse, and can be adapted to multiple fields such as chips, PCBs and electric vehicle power distribution.

One aspect of the invention relates to an electronic circuit (1) designed to electrically connect a plurality of cells (21, 22) of a battery (3) to a cell supervision circuit (4), the circuit (1) comprising: - for each cell (21, 22), a first conductor track (6) designed to be connected to a positive terminal (2+) and to the cell supervision circuit (4), and - for all the cells (21, 22), a second conductor track (12) designed to be connected to the negative terminals (2-) of the cells (21, 22) and to the cell supervision circuit (4); - each first conductor track (6) comprises a first transistor (7) connected to a current control loop (8) that is designed, when the input current of the first transistor (7) is greater than a first reference value, to limit an output current of the first transistor (7).

The application discloses a kind of adjustable adaptive bias structure, applied to electronic circuit design field, including mainly by adjustable attenuation unit The adjustable power distribution module, mainly by capacitor, transistor differential pair and current mirror The adjustable power-current conversion module, mainly by transistor Current subtraction circuit module, output is the bias voltage of radio frequency amplifier or other nonlinear active device.The application is applicable to CMOS process, also applicable to other silicon-based or compound semiconductor process, utilize the difference of different device radio frequency power-direct current conversion characteristics, and through digital or analog signal control, realize that the adjustment direction and adjustment degree controllable power adaptive bias voltage, to reach the linearization compensation of radio frequency amplifier or system with different power characteristics.