62 results about "Electronic circuit design" patented technology

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

A method comprises creating an electronic circuit design having a plurality of electronic components, defining a fault condition imposable during a simulation of the electronic circuit design, and generating a simulation model based on the electronic circuit design. The method also comprises generating a simulation fault model representing the fault condition and executing a simulation of the simulation model to simulate operation of the electronic circuit design. During the execution of the simulation, the method comprises controlling the simulation fault model to begin an imposition of the fault condition within the simulation model, simulating circuit behavior of the simulation model in response to the imposition of the fault condition, controlling the simulation fault model to cease the imposition of the fault condition within the simulation model, and simulating circuit behavior of the simulation model in response to the cessation of the imposition of the fault condition.

The invention relates to the field of electronic circuit design, and discloses a numerical control crystal oscillator circuit with low noise and high stability. According to the circuit, a two-stage voltage regulator is adopted to suppress power supply noise, wide-range high-precision frequency regulation is realized through thick and thin capacitor array regulation, oscillation signal quality is ensured through automatic detection feedback and external programming double-loop control, and a special oscillation starting circuit is arranged to accelerate the starting process of a crystal oscillator. Meanwhile, targeted optimization is carried out on a core circuit and layout in the loop, and noise and distortion are further reduced. The digital controlled oscillator can effectively solve the problems that an existing digital controlled oscillator scheme is narrow in frequency modulation range, large in phase noise and the like, the characteristics of low noise, high stability, rapid starting and the like are achieved, an excellent frequency reference is provided for a wireless communication and high-precision timing system, and the digital controlled oscillator has remarkable practical value.

A method and system for parasitic extraction in semiconductor layouts using spatial localization and point reduction, thereby improving efficiency of predictive models for identifying parasitic capacitance in electronic circuit design. Candidate physical layouts are generated from electrical design. Transistors and wiring are spatially modeled as three-dimensional structures. Geometrical points are identified from the three-dimensional structures being modeled and used as nodes in a neural network. A subset of the nodes is selected, and the subset is further limited to a limited region surrounding the given node to be evaluated. Nodes can have weighting based on relative geometrical position. Parasitic extraction is performed on the limited number of nodes for efficient evaluation of candidate layouts.

The invention relates to the technical field of electronic circuit design, and discloses a hardware overcurrent protection design circuit of a motor controller, which comprises a driving signal input module comprising a three-phase independent half-bridge driving chip and a three-phase bridge arm N-channel MOS (Metal Oxide Semiconductor) tube, a current detection module consisting of a three-phase sampling branch, two N-channel MOS tubes connected in series in each phase and a sampling resistor, a sampling signal is amplified by the operational amplifier, the voltage comparison module comprises a first comparator and a second comparator, the logic control module comprises an AND gate and a seventh N-channel MOS tube, and the power supply control module comprises a P-channel MOS tube. According to the hardware overcurrent protection design circuit of the motor controller, the overcurrent protection value of the phase line load current is designed through hardware, and when the actual load reaches the threshold value, the hardware immediately responds to disconnect the power supply of the three-phase independent half-bridge driving chip of the controller, so that continuous output overload is avoided, and the reliability of the motor controller is improved. And overload or overvoltage damage of three-phase power bridge circuit components is caused.

The present disclosure describes systems and methods for generating a superconducting electronic circuit design. The system includes a memory and a processor. The processor simulates a superconducting electronic circuit design using a first process variation to produce a first score and simulates the superconducting electronic circuit design using a second process variation to produce a second score. The processor, in response to determining that the first score is lower than the second score, simulates the superconducting electronic circuit design using the first process variation and a first design variation to produce a third score and simulates the superconducting electronic circuit design using the first process variation and a second design variation to produce a fourth score. The processor updates the superconducting electronic circuit design using the first process variation and the first design variation in response to determining that the third score is higher than the fourth score.

A system performs optimization of parameters of a circuit design. The system accesses a model configured to receive design variables of the circuit design and predict a measure of quality of the circuit design. For multiple coverage levels, the system generates samples representing a values of design parameters. For each sample, the system predicts the quality of the sample using the model. The system selects a subset of samples having a predicted quality that exceeds a target. The system performs simulations of the selected subset of samples. The system maintains a moving target and drops samples encountering worse results before all simulations finish. The system performs incremental training of the model based on results of the simulations of the selected subset of samples. The system also decides whether to enter the next coverage level based on the simulation results and the moving target.

Embodiments include herein are directed towards a method for electromigration analysis of a circuit design. Embodiments may include performing a first transient simulation of an electronic design using one or more electronic design tools. Embodiments may further include storing a level of current associated with one or more generic passive device tap points. Embodiments may also include identifying a resistor capacitor (RC) model for one or more generic passive devices using the one or more electronic design tools and performing a second transient simulation for the one or more generic passive devices. Embodiments may further include analyzing a current density obtained from the first and second transient simulation to obtain a single current density map.

The invention discloses a temperature isolation sampling circuit, and relates to the field of electronic circuit design, and the circuit comprises a triangular wave circuit which generates a triangular wave with a fixed period according to a threshold value comparison result in a capacitor charging and discharging mode; the temperature sampling circuit is used for comparing the sampling voltage which is output by the thermistor voltage division circuit and changes along with the temperature with the triangular wave and outputting a PWM (Pulse Width Modulation) square wave signal of which the duty ratio changes along with the temperature; and configuring an optocoupler device to work in a switching state based on a non-linear region, and transmitting the PWM square wave signal to an isolation output circuit at a low-voltage side to realize electrical isolation transmission. The device supports electrical isolation and adapts to high-voltage occasions, and the isolation voltage range depends on selected isolation elements; according to the invention, the PWM is used for transmitting the temperature signal, when the temperature signal is interfered by an electromagnetic environment, the influence on the level amplitude does not change the duty ratio, and in addition, the cost of the device is also reduced.

The invention relates to the field of electronic circuit design, and discloses an anti-reverse connection power-on soft start circuit and method, which can realize dual protection functions of anti-reverse connection and soft start and improve the safety and reliability of the circuit. The circuit is simple in design and easy to implement, and the manufacturing cost can be reduced; moreover, the anti-reverse connection soft start circuit can cut off the power supply quickly when detecting that the polarity of the power supply is wrong, thereby preventing the current from flowing reversely, improving the safety of the circuit, and prolonging the service life of the circuit.

A, preferably computer-implemented, method of verifying a design of an electronic circuit, comprising the steps of: prompting a large language model, LLM, with a design description in a machine-readable form, for example a hardware description language, HDL, for the LLM to provide one or more expressions specifying an intended functioning of the design in a natural language, prompting the same or another LLM with the one or more expressions for the LLM to provide one or more properties of the design in a machine-readable property description, for example a hardware verification language, HVL.

The present application belongs to the technical field of electronic circuit design, and specifically relates to an electronic circuit intelligent design method based on Internet of Things technology, which comprises the following steps: collecting real-time state data of an electronic circuit design environment based on Internet of Things sensing technology, and performing data processing on the collected real-time state data; introducing a design rule library and a performance target constraint set to map the real-time design state data to a decision space, and determining an electronic circuit design under a current multi-dimensional state vector; performing joint analysis on the multi-dimensional state vector and the performance index response relationship based on the electronic circuit design under the current multi-dimensional state vector; and dynamically adjusting parameters in the multi-dimensional state vector according to the joint analysis result, thereby realizing adaptive optimization of the electronic circuit.

This application relates to the field of electronic circuit design technology, and in particular to a PCB layout optimization method suitable for signal transmission. This method acquires manufacturer-specific process capability parameters, constructs a manufacturing disturbance model including conductor geometric deviations, dielectric non-uniformity, and interlayer alignment errors, and embeds an electromagnetic simulation engine to form a dynamic signal integrity analysis model. Based on this, an adaptive layout constraint rule set is generated, driving the layout and routing algorithm to perform manufacturing robustness-oriented automatic routing. This solves the problem of signal integrity degradation in high-speed signal links on PCBs due to manufacturing fluctuations, pre-compensating for manufacturing-introduced non-ideals during the design phase, and improving the first-pass success rate and signal performance consistency of high-speed PCBs.

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design layout and performing parasitic extraction on the electronic design layout. Embodiments may further include extracting an electromagnetic model from the electronic design layout and reconnecting at least one coupling capacitor associated with a net of the electromagnetic model. Embodiments may include performing a simulation including the reconnected at least one coupling capacitor.

The invention discloses a trigger instruction configuration system, method and device and a storage medium, and relates to the field of chip manufacturing and chip testing, and the system comprises a signal sampling module which is used for obtaining all sequential logic signals of a to-be-tested electronic circuit design; the filtering execution module is used for acquiring an associated sequential logic signal related to a trigger condition in all sequential logic signals; the trigger generation module is used for generating a trigger instruction if it is determined that the associated sequential logic signal meets the trigger condition; and the debugging function module is used for executing debugging operation according to the triggering condition. According to the technical scheme provided by the embodiment of the invention, the configuration generation of the trigger instruction after the design compiling of the electronic circuit to be tested is realized, the configuration flexibility of the trigger signal is improved, meanwhile, the compiling process after the trigger signal is appointed is avoided, the configuration efficiency of the trigger instruction is improved, and the test time of the design of the electronic circuit to be tested is greatly saved.

The present invention discloses an engine brake valve drive circuit and a shutdown implementation method, device, and medium, relating to the field of electronic circuit design. The circuit includes a pre-driver chip, a main control chip, and a power supply chip. The pre-driver chip includes a first pre-driver chip for connecting to the main MOSFET on the engine brake valve, and a second pre-driver chip connected to the sub-MOSFET corresponding to each engine brake valve; the main control chip includes a safety core and a functional core connected to the first pre-driver chip to implement high-side control, and a logic judgment component is provided between the safety core and the functional core and the first pre-driver chip, and the functional core is also connected to the second pre-driver chip to implement low-side control; the power supply chip and the safety core are both connected to the main power switch corresponding to the main MOSFET to implement on-off control of the main power switch. This application can effectively ensure vehicle driving safety.

The present disclosure provides a file processing method and apparatus a, which may obtain a first electronic circuit design file, wherein the first electronic circuit design file has an XML format, the first electronic circuit design file is converted to a second electronic circuit design file having a JSON format based on a conversion rule associating a first XML tag corresponding to an electronic circuit design element with a JSON attribute corresponding to the same electronic circuit design element, and generate an electronic circuit design based on the second electronic circuit design file using an electronic design automation (EDA) tool.

The invention discloses a high-precision, high-efficiency and low-power-consumption magnetic field imaging device and method, and belongs to the field of integrated electronic circuit design and automatic algorithms. The device part comprises 10 * 10 millimeter-scale packaged linear magnetic sensor zero-spacing arrays, output signals of each linear Hall magnetic field sensor are output to a self-adaptive magnetic field acquisition motion controller through a signal pin header, and are enabled and conducted through a 16-channel analog signal multiplexing module and a 16-channel digital signal chip selection enabling module in the controller; and reading detection data of the linear Hall sensor at the specified position. And meanwhile, a linear motor platform is designed to control the millimeter-level packaging linear magnetic sensor to move to a target area in a zero-spacing array manner according to different movement requirements. The method is partially combined with an adaptive magnetic field acquisition algorithm and a high-precision linear motor platform, so that high-precision magnetic field imaging of a local area can be finally realized while large-range efficient imaging can be realized.

The invention belongs to the technical field of electronic circuit design, and discloses a differential signal Fanout structure for improving the integrity of a high-speed signal, and the structure comprises a PCB substrate; the differential signal pair is arranged on the PCB substrate, the differential signal pair comprises a P signal wire and an N signal wire, and the P signal wire and the N signal wire are respectively used for connecting chip pins; and a ground shield unit. By adopting layered fan-out and large-spacing decoupling design, crosstalk of high-speed differential signals is remarkably reduced, the limitation that tight coupling wiring must be conducted on the same layer in a traditional Fanout structure is broken through, P signals and N signals are arranged on the surface layer and the inner layer of a PCB respectively, and therefore the signal transmission efficiency is improved. By means of isolation of a vertical space, maximization of horizontal projection spacing is achieved (a decoupling spacing area is formed), inter-line coupling capacitance is remarkably reduced, far-end crosstalk is remarkably reduced through the structure, and the signal-to-noise ratio and eye pattern opening of a high-speed link are improved.

A system and method for power estimation for an electronic circuit design is disclosed. The method comprises receiving a request for performing power estimation for a first electronic circuit design of a first electronic device, wherein the request is indicative of one or more first nets in the first electronic circuit design. Further, one or more first attributes associated with at least one of the first nets in the first electronic circuit design are determined from the request based on the one or more first attributes of the first net, a capacitance model corresponding to the first net is identified, from a plurality of capacitance models stored in a database. The capacitance model of the first net is further used to perform the power estimation for the first electronic circuit design, and a power report file is generated based on the power estimation on an output device.

A method for manufacturing an electronic device comprising a non-planar layered item (10) having a non-planar electronic circuit (20) on top of it, wherein the planar electronic circuit (20') is designed to become a non-planar electronic circuit (20) after a molding process, and for each surface mount component (22), an optimal adhesive distribution is defined by determining a first load induced on the bond between the surface mount component and the planar layered item, and a second load induced on the portion of a conductive track located around a local curing area of ​​the planar layered item to which at least one adhesive is applied, wherein the optimal adhesive distribution is selected to obtain a bond having a first fracture threshold greater than the first load and to produce a second load below a predetermined second fracture threshold of the conductive track,

The invention discloses a gated clock conversion method and device, electronic equipment and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that each gated clock unit in electronic circuit design is obtained, and each gated clock unit is configured in each field programmable logic gate array; obtaining a truth table of each gated clock unit according to the logic expression of each gated clock unit, and splitting the truth table into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with an inconstant output result; and obtaining a sub-logic expression after the clock signal is deleted according to the target sub-truth table, and obtaining an enable signal of the sequential logic device according to the sub-logic expression. According to the technical scheme provided by the embodiment of the invention, not only is the conversion duration of the gated clock shortened and the logic comprehensive performance of the electronic circuit design greatly improved, but also the conversion complexity of the gated clock is reduced.

A computer-implemented method for evaluating power consumption of an electronic circuit design including at least one logic gate is disclosed. The method includes receiving one or more data files describing an electronic circuit design, describing waveform data describing signal activity describing a logic gate used in the electronic circuit design, and describing power consumption values of internal cells of the logic gate of the electronic circuit design (701). Waveform data is extracted from one or more data files describing signal activity at a main input of the electronic circuit design and describing outputs of registers and memories of the electronic circuit design (702). Simulation of the logic gate is performed using the extracted waveform data to generate analog waveform data describing analog logic transitions of the internal cells of the logic gate (703), and event-based evaluation of power consumption of the electronic circuit design is performed based on the extracted waveform data, the analog waveform data, and the power consumption value (704).

Methods and systems for detecting problematic floating nodes in an electronic circuit or electronic circuit design are presented. Floating node detection methods and systems use graph crawling techniques in combination with machine learning to perform an exhaustive search for floating nodes without requiring the use of expensive commercial simulation tools.

The application discloses a multi-channel output control multiplexer, and relates to the field of electronic circuit design, which can facilitate the cooperative use of multiple groups of output data in signal transmission, and specifically comprises a signal input control device, a selection device and a signal output control device. The principle is that the signal input control device analyzes M input enable signals into N input control signals, which are used for controlling the gating state of N input control units of the selection device; the signal output control device analyzes M output enable signals into N output control signals, which are used for controlling the gating state of N output control units of the selection device; M and N are positive integers greater than 1, and N is less than or equal to 2M. The selection device is connected with input signals at the input end of the N input control units, and the output ends of the N input control units are connected with each other and connected in parallel to the input ends of the N output control units, and the output ends of the N output control units are output signals.

The invention relates to the technical field of electronic circuit design, in particular to a PCB layout optimization method suitable for signal transmission, and the method comprises the steps: building a manufacturing disturbance model comprising conductor geometric deviation, medium heterogeneity and interlayer alignment error through obtaining the specific process capability parameters of a manufacturer, and optimizing the layout of the PCB; and an electromagnetic simulation engine is embedded to form a dynamic signal integrity analysis model, a self-adaptive layout constraint rule set is generated based on the model, and a layout wiring algorithm is driven to execute manufacturing robustness-oriented automatic wiring. Therefore, the problem that the signal integrity of a high-speed signal link of the PCB is degraded due to manufacturing fluctuation is solved, non-ideality introduced by manufacturing is compensated in advance in the design stage, and the one-time board throwing success rate and the signal performance consistency of the high-speed PCB are improved.

The invention relates to a tool for designing an electronic circuit comprising at least two electronic packages and a control unit, said design tool being notable in that: each electronic package comprises a functional electronic circuit configured to transform a functional input signal into a functional output signal; the at least two electronic packages are configured to interconnect so as to form an overall functional electronic circuit by electrical connection of the functional electronic circuits of said at least two electronic packages; the control unit is configured to generate a digital model of the overall functional electronic circuit. Abstract figure: Figure 6

The invention relates to the field of artificial intelligence and electronic design automation, in particular to a DSL language-based circuit logic modeling and automatic generation method, which comprises the following steps of: 1, designing a DSL language based on a current trend; step 2, conversion from DSL to a circuit diagram; and step 3, generating and optimizing a circuit, wherein the step 1 comprises DSL grammar design and a DSL analyzer. According to the method, DSL grammar design is adopted, and a current-driven logic description mode is adopted; describing a hierarchical relation of the circuit by adopting a nested structure; series and parallel current flow directions are supported, and DSL codes are analyzed through a DSL analyzer and converted into a current trend graph; carrying out connection verification based on the current flow direction in combination with a circuit element library; the correctness of DSL codes is ensured by adopting lexical analysis and grammatical analysis, so that a current path is optimized, the electrical correctness is ensured, and finally, through circuit layout optimization, expression, analysis and automatic generation of circuit logic are realized, so that the intelligence and automation level of electronic circuit design is improved.

The invention relates to the technical field of electronic circuit design and signal processing, and discloses a high-voltage active low-frequency filter which comprises an input voltage end + HVIN and an output voltage end-HVOUT. The input filtering and preprocessing module is used for purifying, regulating and controlling an input signal and comprises an inductor L1 of which one end is connected with an input voltage end + HVIN and the other end is connected with one end of a resistor R1; one end of the resistor R1 is connected with one end of the inductor L1, and the other end is connected with one end of the capacitor C1 and one end of the resistor R4; one end of the capacitor C1 is connected with one end of the resistor R1, and the other end is grounded; one end of the resistor R4 is connected with one end of the resistor R1, and the other end is connected with one end of the capacitor C4 and one end of the resistor R2; according to the high-voltage active low-frequency filter, through collaborative design of the inductor L1, the triode Q52 and the resistor, the inductor L1 reduces obstruction of high-frequency impedance to current, the triode Q52 serving as an active device can dynamically adjust the conduction degree and is matched with the resistor to reasonably divide voltage and limit current, the adaptation capacity of a circuit to the current under different working conditions is effectively improved, and stable transmission of the current is guaranteed.