38results about How to "Increased hardware resources" patented technology

One or more processes are offloaded from one virtual machine running on one host computer to another virtual machine running on another host computer so that load balancing can be performed on a per process level and physical servers supporting the virtual machines can be more optimally utilized. Migrating one or more processes from a virtual machine running on a first host computer to a second host computer includes replicating the virtual machine on the second host computer, terminating the migrated processes from the virtual machine running on the first host computer, and terminating all user-level processes running on the replicated virtual machine other than the migrated processes.

A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.

The invention discloses a pipelined Montgomery modular multiplication operation method and a pipelined Montgomery modular multiplication operation device, relates to the technical field of data cryptography algorithms, adopts a pipelined mode to improve Montgomery modular multiplication algorithm performance, increases throughput of a single Montgomery modular multiplier, and consumes less hardware resources and area than a traditional method using a plurality of Montgomery modular multipliers under the condition of the same throughput. Therefore, the modular multiplication number in unit timeis increased by dozens of times, and the Montgomery modular multiplier has higher performance/resource ratio than a non-pipelined Montgomery modular multiplier. Meanwhile, the asymmetric key algorithm hardware using the pipelined Montgomery modular multiplier can achieve higher performance with fewer hardware resources, and the throughput of Montgomery modular multiplication operation of any length is improved.

In a packet transmission system including host apparatuses and a router which transfers a packet from host apparatuses in a first host group to host apparatuses in a second host group, each host apparatus in the first host group inserts in a packet an IP address and a link-layer address of a destination host apparatus in the second host group before transmitting the packet. When the router receives the packet, the router determines an output port connected to at least one host apparatus in the second host group including the destination host apparatus, based on the IP address of the destination host apparatus inserted in the packet, and transmits the received packet from the determined output port.

A method of and apparatus for efficiently communicating between a provider of video on demand services and a cable television subscriber. The communication is implemented using a message protocol specifically optimized to communicate between a multimedia application server and a set top subscriber box. The message format includes unique identifiers for addressing and synchronization to permit the multimedia application server to manage the communication process.

A reconfigurable scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected by reconfigurable high-speed serial links to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.

A vehicle control system has a main control apparatus, a plurality of relaying connector units, lower-level network lines provided in correspondence to the relaying connector units, and a plurality of electronic devices connected to the lower-level network lines. Moreover, the relaying connector unit monitors failure of the other relaying connector unit and upon detection of failure thereof, transmits an operation state transition request control signal, for transitioning the electronic apparatuses controlled by the other relaying connector unit to safe operation states which have been pre-defined for each of the electronic apparatuses, from an other line connection portion to the electronic apparatuses.

The invention provides a network communication system based on a TCP/IP communication protocol. The network communication system comprises a server and at least one client side; the server is used for creating a dynamic chain table; the dynamic chain table comprises a head node and a plurality of child nodes; starting from the head node, the nodes are sequentially connected in series through a pointer field next, so that the dynamic chain table is formed; the server judges whether a communication event is triggered at the client side or not by calling an epoll_wait function; if so, the server quits the epoll_wait function, and traverses and processes the communication event; and if not, a blocking mode is adopted to wait for the triggering of the communication event at the client side. According to the network communication system disclosed by the invention, by utilization of an epoll server communication model, online and offline states of the client side, communication between the client side and the server, and communication between the client side and another client side can be realized through the dynamic chain table; the defect that large-scale user connection cannot be satisfied by a general server can be solved; and furthermore, the memory utilization rate of the server is increased by utilization of computer hardware resources.

A computing system includes a central processing unit (CPU), a first direct memory access (DMA) controller, a first bus, a memory module inserted in a first dual inline memory module (DIMM) slot, and a storage device installed on a second DIMM slot. The storage device includes a storage module, a second bus, a memory unit, an interface control unit, and a second DMA controller. The CPU sets up the first and the second DMA controllers to perform data transmission. The first DMA controller controls a first data transmission between the memory module and the memory unit through the first and the second buses, and the second DMA controller controls a second data transmission between the memory unit and the storage module, with the interface control unit, through the second bus. The disclosure further provides a data transmission method of the computing system.

A method utilizes event-driven reoptimization to reallocate one or more logical partitions within a pool of logically-partitioned data processing systems in a logically-partitioned computing environment in response to detection of a system event that is likely to increase or decrease the collective resource demands of logical partitions resident in a logically-partitioned computing environment. The reoptimization may be used to consolidate logical partitions on fewer processor nodes to improve the potential for powering down hardware resources and thereby reduce power consumption.

A method and a system are disclosed for allocating program components to distributed control devices of a control system, comprising the following steps: a) creating at least two program modules, which each comprise program components, data interfaces and performance parameters for the definition of a performance requirement; b) linking the program modules via data connections between the data interfaces to form a control program; c) ascertaining available control devices and the performance capability thereof in the control system; d) ascertaining possible allocations of the program modules and verification by a comparison between the requirement and performance capability; c) selecting and allocating a verified allocation; and f) configuring data exchange channels between the distributed control devices.

The invention discloses a multi-aircraft coordinated combat simulation control apparatus. The apparatus comprises a power supply control module, an emission control module, a software loading control module and an address bit control module, wherein the power supply control module provides power supply control for aircrafts; the emission control module obtains discrete magnitude signals from a power supply input end and emits control instruction signals through a delay relay and switches to realize emission control of the aircrafts; the software loading control module performing software loading on simulation systems I, II and III; and the address bit control module is connected with the corresponding switches and carries out address bit control thorough controlling whether the switches are connected with an address loop. The apparatus substantially reduce preparation time before a test, the workload, operation personnel and simulation time, and ensures what is urgently needed for the test.

The invention discloses a method for improving the universality of a computing unit in a Polar code decoding process. An h function circuit composed of an adder and an auxiliary circuit of the adder is adopted; when the log-likelihood ratio is calculated, the f function function is achieved as much as possible in the earlier stage, namely the one with the smaller absolute value in the two input variables is found out, and then whether the output is a positive value or a negative value is determined according to the positive and negative relation of the two inputs; the g function function is realized as much as possible in the later period, namely addition or subtraction operation is performed on the two inputs. The invention further provides a specific structure of the h function circuit.Through optimization of an algorithm and a circuit, the speed and the accuracy of polar decoding are improved, and meanwhile, the area of a polar decoder is reduced.