13 results about "Modular multiplier" patented technology

The present application relates to the technical field of modular multiplier and compressor design, and in particular to a modular multiplication compressor circuit, which solves the problems in the prior art of large data transmission delay, high hardware overhead, and poor flexibility of discrete modular multipliers and compressors. The modular multiplication compressor circuit comprises: an input configuration unit configured to generate first data to be processed, a first pre-processing parameter, a second pre-processing parameter, and a third pre-processing parameter; a data pre-processing unit configured to perform, on the basis of the first pre-processing parameter, the second pre-processing parameter and the third pre-processing parameter, data processing on the first data to be processed and second original data to be processed, to generate pre-processed output data and quotient output data; a switching unit configured to send the pre-processed output data to a compression processing unit or a modular multiplication processing unit; the compression processing unit configured to generate compressed data on the basis of the pre-processed output data, the quotient output data and a modulus; and the modular multiplication processing unit configured to generate modular multiplication data on the basis of the pre-processed output data, the third pre-processing parameter, and the modulus.

The application discloses a prime number field elliptic curve password co-processor, which comprises a register module, a NAF encoding module, an operation module and a controller module; wherein the operation module comprises a modular multiplier unit, a modular squarer unit, a first modular adder unit and a second modular adder unit; the modular multiplier unit is connected with the first modular adder unit and the second modular adder unit and constitutes a three-stage pipeline structure to perform modular multiplication operation; the modular squarer unit is connected with the first modular adder unit and the second modular adder unit and constitutes a three-stage pipeline structure to perform modular squaring operation; the modular multiplier unit and the modular squarer unit operate in parallel, which can accelerate the operation rate, realize higher performance, and achieve the best trade-off between area and performance, and is very suitable for high-speed encryption and decryption application. The application can be widely applied to the technical field of information security.

The invention discloses a cryptographic algorithm hardware implementation method based on Montgomery modular multiplication. A hardware circuit comprises an APB interface module, a host register interface module, a control logic module, an IRQ interface module and an RSA core operation module. According to the hardware implementation method, loading of RSA parameters and result output are achieved through a host register interface. And full-process control from data loading, Montgomery domain conversion, modular exponentiation iterative operation to final result output is realized through a control logic module and an internal state machine. A high-base Montgomery algorithm is adopted in the RSA core operation module to be combined with a base 4 Booth carry-save multiplier and a CSA partial product compressor, parallel operation of a multi-stage depth assembly line is achieved, and a modular multiplier of 12-path parallel operation is adopted outside the RSA core operation module to achieve an external assembly line structure. Through cooperative processing of internal and external double-layer assembly lines, the delay of a critical path is remarkably shortened, and the throughput rate of modular exponentiation calculation and the utilization rate of hardware resources are improved.

The invention discloses a configurable vectoring modular multiplier, comprising a plurality of modular multiplication units, each modular multiplication unit comprising: an input module for receiving a first input signal, a second input signal, a third input signal and a control signal; the first input signal is a first coefficient corresponding to the column number of the modular multiplication unit in the first polynomial; the second input signal is a second coefficient corresponding to the line number of the modular multiplication unit in a second polynomial; the third input signal is a third coefficient corresponding to the line number of the modular multiplication unit in the irreducible polynomial; the multiplication and addition module is used for performing vectorization multiplication and addition on an output vector, a second input signal and a first input signal according to bit block circulation, calling an update function to perform reduction operation on the output vector and a third input signal, and performing reduction operation on the output vector and the third input signal by the update function according to a control signal; and the output module is used for outputting the output vector outwards. According to the method, the dynamic MDS matrix vector multiplication can be efficiently supported without redundancy.

The invention relates to the technical field of cryptography hardware acceleration, in particular to a Paillier hardware accelerator based on a distributed multi-core pipeline. The Paillier hardware accelerator comprises a distributed hierarchical multi-core hardware architecture and a Paillier encryption and decryption algorithm executed in the Paillier hardware accelerator, and the distributed hierarchical multi-core hardware architecture splits an encryption and decryption data stream into an assembly line sequentially executed by a pre-processing unit, a distributed modular exponentiation core and a post-processing unit. The modular exponentiation operation of the encryption process of the Paillier encryption and decryption algorithm is converted into modular multiplication and modular addition operation through a simplification mode based on the binomial theorem, so that the encryption and decryption process is adapted to a parallel mechanism of high-digit modular multiplier hardware resource multiplexing and assembly lines in the distributed hierarchical multi-core hardware architecture. The problems of low hardware resource utilization rate, difficulty in time sequence convergence and the like in the prior art are solved, and the performance and the flexibility are remarkably improved.

Provided are an efficient quantum modular multiplier using characteristics of a modular operation, that is, a quantum modular multiplier having low quantum circuit complexity, and a quantum modular multiplication method. A quantum modular multiplier according to one embodiment of the present invention is a quantum modular multiplier for multiplying first qubits having N digits by second qubits having N digits (N is a natural number that is greater than or equal to 2) and includes a first auxiliary register setting unit, a second auxiliary register setting unit, an addition unit, and an auxiliary register initialization unit.

The application provides a Dilithium algorithm implementation method based on a DSP-Free modular multiplier. The scheme mainly comprises a top control module, a number theory transformation module of a multi-path delay commutation structure, a butterfly unit, an optimized multi-constant multiplication coding multiplication module and a final module reduction module. Compared with the implementation method based on DSP, the average area-time product performance is improved by more than 40%; compared with the current international optimal DSP-free design, the working frequency is improved by 29.2% on the premise of keeping the ATP performance equivalent.

The application discloses a constant decomposition and cooperative optimization-based hardware construction method and system for a modulus multiplier. The method comprises the following steps: obtaining an original constant modulus multiplication operation, decomposing a large-bit-width constant to obtain an expression composed of small-bit-width parameters through multiplication and addition and subtraction operations, wherein each level of decomposition splits a current level value into a combination of a high-bit part and a low-bit part, and each parameter value is limited in a modulus range; based on a regular signed number coding method, converting each small-bit-width parameter obtained through decomposition into a binary representation form with the least non-zero bits to determine the least number of adders required for multiplication of each parameter; in combination with the characteristics of a modulus reduction algorithm, evaluating the resource consumption and critical path delay of different decomposition expressions during hardware construction; and through iterative optimization, selecting a decomposition expression with the least number of adders under the constraint of critical path delay to generate a hardware circuit structure of a constant modulus multiplier. The application can effectively reduce resource consumption and improve operation speed.

The application provides a configurable modulo multiplier, comprising an n*n-bit binary multiplier, a bit extractor, an (n-1-k)*k-bit binary multiplier, a first configuration register stack, a compression tree adder, a second configuration register stack, an n+1-bit adder, a 2-bit adder, a carry-save adder, an n+2-bit adder and a modulo correction unit. The configurable modulo multiplier of the application proposes a new modulo correction scheme for high-bit partial product modulo correction, greatly reduces the configuration capacity of the configurable general-purpose modulo multiplier, reduces the critical path delay of the general-purpose modulo multiplier, and solves the variable remainder base requirement of the remainder system application compared with the prior art. By completely separating the multiplier and the modulo correction part, the hardware compatibility problem of the regular application and the remainder application is solved.

The application discloses a Montgomery modular multiplier based on parallel structure and coding, comprising a pre-computation storage unit, a control unit and two groups of iterative computation modules, the iterative computation module comprising an input selection control unit, a multiplexer, a CSA addition unit, an output shift unit and a register group. The Montgomery modular multiplier adds an additional shift compensation operation, decomposes the cyclic iterative computation of the partial product into two groups of parallel computation, realizes two-way parallel of 2-base Montgomery modular multiplication, and reduces the cycle delay of the original 2-base Montgomery modular multiplication to 1 / 2 of the original. In combination with the characteristics of the two-way parallel design, the input data is re-encoded, the additional shift compensation operation and the partial product are pre-computed, the original three additions are converted into a multiplexing and an addition, the additional area overhead caused by the parallel of the circuit module is optimized, the critical path of the overall operation is shortened, and the Montgomery modular multiplier can be better deployed in a lightweight application scenario.

The application provides a modular multiplier applied to SM9, comprising: a multiplication circuit configured to perform a multiplication operation on two operators in the SM9 to obtain a product of the two operators, wherein the product is a binary number, and the number of bits of the product is m, and the m is an integer multiple of 2; and a modulus calculator connected with the multiplication circuit and configured to perform n times of modulus operation on the product in n clock cycles to obtain a final modular multiplication result, wherein each time of the modulus operation is performed in one clock cycle to obtain one modulus result, and the n is a positive integer less than m / 2. The application also provides a corresponding secure chip and encryption algorithm. The above scheme of the application avoids using the Montgomery modular multiplication algorithm, reduces unnecessary repeated modular multiplication, improves the speed of the entire modular multiplication operation in the SM9, and thus improves the overall performance of the SM9.

The application relates to a lookup table-based modular multiplier and a modular multiplication method. The modular multiplier comprises a multiplier module, which is used for tripartite decomposition of a multiplier and a multiplicand to obtain a first polynomial of multiplication operation of the multiplier and the multiplicand; quadruple decomposition of the multiplier and the multiplicand of each multiplication operation in the first polynomial to obtain each second polynomial of each multiplication operation in the first polynomial; operation based on each second polynomial to obtain a product of the multiplication operation of the multiplier and the multiplicand; a modulus reduction module connected with the multiplier module, which is used for large-bit-width modulus reduction operation of the product and a modulus to obtain a first calculation result; small-bit-width modulus reduction operation of the first calculation result and the modulus to obtain a modular multiplication result, consumption of hardware resources and complexity of circuit design are reduced, and calculation time delay is effectively reduced.

The application provides a modular multiplier circuit applied to a post-quantum cryptographic algorithm and a calculation method thereof, comprising: a first calculation module, which is used for calculating the result of (a*b1)mod q to obtain a first calculation result f; wherein mod represents a remainder algorithm; a second calculation module, which is used for calculating the result of (a*b2)mod q to obtain a second calculation result g; wherein a is 23-bit data, b is 23-bit data, b1 represents data from the 5th bit to the 22nd bit of the data b, and b2 represents data from the 0th bit to the 4th bit of the data b; and a third calculation module, which is used for calculating the result of (f+g)mod q to obtain a final output result. The structure only uses one DSP, and further improves the circuit performance through modular reduction method and key path insertion register.