4 results about "Carry-save adder" patented technology

The application discloses a method and device for approximating calculation of a softmax function. The method simplifies the exponential operation of e into twice constant multiplication and once exponential operation of e with the output range of (1, 2), which is mainly to limit the range of e exponent to utilize the characteristics of small range and high precision of the cordic algorithm; and simplifies N times division operation into once reciprocal operation with fixed input range, N times multiplication and shift operation. The device of the application comprises a constant multiplication unit, an exponential calculation unit, a floating point addition unit, a mantissa calculation unit, a subtraction array unit and a multiplication unit, adopts a carry-save adder instead of a traditional adder, and further shortens the critical path. The scheme of the application greatly improves the calculation speed while maintaining high precision, and reduces the consumption of calculation resources.

The present invention discloses a data encryption implementation method and device of an SM3 algorithm, the method comprising: filling a plaintext message through a state machine; grouping the filled messages, respectively expanding them, and outputting message words; optimizing the iterative compression calculation of the message words in parallel through a CSA carry-preserving adder and a CPA carry-propagating adder to obtain encrypted data. The device comprises a message filling module, a plurality of groups of expansion and compression modules, and a control module, wherein the control module is respectively connected to the message filling module and the expansion and compression module, and the expansion and compression module comprises an expansion module and a compression module. The present invention solves the problems of large circuit resource occupancy and high operating power consumption of the existing SM3 algorithm implementation structure.

The invention discloses a sparse linear optimization-oriented fast floating point multiply-accumulator, which comprises a complement module for complementing a mantissa part and a sign bit of input data; the order adding module is used for carrying out additive operation on the order part of the input data; the coding module is used for coding the complement data; the adder tree module comprises a 5-3 carry-save adder and is used for summing the partial products; the shifting module is used for performing shifting alignment on the Sum and the Carry according to the order code data; the accumulator module is used for accumulating the shifted Sum and Carry and a feedback result; the carry propagation adder module is used for carrying out carry propagation addition operation on the accumulation result; and the normalization module is used for carrying out normalization processing on the accumulated fixed-point format result. According to the sparse linear optimization-oriented fast floating point multiply accumulator, when the 5-3 carry-save adder is adopted to be realized on the FPGA, only one LUT is needed, and the compression ratio is improved.

The application relates to a modulus addition and modulus subtraction acceleration device based on a carry-save adder and an encryption device, wherein the modulus addition and modulus subtraction acceleration device comprises a modulus addition acceleration module and a modulus subtraction acceleration module; the modulus addition acceleration module carries out modulus addition on input addends and addends through three-stage cascaded data compression circuits to output a modulus addition result with a modulus P, wherein a four-input CSA unit is used for modulus addition compression processing in the first-stage data compression circuit, and three-input CSA units are used for modulus addition compression processing in the second-stage and third-stage data compression circuits; the modulus subtraction acceleration module carries out bitwise inversion on a minuend, and then carries out modulus addition on the inverted minuend and the subtrahend through four-stage cascaded data compression circuits to output a modulus subtraction result with the modulus P, wherein a four-input CSA unit is used for modulus addition compression processing in the first-stage data compression circuit, and three-input CSA units are used for modulus addition compression processing in the second-stage, third-stage and fourth-stage data compression circuits. The application realizes modulus addition and modulus subtraction operation acceleration, and improves circuit frequency.