Carry save adder and its system

Abstract

A 4-to-2 carry store adder that reduces output sum and carry delays. The 4-to-2 store adder may include a lower-order full adder coupled to a higher-order full adder. The carry store adder may also include a logic unit coupled to the higher order full adder, wherein the logic unit is configured to generate a carry input to the higher order full adder, typically generated from a carry store adder at a previous stage. By generating the carry (input bit) in the current stage, rather than the previous stage, the delay of the input bit to the higher order full adder is reduced, and thus the delay of the output sum of the higher order full adder and the carry is reduced.

Description

technical field [0001] The present invention relates to the field of carry-save adders, and more particularly to carry-save adders that compute input bits to higher order full adders in the current stage, but not in the previous stage. Background technique [0002] Carry-save adders are often used in high-speed multipliers, where they are generally capable of running faster than "carry-pass" or "parallel-carry" adders. Carry-save adders differ from other types of adders by the fact that the "carry" and half-sum bits (for convenience, hereinafter simply referred to as "sum bits") resulting from each addition are not immediately combined or merged. ”), but are kept separate from each other for subsequent use in the next addition to be performed by the next carry-save adder in the cascade. [0003] Because carry-store adders do not fully perform the relatively time-consuming process of combining carries, but defer this task until the final cycle of the multiplication operation...

AI Technical Summary

Problems solved by technology

The output generated by the carry store adder, such as full adder 102B, is delayed due to the propagation delay of the signal generated from the previous stage (such as the signal C'in)

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