29 results about "Lower order" patented technology

Consistent with the present disclosure, an encoder circuit is provided at a transmit side of an optical fiber link that maps an input sequence of bits of fixed length k a sequence of symbols of a codeword of length n, such that the symbols of the codeword define a predetermined transmission probability distribution. Preferably, each symbol of the codeword is generated during a corresponding clock cycle, such that after n clock cycles, a complete codeword corresponding to the input bit sequence is output. On a receive end of the link, a decoder is provided that outputs the k-bit sequence every n clock cycles. Accordingly, buffers need not be provided at the output of the encoder and the input of the decoder, such that processing of the input sequence, codewords, and output sequence may be achieved efficiently without large buffers and complicated circuitry. Moreover, the input sequence, with any binary alphabet may be matched to a desired output distribution with any arbitrary alphabet. Accordingly, probabilistic constellation shaping may be achieved over constellations of arbitrary size. In addition, relatively long codewords, may be encoded and decoded with the apparatus and method disclosed herein. Accordingly, for a fixed SNR a higher SE (more bits per symbol) can be achieved. Alternatively, for a fixed SE, a lower SNR may be sufficient. Moreover, the resulting SE may be finely tailored to a particular optical link SNR to provide data transmission rates that are higher than the low order modulation formats that would otherwise be employed for optical signals carried by such links.

The present invention provides a time-saving method for performing queries in a database or information retrieval system, the method comprising performing operations such as intersection, union, difference, and exclusive OR on two or more key sets stored in the database or information retrieval system. In a novel execution model, all data sources and operations are tries, and the input tries for higher-order set operations can be the output of lower-order set operations that are evaluated on demand. Two or more input tries are combined according to the corresponding set operations to obtain the key sets associated with the nodes of the corresponding result tries. The physical algebra of the bitmap-based trie implementation directly corresponds to the logical algebra of the set operations and allows for an efficient implementation by means of bitwise Boolean operations.

A computer-implemented method for efficiently estimating the number of unique elements in a collection of elements comprises generating, via hash logic, hash values associated with the elements. The hash values specify bit positions within an array of bits. Hash values output from the hash logic conform to a geometric distribution such that bit positions of the array of bits corresponding to lower orders bits are more likely to be generated than bit positions corresponding to higher-order bits. Bits of the array of bits corresponding to the bit positions are set. The number of bits of the array of bits that are set is counted. Estimation logic estimates the number of unique elements of the collection of elements as a function of the number of bits of the array of bits that are set.

A bit plane converter and associated methods. In an embodiment, the bit plane converter is configured to receive a first bit plane comprising low-order bits for an array of pixels, and a second bit plane comprising higher-order bits for the pixels. The bit plane converter is configured to perform an interleave process on the pixels to generate bit fields for the pixels by processing low nibbles of a low-order word and the low nibbles of a higher-order word using a lookup table to generate a bitwise interleaved low nibble vector, processing high nibbles of the low-order word and the high nibbles of the higher-order word using the lookup table to generate a bitwise interleaved high nibble vector, and interleaving bytes of the bitwise interleaved low nibble vector with bytes of the bitwise interleaved high nibble vector to generate a bitwise interleaved vector.

This invention discloses an efficient direct method for identifying the order of a low-order linear system containing complex poles, comprising the following steps: initializing the system under test to a zero state, applying a constant excitation to the system under test, and simultaneously acquiring the response output signal V of the system under test. (out) (t), calculate the second-order discriminant Ψ (2) (i) and its average value μ (2) With standard deviation σ (2) Calculate the third-order discriminant element Ψ (3) (i) and its average value μ (3) With standard deviation σ (3) Identify, remove outlier discriminants and update μ (2) μ (3) σ (2) σ (3) The order N of the system under test is analyzed. ord This invention addresses a key technical challenge in the control and operation of low-order linear systems with complex poles, laying a solid foundation for achieving safe, controllable, efficient, low-consumption, and high-performance stable operation.

The application discloses a kind of piecewise direct identification method of low-order linear system order containing complex pole, comprising the following steps: the system to be measured is initialized to zero state and prepares a constant input excitation and an output quantity acquisition system, the constant input excitation is applied to the system to be measured and the output sample is collected and saved, the sample adjacent difference element is calculated, the order base element is calculated, the singular order base element and the corresponding sample adjacent difference element are identified and removed, and the total number of effective sample adjacent difference elements and the total number of effective samples are updated, the identification coefficient and the identification accuracy are calculated, and the order of the system to be measured is analyzed;The application gives a solution to the key technical pre-problem in the control and operation level for the low-order linear system containing complex pole, which lays a solid foundation for the core technology for the subsequent realization of safe and controllable, efficient and low-consumption, and high-performance stable operation.

To provide an attractive game for making a player interested in the composition of a game medium by improving the utilization value of the game medium of a low order rank whose value is recognized to be low and which tends to be surplus as the game medium owned by the player.SOLUTION: The server device 10 is configured to, upon receiving a fusion instruction to fuse a second game card at a higher rank with a first game card at a lower rank for which a specific ability parameter is defined, execute a determination process of making a determination as to whether the first game card satisfies a given fusion condition, and upon determining that the first game card satisfies the fusion condition, execute a specific ability addition process of adding the specific ability parameter defined for the first game card to the second game card as a fusion process.SELECTED DRAWING: Figure 4

Apparatus and methods for prime field modular reduction are described. As an example, a customized modular reduction digital circuit is described for reducing an n-bit integer based on a modulus, where the modulus includes a k-bit integer for use with a cryptographic algorithm. A customized modular reduction digital circuit includes a first circuit to generate at least two partial results by processing: (1) k lower order significant bits of an n-bit integer, and (2) at least a subset of bits for a congruent representation corresponding to any n-k higher order bits of the n-bit integer whose significance is higher than the most significant bit of the k-bit integer. The customized modular reduction digital circuit also includes a second circuit to process the at least two partial results output by the first circuit to generate a reduced version of the n-bit integer for use with the cryptographic algorithm.

A computer processing system configured to effectuate lower-order masking in a higher-order masked design that includes a DOM Multiplication gate of order M operably configured to receive M + 1 data shares for each of a plurality of variables and operably configured to perform a lower order masking of N. As used herein, M is greater than N, by disabling at least one cross-domain computation of the M + 1 data shares between N + 1 data shares and M – N data shares. To that end, the system and method of effectuating lower-ordered masking in a higher-order masked design beneficially by being operable to disable cross-domain computations to perform the lower-order masked operations.

The invention belongs to the technical field of numerical control, and relates to a Bode diagram-based feed system agility parameter identification method and equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: (1) acquiring a closed-loop Bode diagram of a to-be-identified feed shaft instruction to a workbench; (2) enabling a feeding system to be equivalent to a low-order system; (3) replacing the relation curve of the agility and the speed fluctuation of the feed shaft to be identified with the relation curve of the agility and the speed fluctuation of the equivalent low-order system; and (4) determining a speed fluctuation threshold value of the equivalent low-order system according to processing requirements, and determining a rapid degree parameter conforming to the speed fluctuation threshold value according to a relation curve of the rapid degree and the speed fluctuation of the equivalent low-order system. According to the method, a machine tool operator can accurately identify and optimize the rapid parameters, and the adaptability of the rapid parameters of the feeding system to the machine tool capacity and tasks is improved.

The invention discloses an end-to-end speech separation algorithm based on a speech language model, and the algorithm comprises the steps: discretizing a continuous audio into a 32-order discrete codebook sequence through a residual vector quantization coder-decoder, and introducing a transcription start symbol lt through an SOT strategy; sOSgt, SOSgt; a special separator is lt; sCgt; and a termination symbol lt; eOSgt, EOSgt; splicing a multi-person voice sequence; extracting audio depth features by using a pre-trained WavLM model, and guiding an autoregression decoder to output a separated zero-order codebook sequence in combination with a cross attention mechanism; predicting a high-order codebook sequence step by step through a non-autoregression model, configuring an independent embedding layer to fuse low-order information, and introducing a task embedding mechanism to optimize modeling; based on a special separator lt; sCgt; and slicing the multi-order discrete codebook sequence, and outputting an independent voice source through an Encodec decoder. According to the method, the intelligibility of voice separation and the audio restoration quality can be effectively improved, the decoding speed is high, the subjective hearing experiment result and the downstream task performance are excellent, the scene that the number of speakers is unknown is supported, and the industrialization application prospect is wide.

A ratio of events in a data stream can be probabilistically maintained using a machine which comprises an observation line and circuitry for maintaining the ratio. In such a machine the circuitry may comprise a set of estimator modules, each of which comprises a random number generator and a storage module, wherein the set of estimator modules may comprise a highest order estimator module and a lowest order estimator module.

Provided is a time to digital converter that outputs time interval digital data having multiple bits according to a time interval from a first timing to a second timing, the time to digital converter including a first circuit configured to generate lower order bits among the multiple bits, a second circuit configured to generate higher order bits among the multiple bits, and a third circuit configured to synchronize the first circuit and the second circuit by generating a second signal with use of a first signal output from the first circuit and outputting the second signal to the second circuit, in which the first signal is generated by using a signal with multiple bits among the lower order bits.

Apparatus and methods for prime field modular reduction are described. As an example, a custom modular reduction digital circuit for reducing an n-bit integer based on a modulus, where the modulus comprises a k-bit integer for use with a cryptographic algorithm, is described. The custom modular reduction digital circuit includes a first circuit to generate at least two partial results by processing: (1) k lower order significant bits of the n-bit integer and (2) at least a subset of bits for congruent representations corresponding to any n-k higher order bits of the n-bit integer that are higher in significance than the most significant bit of the k-bit integer. The custom modular reduction digital circuit further includes a second circuit to process the at least two partial results, output by the first circuit, to generate a reduced version of the n-bit integer for use with the cryptographic algorithm.

The present application relates to a click-through rate prediction method, apparatus, computer equipment, storage medium and computer program product. The method comprises: obtaining each coded discrete feature and coded continuous feature of the target user; performing a linear transformation on the output cross-feature matrix to obtain a cross-feature linear transformation matrix; weighting each embedded feature by feature importance to obtain each weighted embedded feature; performing an explicit low-order feature cross on each weighted embedded feature to obtain a low-order combination feature; performing an explicit high-order feature cross on each embedded feature to obtain a high-order combination feature; performing feature aggregation on the low-order combination feature, the high-order combination feature and the coded continuous feature to obtain an aggregated feature, and predicting the click-through rate of the target user based on the aggregated feature. The use of this method can improve the accuracy of click-through rate prediction.

A processing unit includes a processing element (PE) array having a plurality of rows of PEs and a plurality of columns of PEs. Each of the PEs includes an arithmetic circuit configured to mathematically combine activation operands and weight operands. The PE array also includes a weight memory configured to supply weight operands to PEs in the PE array, an activation memory configured to supply activation operands to PEs in the PE array, and an encoder coupled to the activation memory. The encoder includes a multiplexing circuit configured to encode a signed N-bit input activation as a signed N-M bit higher order portion representing the integer value [signed {aN-1 . . . aN-M}+aN-1]*2M and a signed M+1 bit lower order portion representing the integer value signed {aNaN-M-1 . . . a0}.

The invention provides a large-model low-resource high-efficiency fine tuning method and system. The method comprises the following steps: constructing a training set, quantifying the weight of a pre-training model, configuring a low-order adaptation module for a part of weight matrix, and calculating a scaling factor for each module based on a layer index and a norm; estimating memory consumption of each converter module, setting the module with high memory consumption and low scaling factor mean value as a gradient check point, and only retaining input activation of the module during forward propagation; in back propagation, forward calculation is re-executed on a non-check-point module, the self-attention sub-layer adopts high precision, and the feed-forward network sub-layer adopts low precision according to a scaling factor; and updating the parameters of the low-order adaptation module by using the gradient, and adjusting the quantitative configuration of the next training step according to the ratio of the gradient to the weight to realize fine adjustment.

Provided is a research data management infrastructure system for collecting and creating low-order data from high-order data. This research data management infrastructure system comprises: an extraction means that extracts relationship information and a feature keyword from a large-scale language model to which high-order data and metadata accompanying the high-order data are inputted; and an output means that, on the basis of the high-order data, the metadata accompanying the high-order data, the relationship information, and the feature keyword, outputs low-order data of a lower order than the high-order data and metadata accompanying the low-order data.

A bit plane converter and associated methods. In an embodiment, the bit plane converter is configured to receive a first bit plane comprising low-order bits for an array of pixels, and a second bit plane comprising higher-order bits for the pixels. The bit plane converter is configured to perform an interleave process on the pixels to generate bit fields for the pixels by processing low nibbles of a low-order word and the low nibbles of a higher-order word using a lookup table to generate a bitwise interleaved low nibble vector, processing high nibbles of the low-order word and the high nibbles of the higher-order word using the lookup table to generate a bitwise interleaved high nibble vector, and interleaving bytes of the bitwise interleaved low nibble vector with bytes of the bitwise interleaved high nibble vector to generate a bitwise interleaved vector.

A method may include receiving a plurality of input bits; determining, using a convolutional trellis, a state transition of the convolutional trellis at least partially responsive to a first subset of the input bits; selecting, from a symbol alphabet that is a subset of a constellation of signal‑level patterns of a multi-level modulation scheme, a group of symbols pre‑associated with the determined state transition and identified at least partially by a second subset of the input bits; and serializing and transmitting the selected group of symbols.

Neurosynaptic systems for computing characteristics of a set are provided. In various embodiments, a plurality of encoders is provided. Each encoder is adapted to receive a population coded input and generate an encoded output. The encoded output comprises a plurality of segments. Each segment corresponds to one or more binary bits. A winner selection component is adapted to receive the encoded outputs from the plurality of encoders and to perform a method comprising: proceeding from highest order to lowest order of the segments of the encoded outputs of the encoders, performing a bitwise OR operation across all segments of equivalent order; disqualifying each encoded output whose bits do not match the result of the bitwise OR operation across all segments of equivalent order; outputting remaining encoded outputs.

Systems, apparatuses, methods, and computer program products are disclosed for computing a Shapley additive explanation (SHAP) value ϕi using model structure information. An example method includes receiving a model ƒ(x) that uses a vector of features x as input, where the model has a known functional decomposition and generating, using the known functional decomposition, a set of lower order terms ƒv(xv), where a lower order term from the set of lower order terms takes a subset of the features as input, where a sum of the set of lower order terms equals the model ƒ(x). The example method further includes computing a set of lower-order SHAP values ϕi(ƒv) for the set of lower order terms and computing the SHAP value ϕi for the model based on a sum of the set of lower-order SHAP values.

A bit-slicing method comprises: dividing input data into predetermined bit units to obtain a plurality of intermediate representation slice data; and sequentially obtaining higher-order slice data by adding, to a higher-order intermediate representation slice data, a sign bit that is a most significant bit of lower-order slice data obtained in a previous step and a carry bit generated in a process of obtaining the lower-order slice data.

A multiplier apparatus computes multiplication of a multiplicand and a multiplier to give a product. A multiplicand separator and a multiplier separator receive n bit numbers and separate them into high order segments and low order segments. A first multiplier multiplies the high order segments. Second and third multipliers multiply the high order and low order segments. The products of these multiplications are added together by an adder to give a multiplication product. Another implementation uses rounding logic to allow fewer bits in the multipliers. The adder can be a three-way adder or a combination of two-way adders.

The invention discloses a low-operand low-order dissimilar real pole linear system order direct type identification method, which comprises the following steps: step 1, preparing a constant value input excitation and output quantity acquisition system, step 2, applying the constant value input excitation to a system to be detected and acquiring and outputting, step 3, calculating a sample element h (r, j), step 4, calculating an identification element g (a, b), and step 5, calculating the identification element g (a, b). 5-7, respectively calculating first-level, second-level and third-level identification elements and first-level, second-level and third-level identification elements, 8, calculating identification factors xRecc (1), xRecc (2) and xRecc (3), 9, analyzing the order number Num of the system to be tested according to the identification factors, 10, if Num =-1 and Recc = 1, if Recc = 2, turning to the step 4, and otherwise, ending; the method lays a solid foundation for safe, efficient and high-performance control and operation of the low-order dissimilar real pole linear system.

The present disclosure provides a decoding method and a memory system that decodes data and estimates a weighted check sum of the decoded data to determine whether the decoding is successful. The weighted check sum is computed based on a first set and a second set, the first set being associated with weights of high order nodes of an irregular parity check matrix, the second set being associated with weights of low order nodes of the irregular parity check matrix.

Apparatus and methods for prime field modular reduction are described. As an example, a custom modular reduction digital circuit for reducing an n-bit integer based on a modulus, where the modulus comprises a k-bit integer for use with a cryptographic algorithm, is described. The custom modular reduction digital circuit includes a first circuit to generate at least two partial results by processing: (1) k lower order significant bits of the n-bit integer and (2) at least a subset of bits for congruent representations corresponding to any n-k higher order bits of the n-bit integer that are higher in significance than the most significant bit of the k-bit integer. The custom modular reduction digital circuit further includes a second circuit to process the at least two partial results, output by the first circuit, to generate a reduced version of the n-bit integer for use with the cryptographic algorithm.

The application discloses a low-order different real pole linear system order direct identification method with small operation amount, which comprises the following steps: step one, preparing a constant input excitation and an output quantity collection system; step two, applying the constant input excitation to a system to be measured and collecting the output; step three, calculating sample elements h(r, j); step four, calculating identification base elements g(a, b); steps five to seven, respectively calculating first, second and third identification elements and first, second and third identification factors; step eight, calculating an identification factor χ Rec (1), χ Rec (2), χ Rec (3); step nine, analyzing the order Num of the system to be measured according to the identification factor; and step ten, if Num=-1 and Rec=1, then Rec=2, returning to step four for calculation, otherwise ending. The application lays a solid foundation for safe, efficient and high-performance control and operation of a low-order different real pole linear system.