14 results about "Lower order" patented technology

This invention discloses an efficient direct method for identifying the order of a low-order linear system containing complex poles, comprising the following steps: initializing the system under test to a zero state, applying a constant excitation to the system under test, and simultaneously acquiring the response output signal V of the system under test. (out) (t), calculate the second-order discriminant Ψ (2) (i) and its average value μ (2) With standard deviation σ (2) Calculate the third-order discriminant element Ψ (3) (i) and its average value μ (3) With standard deviation σ (3) Identify, remove outlier discriminants and update μ (2) μ (3) σ (2) σ (3) The order N of the system under test is analyzed. ord This invention addresses a key technical challenge in the control and operation of low-order linear systems with complex poles, laying a solid foundation for achieving safe, controllable, efficient, low-consumption, and high-performance stable operation.

The application discloses a kind of piecewise direct identification method of low-order linear system order containing complex pole, comprising the following steps: the system to be measured is initialized to zero state and prepares a constant input excitation and an output quantity acquisition system, the constant input excitation is applied to the system to be measured and the output sample is collected and saved, the sample adjacent difference element is calculated, the order base element is calculated, the singular order base element and the corresponding sample adjacent difference element are identified and removed, and the total number of effective sample adjacent difference elements and the total number of effective samples are updated, the identification coefficient and the identification accuracy are calculated, and the order of the system to be measured is analyzed;The application gives a solution to the key technical pre-problem in the control and operation level for the low-order linear system containing complex pole, which lays a solid foundation for the core technology for the subsequent realization of safe and controllable, efficient and low-consumption, and high-performance stable operation.

To provide an attractive game for making a player interested in the composition of a game medium by improving the utilization value of the game medium of a low order rank whose value is recognized to be low and which tends to be surplus as the game medium owned by the player.SOLUTION: The server device 10 is configured to, upon receiving a fusion instruction to fuse a second game card at a higher rank with a first game card at a lower rank for which a specific ability parameter is defined, execute a determination process of making a determination as to whether the first game card satisfies a given fusion condition, and upon determining that the first game card satisfies the fusion condition, execute a specific ability addition process of adding the specific ability parameter defined for the first game card to the second game card as a fusion process.SELECTED DRAWING: Figure 4

Apparatus and methods for prime field modular reduction are described. As an example, a customized modular reduction digital circuit is described for reducing an n-bit integer based on a modulus, where the modulus includes a k-bit integer for use with a cryptographic algorithm. A customized modular reduction digital circuit includes a first circuit to generate at least two partial results by processing: (1) k lower order significant bits of an n-bit integer, and (2) at least a subset of bits for a congruent representation corresponding to any n-k higher order bits of the n-bit integer whose significance is higher than the most significant bit of the k-bit integer. The customized modular reduction digital circuit also includes a second circuit to process the at least two partial results output by the first circuit to generate a reduced version of the n-bit integer for use with the cryptographic algorithm.

The invention discloses an end-to-end speech separation algorithm based on a speech language model, and the algorithm comprises the steps: discretizing a continuous audio into a 32-order discrete codebook sequence through a residual vector quantization coder-decoder, and introducing a transcription start symbol lt through an SOT strategy; sOSgt, SOSgt; a special separator is lt; sCgt; and a termination symbol lt; eOSgt, EOSgt; splicing a multi-person voice sequence; extracting audio depth features by using a pre-trained WavLM model, and guiding an autoregression decoder to output a separated zero-order codebook sequence in combination with a cross attention mechanism; predicting a high-order codebook sequence step by step through a non-autoregression model, configuring an independent embedding layer to fuse low-order information, and introducing a task embedding mechanism to optimize modeling; based on a special separator lt; sCgt; and slicing the multi-order discrete codebook sequence, and outputting an independent voice source through an Encodec decoder. According to the method, the intelligibility of voice separation and the audio restoration quality can be effectively improved, the decoding speed is high, the subjective hearing experiment result and the downstream task performance are excellent, the scene that the number of speakers is unknown is supported, and the industrialization application prospect is wide.

A processing unit includes a processing element (PE) array having a plurality of rows of PEs and a plurality of columns of PEs. Each of the PEs includes an arithmetic circuit configured to mathematically combine activation operands and weight operands. The PE array also includes a weight memory configured to supply weight operands to PEs in the PE array, an activation memory configured to supply activation operands to PEs in the PE array, and an encoder coupled to the activation memory. The encoder includes a multiplexing circuit configured to encode a signed N-bit input activation as a signed N-M bit higher order portion representing the integer value [signed {aN-1 . . . aN-M}+aN-1]*2M and a signed M+1 bit lower order portion representing the integer value signed {aNaN-M-1 . . . a0}.

The invention provides a large-model low-resource high-efficiency fine tuning method and system. The method comprises the following steps: constructing a training set, quantifying the weight of a pre-training model, configuring a low-order adaptation module for a part of weight matrix, and calculating a scaling factor for each module based on a layer index and a norm; estimating memory consumption of each converter module, setting the module with high memory consumption and low scaling factor mean value as a gradient check point, and only retaining input activation of the module during forward propagation; in back propagation, forward calculation is re-executed on a non-check-point module, the self-attention sub-layer adopts high precision, and the feed-forward network sub-layer adopts low precision according to a scaling factor; and updating the parameters of the low-order adaptation module by using the gradient, and adjusting the quantitative configuration of the next training step according to the ratio of the gradient to the weight to realize fine adjustment.

Provided is a research data management infrastructure system for collecting and creating low-order data from high-order data. This research data management infrastructure system comprises: an extraction means that extracts relationship information and a feature keyword from a large-scale language model to which high-order data and metadata accompanying the high-order data are inputted; and an output means that, on the basis of the high-order data, the metadata accompanying the high-order data, the relationship information, and the feature keyword, outputs low-order data of a lower order than the high-order data and metadata accompanying the low-order data.

A method may include receiving a plurality of input bits; determining, using a convolutional trellis, a state transition of the convolutional trellis at least partially responsive to a first subset of the input bits; selecting, from a symbol alphabet that is a subset of a constellation of signal‑level patterns of a multi-level modulation scheme, a group of symbols pre‑associated with the determined state transition and identified at least partially by a second subset of the input bits; and serializing and transmitting the selected group of symbols.

Neurosynaptic systems for computing characteristics of a set are provided. In various embodiments, a plurality of encoders is provided. Each encoder is adapted to receive a population coded input and generate an encoded output. The encoded output comprises a plurality of segments. Each segment corresponds to one or more binary bits. A winner selection component is adapted to receive the encoded outputs from the plurality of encoders and to perform a method comprising: proceeding from highest order to lowest order of the segments of the encoded outputs of the encoders, performing a bitwise OR operation across all segments of equivalent order; disqualifying each encoded output whose bits do not match the result of the bitwise OR operation across all segments of equivalent order; outputting remaining encoded outputs.

A bit-slicing method comprises: dividing input data into predetermined bit units to obtain a plurality of intermediate representation slice data; and sequentially obtaining higher-order slice data by adding, to a higher-order intermediate representation slice data, a sign bit that is a most significant bit of lower-order slice data obtained in a previous step and a carry bit generated in a process of obtaining the lower-order slice data.

A multiplier apparatus computes multiplication of a multiplicand and a multiplier to give a product. A multiplicand separator and a multiplier separator receive n bit numbers and separate them into high order segments and low order segments. A first multiplier multiplies the high order segments. Second and third multipliers multiply the high order and low order segments. The products of these multiplications are added together by an adder to give a multiplication product. Another implementation uses rounding logic to allow fewer bits in the multipliers. The adder can be a three-way adder or a combination of two-way adders.

The present disclosure provides a decoding method and a memory system that decodes data and estimates a weighted check sum of the decoded data to determine whether the decoding is successful. The weighted check sum is computed based on a first set and a second set, the first set being associated with weights of high order nodes of an irregular parity check matrix, the second set being associated with weights of low order nodes of the irregular parity check matrix.