89 results about "Sign bit" patented technology

A floating point arithmetic device with two floating point operands and its operation method are disclosed. The floating point arithmetic device includes an exponent subtraction circuit, an exponent calculation circuit, a mantissa calculation circuit, and a conversion circuit. The exponent subtraction circuit calculates the difference between the exponents of the two operands and generates a sign bit and an exponent difference. The exponent calculation circuit generates the post-operation exponent bits according to the larger one of the exponents of the two operands. The mantissa calculation circuit aligns the mantissa bits of the two operands and performs one of addition and subtraction on the aligned mantissa bits. To improve the calculation efficiency and reduce the power consumption, the floating point arithmetic device can complete the floating point addition or subtraction operation in one step (one clock cycle) without moving the intermediate floating point data between the registers and the functional circuit units as in the multi-step operation.

The invention relates to a task-oriented semantic communication-oriented adaptive source channel coding system, which belongs to the field of wireless communication, and comprises a sending end for extracting a semantic feature map for evaluation from input data through a feature extractor initialized based on a pre-training large model, executing nested quantization and arithmetic coding based on a calculated importance score, and sending the semantic feature map to a task-oriented semantic communication-oriented adaptive source channel coding system; generating a scalable semantic bit stream with importance levels; the physical layer is used for carrying out reordering and grouping according to importance levels of bit streams, a channel encoder is combined with an interleaver to realize unequal error protection of semantic matching, and encoded bits are mapped to sign bits with different fault-tolerant capabilities in a constellation diagram through division modulation; and a receiving end: recovering the semantic feature map through arithmetic decoding and nested inverse quantization. According to the invention, on the premise of keeping compatibility with a digital communication protocol stack, through distortion-driven joint rate self-adaption, the transmission effectiveness for machine tasks and human vision is obviously improved under a limited bandwidth.

The invention discloses a circuit for approximate floating point fusion dot product operation. The circuit comprises an extraction module used for extracting sign bits, mantissa bits and exponent bits from four single-precision floating point numbers; the symbol integration module is used for integrating symbol bits and correcting mantissa bits; the index comparison module is used for calculating two groups of dot product effective indexes according to the index bits and generating three control quantities; the first multiplication module is used for generating a first group of approximate partial products according to a correction mantissa digit corresponding to a first control quantity larger value; the second multiplication module is used for generating a second group of approximate partial products according to the correction mantissa digit corresponding to the smaller value of the first control quantity, and performing arithmetic displacement and adding symbol compensation bits according to the size of the second control quantity; the fusion compression module is used for performing fusion compression on the first group of approximate partial products, the second group of approximate partial products after arithmetic shift and the symbol compensation bits to obtain a sum sequence and a carry sequence; and the result output module is used for generating a dot product operation result in combination with the third control quantity.

This application provides a tensor computation method and related apparatus. Through this method, a unified preprocessing is used to obtain the corresponding sign bit, exponent part, and mantissa part for tensors of different data types. Then, through subsequent general exponent accumulation, mantissa multiplication, comparison, shifting, and addition processing, the above unified processing logic can be adapted to the computational needs of different data tensors. Compared with the design idea of ​​equipping each data type with dedicated integrated circuits, this fundamentally eliminates circuit redundancy, thereby reducing chip area, reducing power consumption, and improving flexibility.

The application discloses a model training process-oriented computing power chip hardware Trojan design method, and relates to the field of integrated circuit security.The method is designed in view of the computing architecture of a GPU, and contains a flip-flop, a finite state machine and a load circuit.The flip-flop identifies the typical characteristics of deep learning training by monitoring the arithmetic instruction intensity and the Warp concurrent activity of the GPU runtime; when the characteristics meet a preset threshold, the finite state machine is triggered, so that the hardware Trojan enters an activated state.The load circuit has two types of designs: the first type is a gradient flipping circuit which interferes with the gradient update direction by modifying the sign bit output by a floating point calculation unit, so that the model cannot converge; the second type is a redundant calculation circuit which consumes computing resources by inserting invalid floating point operations, thereby prolonging the training time.The application designs and triggers the hardware Trojan by utilizing the architecture characteristics of the GPU, has high concealment, and can effectively destroy the accuracy and efficiency of a deep learning training task.

The invention discloses a data coding method and device based on a block chain, equipment and a storage medium. The data coding method comprises the following steps: reading floating point data in a block body of a first block; encoding the floating point data to obtain block floating point data; and storing a sign bit and a mantissa bit of the block floating point data into a block body of the first block, and storing a sharing index of the block floating point data into a block head of the first block. According to the application, the floating point data in the block body of the first block is encoded to obtain the block floating point data; the sign bit and the mantissa bit of the block floating point data are stored in the block body of the first block, and the sharing index of the block floating point data is stored in the block head of the first block, so that the storage space of the index bit is released, the on-chain storage overhead and the network transmission load of the block chain can be reduced, the data transmission speed is improved, and the user experience is improved. And the performance of the block chain is optimized.

The application discloses an R-2R digital-analog converter with an auxiliary calibration structure and relates to the technical field of high-precision digital-analog conversion. The converter comprises a main DAC, a calibration quantity calculation module, a compensation code generation module, an auxiliary DAC and an operational amplifier circuit. The main DAC converts a digital input into an analog current. The calibration quantity calculation module generates a 15-bit compensation code containing a 1-bit sign bit and a 14-bit data bit through a 24-bit ADC, a comparator and successive approximation logic, and only calibrates the high 12 bits of the main DAC bit by bit, and the low 4 bits do not need to be calibrated. The compensation code generation module generates a total compensation code through gating by a multiplexer and superposition by an adder. The auxiliary DAC is a 14-bit binary current type structure, and realizes bidirectional compensation in cooperation with a positive and negative reference voltage source. The application has the advantages of short calibration period, small storage consumption, no need for additional bias calibration, excellent linearity, and suitability for application in the fields of wireless communication, biological medicine and the like, and meets the application requirements of high resolution and high precision.

This invention provides an optimized method for integrating floating-point multiply-accumulate algorithms in a single-precision floating-point multiply-accumulate unit. During the single-precision floating-point multiply-accumulate calculation, the pipeline is implemented as follows: P0 stage: The first pipeline stage receives three operands a, b, and c as input; it performs special value judgment, product mantissa calculation, product leading zero pre-statistics, and exponent difference and comparison logic; P1 stage: The second pipeline stage receives the multiplication result, compares the product exponent with the exponent of operand c, compares the exponent difference with the product leading zero, and performs exponent difference and product leading zero comparison; after exponent alignment, the mantissa of the aligned result is summed; P2 stage: The third pipeline stage receives the mantissa summed result, adjusts the exponent data, the sign bit to be operated on, and compares the results; after completion of normalization and rounding operations, the final result is adjusted accordingly, and abnormal states are judged. A single data path is used to ensure reuse of the same logic module within the pipeline, reducing area overhead.

The application provides a signal peak position detection device and method and an input signal extraction equipment. A lookup table memory comprises: a lookup table, the lookup table comprising: bit values of sign bits of an input signal, and a corresponding relationship of a multiplication result of the input signal and a local signal; a sign extractor is used for extracting a target bit value of a sign bit of the input signal corresponding to each sampling; a multiplexer is used for, for each sampling, looking up a target multiplication result matched with the target bit value from the lookup table of the lookup table memory according to the target bit value; and a calculation unit is used for calculating a modulus value corresponding to each sampling according to the target multiplication result obtained for each sampling, and determining a peak position of the input signal in a time period of multiple samplings according to a sampling corresponding to a maximum modulus value in all modulus values. The application can omit a multiplier and an adder required for implementing the multiplication operation in a circuit, and greatly reduces the area and overall power consumption of the circuit.

The invention discloses a data transmission method and device, a terminal, network side equipment and a medium, and belongs to the technical field of communication. A sending end executes at least one of the following steps: generating modulation signals corresponding to one or more redundancy versions of data to be transmitted according to a first information bit set and a sign bit set, and sending the modulation signals; according to an amplitude value set and the sign bit set, modulation signals corresponding to one or more redundancy versions of the to-be-transmitted data are generated, the modulation signals are sent, and the first information bit set is obtained after binary mapping is conducted on the amplitude value set.

Disclosed is the calculation device of a deep neural network, which includes a conversion unit that outputs a plurality of conversion data values including bits corresponding to bits included in a plurality of original data values and further including a sign bit based on a sign of each of the plurality of original data values each composed of a plurality of bits, a compression unit that generates compression data, and a calculation preparation unit that outputs a plurality of recovery data values by inverting a value of at least some bits in each of the plurality of conversion data values, and wherein the conversion unit determines an MSB of each of the plurality of original data values as the sign bit, and inverts values of bits included in each of original data values whose signs are negative among the plurality of original data values.

A design method for a fixed-point and floating-point adder includes: S1, performing fixed-point and floating-point identification by a shared mantissa addition module; S2, for fixed-point numbers, performing low-bit calculation in the shared mantissa addition module; configuring a fixed-point number processing module, saving a carry of a highest bit in low-bit calculation results, and transmitting the saved carry to the fixed-point number processing module to obtain a fixed-point number addition result; S3, for floating-point numbers, performing calculation, in the shared mantissa addition module, on mantissas of the floating-point numbers, configuring a floating-point number processing module, and performing exponent matching and normalization on exponents of the floating-point numbers to obtain a normalized result; obtaining a floating-point number addition result according to sign bits of the floating-point numbers, the exponents subjected to the exponent matching and the normalized result; and S4, transmitting the result to an output module, and outputting the result.

The invention relates to the field of MIMO signal processing, and discloses an MIMO-oriented bit width quantization method, device, equipment and medium, and the method comprises the steps: obtaining a plurality of variables to be quantized, carrying out the quantization of the integer bit width and sign bit width of the variables, obtaining the initial population of the variables, and carrying out the iterative optimization of the initial population, in any iteration process, carrying out the quantization of the integer bit width and sign bit width of the variables, and carrying out the quantization of the integer bit width and sign bit width of the variables. The method comprises the steps of determining a reference individual in a current population, performing decimal bit width updating on other individuals based on the reference individual, performing decimal bit width updating on any individual after the decimal bit width updating based on the target function value difference between the individual and the other individual, and determining a final population after iterative optimization is completed. And determining a target individual in the final population, and quantizing the decimal bit widths of the variables based on the decimal bit width combination of the target individual. According to the technical scheme provided by the invention, the automatic and efficient distribution of the decimal bit width in the MIMO detector is realized, and the calculation complexity and the hardware overhead are reduced.

A data processing method, device, equipment and medium. The method comprises: obtaining to-be-processed data and a target function, the to-be-processed data being in a floating-point data format, the floating-point data format comprising a sign bit, an exponent part and a mantissa part; the exponent part in the floating-point data format comprising a characteristic code of floating-point data, and the mantissa part in the floating-point data format comprising a tail code of floating-point data; separating the exponent part and the mantissa part of the to-be-processed data and respectively converting them into a floating-point data format to obtain an exponent floating-point data and a mantissa floating-point data; using a segmented polynomial fitting method to approximate the target function by taking the mantissa floating-point data as a variable of the target function to obtain a fitting result of the mantissa part; and performing floating-point multiplication on the exponent floating-point data and the fitting result of the mantissa part to obtain a fitting result of the to-be-processed data. By using the above scheme, segmented polynomial fitting of more nonlinear functions can be realized.

Provided are a random access response generation method, a timing advance time determination method and apparatus, applied to the technical field of communications, the random access response generation method comprising: after detecting a random access preamble sent by a terminal, generating a random access response, the random access response carrying a timing advance field, and sending the timing advance field to the terminal; the timing advance field comprises a sign bit, an index bit and a numerical value bit, the value of the sign bit is used for indicating the sign of the timing advance time, the value of the index bit is used for indicating the index part of the timing advance time, and the value of the numerical value bit is used for indicating the numerical value part of the timing advance time; and sending the random access response to the terminal. In the scheme, the timing advance field is designed into a structure comprising the sign bit, the index bit and the numerical value bit, so that the single signaling can simultaneously indicate the positive and negative values, the measuring range and the accurate value of the timing advance time.

A gain control device comprises a sign bit identification device and a gain determination device. The sign bit identification device is used to receive a data, identify a sign bit, and obtain a position of a time slot corresponding to the sign bit. Also, the data comprises a plurality of bits, wherein the most significant bit of the bits is designed to be a sign bit which is used to represent a positive or negative value of the data. The gain determination device is electrically connected to the sign bit identification device, and the gain determination device is used to determine a gain value for amplifying the data based on the position of the time slot corresponding to the sign bit identified through the sign bit identification device.

A memory device includes a first memory column, a memory array and a sign decoder. The first memory column is configured to store first sign bits. The memory array is configured to store a first data array and generate bit line signals. The sign decoder is configured to output data signals according to the first sign bits and the bit line signals. The data signals correspond to a second data array, and the first data array is generated by reversing rows of the second data array according to the first sign bits.

An embodiment includes encoding a first 32-bit floating point depth value, in a plurality of 32-bit floating point depth values, into a first signed 8-bit integer and a second signed 8-bit integer. An embodiment includes predicting, using a trained convolutional neural network (CNN), the first signed 8-bit integer, and the second signed 8-bit integer, a plurality of depth layer maps and a probability map. An embodiment includes generating, by selecting pixels from the plurality of depth layer maps according to the probability map, a depth map of a scene.

The invention relates to the technical field of computers, and provides a coding data processing method, device and system, and the method comprises the steps: reading a to-be-processed code word, then executing the calculation of a target equation according to the to-be-processed code word, ending the calculation when the coefficient of the parameter of the target equation meets a target condition, and obtaining the parameter of the target equation as a target parameter, parameters of the target equation indicate error symbol location information. And according to the target parameter, determining an error symbol position of the to-be-processed codeword, the error symbol position being used for performing error correction on the to-be-processed codeword to obtain a decoding result of the to-be-processed codeword. On the basis of successfully solving to obtain the error symbol position information, the calculation times of the target equation are automatically controlled according to the coefficient values of the parameters of the target equation, and the calculation times can be reduced, so that the consumption of calculation resources is reduced.

The invention relates to the technical field of digital signal processing and communication data links, in particular to a data link waveform data preprocessing method based on digital operation, which comprises the following steps: acquiring high-speed continuous discrete time sequence data acquired by a data source as original waveform data; a sign bit is extracted, an absolute value is taken, numerical field transformation is carried out by utilizing leading zero detection logic, and linear field data is mapped into approximate logarithm field representation data comprising an order code and a mantissa; dividing the mantissa into a reserved high order and a discarded low order; inputting the approximate logarithm domain representation data into a main addition path of a logarithm domain addition filtering topology to carry out additive operation, and carrying out error compensation on the discarded low bits by utilizing an error compensation lookup table to generate logarithm domain preprocessing data; in combination with sign bits, converting back to a linear domain through anti-logarithm mapping logic, and outputting preprocessed waveform data; according to the invention, dynamic optimal balance between cross-environment processing quality and system resource allocation is realized.

The present disclosure provides a floating point multiplier-adder, a processor and an electronic device. The floating point multiplier-adder includes a control module, a receiving module, a splitting module, an exponent operation module, a multiplication module, a scaling module and an addition module. The receiving module receives all of the first, second and third operands or only the first and third operands for an operation. The splitting module splits the operands received by the receiving module into a sign bit, an exponent and a mantissa, respectively. The addition module performs a first addition process on a scaling result of the mantissa and a multiplication result when performing a multiply-add operation, or performs a second addition process on the scaling result of the mantissa and a first mantissa of the first operand when performing an addition operation. The control module controls the splitting module, the exponent operation module, the addition module and the multiplication array module according to the type of the operation. The floating point multiplier-adder can reduce the power loss when the floating point multiplier-adder performs an addition operation.

This invention provides a lookup table method for half-precision floating-point number FP16, including: S1, 1) NNA quantization input; 2) Int16 input: 16 bits output to Lbit, S=0 indicates a positive number, V=0 indicates no overflow; Int16 input, FP16 input: converted to FPi; lookup table value FPi; obtain offset(FPPi), scale_n(FPPi), scale_p(FPPi); add offset, according to the result: positive multiply by scale_p, negative multiply by scale_n; obtain: absolute value converted to integer, take the lower 16 bits and output to Lbit, overflow 16 bits V=1, otherwise V=0, output overflow to V, output sign bit to S; S2, obtain SVLbit 16-bit positive integer; S3, according to LU_Table, SAT_T0, IDX0_T, get: V=1: take the value SAT_T0 (S=1) or SAT_T1 (S=0), V=0: take the high 5 bits of Lbit as idx, S=1: if idx≥IDX0_T1 take the value SAT_T0, S=0: idx+=IDX0_T1, if idx>31 take the value SAT_T1, take the low 11 bits of Lbit as dx, use idx and dx to look up the table and calculate y; S4, lookup result y (FPin); true value output: convert to FP16; quantization output: get ofbit, convert to integer and saturate to ofbit unsigned number; S5, NNA quantization output or XOR RAM port.

Embodiments of the present application provide a kind of data processing device, method, processor and electronic equipment, it is related to computer technical field, in the device, including by first extraction unit, look-up unit and encoding unit consist of floating point number encoding component.First extraction unit, for extracting the sign bit and data bit of the floating point number to be encoded in the vector to be encoded.Look-up unit, for based on the data bit of the floating point number to be encoded, respectively look up the respective corresponding index of the maximum floating point number and the minimum floating point number in the vector to be encoded, obtain maximum index and minimum index.Encoding unit, for based on target bit number n, the sign bit of the floating point number to be encoded, the data bit of the floating point number to be encoded, maximum index and minimum index, the floating point number to be encoded is encoded into n-bit logarithmic floating point format representation, obtain the encoded vector.In this way, it is realized to high efficiency to the floating point number of logarithmic floating point format is represented.

The invention discloses a bit stream random number generator, a random multiplication circuit and a calculation method, and belongs to the technical field of integrated circuits. A reverse signal end of a highest-bit D trigger Ln of a linear feedback shift register is respectively connected with a NOR gate and a NAND gate, and output signal ends of n-1 low-bit triggers in the linear feedback shift register are respectively connected with a comparator; a sign bit xn of an n-bit binary number corresponding to the target numerical value is input into the NOR gate and the NAND gate respectively; bits corresponding to the amplitude bits of the n-bit binary number are input to the comparator; the comparator and the NOR gate are connected with the OR gate; the OR gate and the NAND gate are connected with the AND gate. In the application, the two bit stream random number generators can generate two bit streams with low correlation, so that the numerical value shown by the bit stream obtained by carrying out multiplication (namely XNOR operation) on the two bit streams is closer to the product result of two target numerical values.

Disclosed are a communication method and a communication device, the method comprising: a transmitting end performing hierarchical coding on a first input bit, the hierarchical coding comprising coding of a first layer and coding of at least one second layer, the first layer corresponding to a first coding mode, one of the at least one second layer corresponding to a second coding mode or not coding, and the coding of the at least one second layer corresponding to a second coding mode; all or part of the first input bits are amplitude symbol sequences output by the distribution matcher; a first check bit obtained through coding of the first layer is used as a first sign bit, the amplitude sign sequence comprises a first amplitude sign, and the layered coding further comprises the steps that when the first sign bit takes a first value, the value of one or more bits of at least one second layer is adjusted; mapping output bits of hierarchical coding based on a hierarchical coding modulation constellation diagram; the performance gain brought by probability amplitude shaping is kept, and the advantage of layered coding modulation for reducing the decoding complexity is also achieved.

This invention discloses an approximate logarithmic multiplier based on a symmetric lookup table, relating to the field of hardware circuit technology. It includes an unpacking unit for extracting the sign bit, exponent bit, and mantissa bit of the operands in different formats; and a symmetric lookup table, using the high-order bits of the mantissa bits of the first and second input operands. k The system uses bits as row and column indices and utilizes the commutative property of multiplication to store multiple residual compensation terms in the lower triangular portion. A mantissa adder, electrically connected to the unpacking unit and the symmetric lookup table, accumulates the mantissa bits of the first and second input operands along with their corresponding residual compensation terms to obtain the mantissa sum. This invention effectively compensates for residual terms neglected in the traditional Mitchell approximation, significantly reducing the relative error of the approximate multiplication. By utilizing the commutative property of multiplication to store multiple residual compensation terms in the lower triangular portion of the symmetric lookup table, it significantly reduces hardware area overhead, achieving a balance between hardware efficiency and computational accuracy.

A novel semiconductor device is provided. An analog signal is converted into a digital signal using a comparison portion comparing two current values, a control portion, and a current output digital-analog conversion portion. The control portion has a function of generating a sign bit showing a magnitude relation between the two current values, a function of converting a difference between the two current values into a digital signal by successive approximation, and a function of outputting the sign bit and the digital signal.

The application provides a probability shaping method, a storage medium, an electronic device and an apparatus. The probability shaping method comprises: dividing a first binary data stream into three parallel data streams; traversing a third amplitude bit data stream and locating a specific bit position satisfying a preset condition; judging a value of a second amplitude bit data stream corresponding to the specific bit position to obtain a judgment result, and determining whether to perform a flip operation on the value of the second amplitude bit data stream at the specific bit position according to the judgment result; and combining a sign bit data stream, the second amplitude bit data stream after the flip operation and the third amplitude bit data stream to obtain a second binary data stream. The application is based on a single-level flip mechanism, only needs to traverse the data stream once and make a statistical decision based on a single bit, can systematically optimize the probability distribution of PAM8 symbols, reduces the hardware complexity and processing delay, and improves the anti-noise performance of the link.

A method for transmitting a first number to a recipient computing machine in a distributed computing environment is proposed, which comprises: obtaining a second number corresponding to the first number, wherein the first number belongs to a first range of numbers, and the second number belongs to a second range of numbers; determining an encoding of the second number according to a binary format for encoding floating-point numbers, wherein a binary code representing a number encoded according to the format comprises a sign binary field carrying at most one sign bits encoding a sign of the number, an exponent binary field carrying one or more exponent bits encoding an exponent of a power of 2, and a fraction binary field carrying one or more significant decimal digits and transmitting, to the recipient computing machine, data representing the first number, wherein the data carries an encoding of the second number according to the format with no exponent field corresponding to the encoded second number.