250 results about "Sign bit" patented technology

An apparatus includes a floating-point gradient register; an integer register; a memory bank; and an array of processing units. Each of the units includes a plurality of binary shifters having an integer input configured to obtain corresponding bits of a 4-bit integer multiplicand, and a shift-specifying input configured to obtain corresponding bits in an exponent field of a 4-bit floating point multiplier. The multiplier is specified in a mantissaless four-bit floating point format including a sign bit, three exponent bits, and no mantissa bits. An adder tree has a plurality of inputs coupled to outputs of the plurality of shifters, and a rounder has an input coupled to an output of the adder tree. The integer inputs are connected to the integer register; the shift-specifying inputs are connected to the floating-point gradient register; and outputs of the rounders are coupled to the memory bank.

The invention provides a nonlinear activation function rapid calculation device and method based on a coefficient lookup table, and the device comprises an input selection unit which is used for selecting an input floating-point number; the coefficient lookup table unit is used for dividing the whole region of the activation function into a plurality of intervals and dividing a non-infinite interval into a plurality of sections; carrying out approximation on each section by using a quadratic function so as to establish a coefficient lookup table; the preprocessing unit is used for performing feature extraction on the floating-point number to obtain a sign bit, an order code and a mantissa; the operation unit is used for calculating an index value and a second mantissa subsegment; obtaining a corresponding quadratic function coefficient in a coefficient lookup table according to the index value; obtaining a value of a quadratic polynomial based on the second mantissa sub-segment, a corresponding quadratic function coefficient and fixed-point number multiplication and addition operation; and the post-processing output unit is used for normalizing the value of the quadratic polynomial and outputting a value in a floating-point number format in combination with the sign bit and the order code of the floating-point number, so that the problem that the calculation speed of the activation function is relatively low is solved.

This disclosure describes systems, methods, and devices for probabilistic constellation shaping in wireless transmissions may include a device configured to generate, using a first quadrature amplitude modulation (QAM) order shaping encoder associated with a first code rate, shaped amplitude bits; generate, using a forward error correcting (FEC) encoder and a second code rate smaller than the first code rate, parity bits for the shaped amplitude bits; cause to transmit, using a channel, a first portion of the parity bits as sign bits for the shaped amplitude bits; and cause to transmit, using the channel, a second portion of the parity bits.

An apparatus includes circuitry for a neural network that is configured to perform forward propagation neural network operations on floating point numbers having a first n-bit floating point format. The first n-bit floating point format has a configuration consisting of a sign bit, m exponent bits and p mantissa bits where m is greater than p. The circuitry is further configured to perform backward propagation neural network operations on floating point numbers having a second n-bit floating point format that is different than the first n-bit floating point format. The second n-bit floating point format has a configuration consisting of a sign bit, q exponent bits and r mantissa bits where q is greater than m and r is less than p.

The embodiment of the invention relates to the field of data processing, and discloses a floating-point number operation method and device. According to the method, a difference absolute value of order digits of two floating-point numbers is utilized to perform order alignment on a small mantissa, and a mantissa operation type system signal and a final calculation result sign bit are obtained through sign bit processing operation; if the mantissa operation type system signal indicates to perform negation operation, performing unsigned fixed-point full addition operation by using the large mantissa and the small mantissa subjected to negation operation; performing normalization shift operation on the result of the unsigned fixed-point full addition operation through the leading zero number and the shift remainder of the result of the unsigned fixed-point full addition operation, and performing overflow judgment and result normalization processing on the normalization result by utilizing an index adjustment result and a final calculation result sign bit. In this way, most of the operation logic of original code and complement conversion is omitted, the calculation precision is guaranteed, meanwhile, the scale of a logic circuit is reduced, and the calculation power density is improved.

A floating point arithmetic device with two floating point operands and its operation method are disclosed. The floating point arithmetic device includes an exponent subtraction circuit, an exponent calculation circuit, a mantissa calculation circuit, and a conversion circuit. The exponent subtraction circuit calculates the difference between the exponents of the two operands and generates a sign bit and an exponent difference. The exponent calculation circuit generates the post-operation exponent bits according to the larger one of the exponents of the two operands. The mantissa calculation circuit aligns the mantissa bits of the two operands and performs one of addition and subtraction on the aligned mantissa bits. To improve the calculation efficiency and reduce the power consumption, the floating point arithmetic device can complete the floating point addition or subtraction operation in one step (one clock cycle) without moving the intermediate floating point data between the registers and the functional circuit units as in the multi-step operation.

The invention relates to the technical field of artificial intelligence, in particular to an operation method and an arithmetic unit based on a Point data format.The method comprises the steps that sign bits, exponential expansion bits, mantissa bits and exponential bits of the Point data format are obtained, all the positions of the Point data format are preprocessed, a bit width distribution priority rule is defined, and a bit width distribution priority rule is obtained; multiplying the two mantissa bits obtained by decoding to obtain a mantissa product and a mask sequence; determining a prepositive zero number of the mantissa product according to the mask sequence, and performing unified logic shift on the mantissa product; the method comprises the following steps: carrying out shift on a mantissa part, carrying out rounding operation on the shifted mantissa part, converting a mantissa product into a fixed-point number format according to a sign bit, an exponential expansion bit and an exponential bit, carrying out additive operation based on the fixed-point number, and outputting an accumulation result. The circuit area and power consumption are reduced, complex time sequence control is not needed, and logic resource consumption is reduced.

The invention belongs to the field of computers, and discloses a variable-precision parallelization index floating point number storage and calculation integrated method based on an FPGA (Field Programmable Gate Array), which specifically comprises the following steps of: inputting decimal floating point data; an index floating-point number binary sequence format is defined, decimal floating-point data values are converted into the index floating-point number binary sequence format, parameters of the index floating-point number binary sequence format comprise sign bits, index bits, mantissa bits, specified index offset and mantissa bit width, and the mantissa bit width is dynamically adjusted according to calculation requirements; based on decimal floating point data numerical values, extracting parameters of an index floating point number binary sequence, and storing the parameters in a register of the FPGA as operands; performing displacement sorting on the two operands stored in the register, and calculating an absolute value of a difference between exponent bits and a difference between mantissa bits of the two operands; the problems that in the prior art, a floating-point number storage scheme is low in calculation efficiency and insufficient in precision in an application scene where the dynamic range changes drastically are solved.

Storing floating-point values according to an extended QFloat floating-point (xqFP) format in processor devices is disclosed herein. In some aspects, a processor device comprises a register file comprising a plurality of registers, and comprises a floating-point unit (FPU) circuit that is configured to store a first floating-point value in a register of the plurality of registers. The first floating-point value is formatted according to the xqFP format that comprises an exponent field and a significand field. The significand field is formatted as a signed one's complement value, and comprises a sign bit, an explicit most-significant-bit (MSB), a fractional field, and a deferred increment bit that represents a value of one-half (½) unit of least precision (ULP).

The invention provides a multi-precision floating point fusion multiply-add structure and a microprocessor architecture, and the structure is characterized in that in a first-stage assembly line, an input preprocessing module decomposes an input operand to obtain a sign bit, an index bit and a mantissa bit; the Booth encoder generates partial products through a radix-4 Booth encoding algorithm, and the tree array multiplier compresses the partial products into three groups; in the second-stage assembly line, the CSA4-2 compression adder compresses the mantissa bits after the three groups of partial products and shift alignment into two groups; the summator module sums the two groups of partial products to obtain a mantissa summation result; in the third-stage assembly line package, a leading zero detection module performs leading zero detection on the mantissa summation result, and performs index adjustment and mantissa adjustment to obtain a normalized result; and in the fourth-stage assembly line, rounding of floating point data is carried out. According to the application, the operation performance, the energy efficiency ratio and the adaptability of the floating point fusion multiply-add structure are improved, so that the high performance and the high energy efficiency of the microprocessor are balanced.

A multiplication apparatus includes: a sign calculator adapted to determine a sign bit of a target product based on a sign bit of a first value and a sign bit of a second value; the first value and the second value are floating-point numbers; the compensator is suitable for determining an index flag bit and a first compensation value based on the mantissa bit of the first value and the mantissa bit of the second value; an exponent calculator adapted to determine a first exponent bit based on the exponent bit of the first value and the exponent bit of the second value; determining an index bit of the target product based on the first index bit and the index flag bit; a mantissa calculator adapted to determine a first mantissa bit based on the mantissa bit of the first value and the mantissa bit of the second value; and based on the first mantissa digit and the first compensation value, determining the mantissa digit of the target product, and finally obtaining the target product. According to the scheme, floating-point number multiplication can be converted into floating-point number addition, good approximation precision is achieved, and the area and power consumption of a calculation unit can be reduced.

The invention discloses a method for optimizing ECC (Error Correction Code) protection strength of an NAND FLASH in-memory computing system for an LLM inference chip, and belongs to the technical field of computing, reckoning or counting. Based on an NAND FLASH in-memory computing architecture, the invention provides a self-adaptive sub-plane protection strategy based on a Hamming code, and an error sensitivity grading model of sign bits, index bits and mantissa bits is established by analyzing BF16 numerical value distribution characteristics of large language model weight data; in combination with a residual connection structure of a Transform decoding layer, inter-layer cosine similarity is calculated to evaluate layer importance; and dynamically adjusting the Hamming code protection granularity by adopting a greedy algorithm, and carrying out iterative optimization according to a simulation error injection result until the model confusion degree and the accuracy meet threshold values. And performing ECC software and hardware collaborative design according to an iteration result of the greedy algorithm to obtain an ECC circuit required to be configured by each plane of the NAND flash memory. According to the method, the circuit area power consumption is remarkably reduced while the model reasoning precision is ensured, the ECC bandwidth requirement is reduced, and the large model reasoning efficiency and reliability are remarkably improved.

The invention relates to a task-oriented semantic communication-oriented adaptive source channel coding system, which belongs to the field of wireless communication, and comprises a sending end for extracting a semantic feature map for evaluation from input data through a feature extractor initialized based on a pre-training large model, executing nested quantization and arithmetic coding based on a calculated importance score, and sending the semantic feature map to a task-oriented semantic communication-oriented adaptive source channel coding system; generating a scalable semantic bit stream with importance levels; the physical layer is used for carrying out reordering and grouping according to importance levels of bit streams, a channel encoder is combined with an interleaver to realize unequal error protection of semantic matching, and encoded bits are mapped to sign bits with different fault-tolerant capabilities in a constellation diagram through division modulation; and a receiving end: recovering the semantic feature map through arithmetic decoding and nested inverse quantization. According to the invention, on the premise of keeping compatibility with a digital communication protocol stack, through distortion-driven joint rate self-adaption, the transmission effectiveness for machine tasks and human vision is obviously improved under a limited bandwidth.

A method of rounding a floating-point number in an Extended Exponent Range, herein "EER", that would be a denormal floating-point number represented in an Unextended Exponent Range, herein "UER" is disclosed. The method may comprise the steps of receiving, at an arithmetic unit, a plurality of input numbers in the EER representation, each input number comprising a sign bit (si), exponent bits (ei) and mantissa bits (mi); performing an arithmetic operation to produce an output number in the EER representation comprising a sign bit (sa), an exponent bits (ea) and mantissa bits (ma); constructing a rounding mask based on the exponent bits (ea) computed by the arithmetic operation; and applying the rounding mask to the output number in the EER representation to round the output number to correct position as if rounding in the UER representation.

The invention discloses a circuit for approximate floating point fusion dot product operation. The circuit comprises an extraction module used for extracting sign bits, mantissa bits and exponent bits from four single-precision floating point numbers; the symbol integration module is used for integrating symbol bits and correcting mantissa bits; the index comparison module is used for calculating two groups of dot product effective indexes according to the index bits and generating three control quantities; the first multiplication module is used for generating a first group of approximate partial products according to a correction mantissa digit corresponding to a first control quantity larger value; the second multiplication module is used for generating a second group of approximate partial products according to the correction mantissa digit corresponding to the smaller value of the first control quantity, and performing arithmetic displacement and adding symbol compensation bits according to the size of the second control quantity; the fusion compression module is used for performing fusion compression on the first group of approximate partial products, the second group of approximate partial products after arithmetic shift and the symbol compensation bits to obtain a sum sequence and a carry sequence; and the result output module is used for generating a dot product operation result in combination with the third control quantity.

Performing floating-point operations using an expanded-range floating-point format in processor devices is disclosed herein. In some aspects, a processor device comprises a floating-point unit (FPU) that is configured to perform a floating-point operation using one or more floating-point values interpreted by the FPU according to an expanded-range floating-point format that comprises no sign bit, a plurality of exponent bits including an additional exponent bit relative to a corresponding standard floating-point format, and a plurality of significand bits. The expanded-range floating-point format comprises a same number of bits as the corresponding standard floating-point format. A count of the plurality of significand bits of the expanded-range floating-point format is identical to a count of a plurality of significand bits of the corresponding standard floating-point format, and the significand bits of the expanded-range floating-point format are interpreted in a manner identical to the significand bits of the corresponding standard floating-point format.

Disclosed is a method comprising, by a transmitter apparatus, partitioning (901) an input data stream to obtain a bit stream X1 and a bit stream X2; subjecting (902) the bit stream X2 to encoding by LDPC encoders, to obtain X2 parity bits, and X2 information bits; applying (903) SPC encoding to the X2 parity bits, together with the bit stream X1, to obtain sign bits, wherein the bit stream X1 is used as padding bits; subjecting (904) the sign bits, the padding bits, and the X2 information bits, to an interleaver operation to obtain an interleaver output; subjecting (905) the interleaver output to Gray mapping to form multiple consecutive quadratic amplitude modulation, QAM, symbols; modulating (905) the QAM symbols by quadratic amplitude modulation to obtain a modulated data stream; and transmitting (906) the modulated data stream via a radio access network or optical fibre communication network.

Provided are a multiplier, a multiply-accumulate circuit, an operational circuit, a processor, and a computing device. The operational circuit comprises an input processing circuit (200) and a multiply-accumulate circuit (100). The input processing circuit (200) receives a first number, if the first number is a signed number, negates a sign bit of the first number and then outputs the first number as a first multiplicator for feeding into the multiply-accumulate circuit (100), and if the first number is an unsigned number, directly outputs the first number as the first multiplicator for feeding into the multiply-accumulate circuit (100). The input processing circuit (200) further receives a pre-known second number and directly outputs the second number as a second multiplicator for feeding into the multiply-accumulate circuit (100). The multiply-accumulate circuit (100) comprises a multiply sub-circuit (111) and an accumulate sub-circuit (112). The multiply sub-circuit (111) comprises a multiplier for performing multiplication of the first multiplicator and the second multiplicator and providing an unsigned output. The accumulate sub-circuit (112) receives and accumulates the output of the multiply sub-circuit.

The invention discloses a deep neural network quantization method and system based on beta divergence and soft approximation mapping. According to the method, dynamic distribution statistics is carried out on input data of each batch of a network to obtain data distribution information, AIC is introduced to serve as an evaluation index of distribution goodness of fit, optimal fitting distribution is dynamically selected from multiple distribution models such as normal distribution models, Laplace distribution models and generalized Gaussian distribution models, and the optimal quantization interval is accurately determined; and then constructing a derivable soft rounding approximation function, designing a dynamic slope adjustment mechanism, and adaptively adjusting a slope parameter of a mapping function according to the variance activated and output of each layer, so that the mapping function realizes dynamic balance of quantization and precision in different distribution states. After network training is completed, original floating point number weights are recorded, symmetric quantization is performed to obtain 8-bit integer weights with sign bits, the difference of weight distribution before and after quantization is measured by using improved beta divergence, and quantization weights are guided to approach original floating point weight distribution in a retraining stage, so that quantization errors are reduced.

The invention relates to the field of floating-point multiplication, and particularly discloses a floating-point multiplier based on an FPGA, a calculation method and equipment, and the floating-point multiplier comprises a symbol calculation module which is used for determining the symbol of a target output floating-point number through an exclusive-OR gate and the symbol bits of a first input floating-point number and a second input floating-point number; the index addition module is used for adding the indexes of the first input floating-point number and the second input floating-point number and subtracting the deviation value of the corresponding format to obtain the index output of the target output floating-point number; the binary multiplier module is used for carrying out multiplication operation by using a Karatsuba algorithm and a Urdhva-Tiryagbhyam algorithm based on the mantissa bit widths of the first input floating-point number and the second input floating-point number so as to obtain a mantissa product of the target output floating-point number; and the result normalization module is used for performing normalization operation based on the mantissa product. The calculation delay can be reduced, and the percentage increase of the hardware area is also reduced.

A matrix multiplier includes an input vector scaler generating a first quantization scaled input vector based on a first input vector, a plurality of common scale coefficients, and first-to-Rth multiplication scale coefficients, a first data type converter generating a first fixed point quantization scaled input vector based on the first quantization scaled input vector, an element array comprising a first processing element generating a first fixed point output element based on the first fixed point quantization scaled input vector and first plurality of quantization sign bits, and a second processing element generating a second fixed point output element based on the first fixed point quantization scaled input vector and second plurality of quantization sign bits, and a second data type converter generating and outputting first and second output elements by converting data types of the first and second fixed point output elements.

This application provides a tensor computation method and related apparatus. Through this method, a unified preprocessing is used to obtain the corresponding sign bit, exponent part, and mantissa part for tensors of different data types. Then, through subsequent general exponent accumulation, mantissa multiplication, comparison, shifting, and addition processing, the above unified processing logic can be adapted to the computational needs of different data tensors. Compared with the design idea of ​​equipping each data type with dedicated integrated circuits, this fundamentally eliminates circuit redundancy, thereby reducing chip area, reducing power consumption, and improving flexibility.

The application provides a kind of approximate precoding convolution operation method and system based on booth algorithm, comprising: step S1: multiplier and multiplicand input multiplier are separated by approximate precoding module to partial product, and the partial product related to the multiplicand after separation is input to addition tree module to complete compression, and the partial product related to the multiplicand after compression and the partial product related to the multiplier are added to obtain multiplier result;Step S2: the multiplier result is extended to sign bit, and the extended multiplier result is input into accumulation module to carry out shift and addition operation, and the shift addition operation result is carried out carry compensation.

A matrix multiplier includes an input vector scaler generating a first quantization scaled input vector based on a first input vector, a plurality of common scale coefficients, and first-to-Rth multiplication scale coefficients, a first data type converter generating a first fixed point quantization scaled input vector based on the first quantization scaled input vector, an element array comprising a first processing element generating a first fixed point output element based on the first fixed point quantization scaled input vector and first plurality of quantization sign bits, and a second processing element generating a second fixed point output element based on the first fixed point quantization scaled input vector and second plurality of quantization sign bits, and a second data type converter generating and outputting first and second output elements by converting data types of the first and second fixed point output elements.

According to one aspect of the present disclosure, a method of operating a set of ferroelectric memory cells is provided. The method may include, in a first cycle, writing a first data bit to a first ferroelectric memory cell of the set of ferroelectric memory cells. The method may include, in the first cycle, writing a set of sign bits each having a first value to at least one second ferroelectric memory cell of the set of ferroelectric memory cells. The set of sign bits may indicate a polarity of the set of ferroelectric memory cells. The method may include, in a second cycle subsequent to the first cycle, reading the set of sign bits from the at least one second ferroelectric memory cell. The method may include, in the second cycle, performing an error-correction operation on the set of sign bits to determine the first value of the set of sign bits written in the first cycle.

A system and method of decoding a sub-block of residual coefficients of a transform block from a video bitstream. The method comprises determining whether sign bit hiding is used for the sub-block, the determination based on a value of a transform skip flag determined for the sub-block and a value of a sign bit hiding flag associated with the sub-block; if sign bit hiding is not used, decoding a number of sign bits equal to a number of significant coefficients in the subblock; and decoding the sub-block by reconstructing the residual coefficients of the sub-block using the decoded sign bits.

The application discloses a model training process-oriented computing power chip hardware Trojan design method, and relates to the field of integrated circuit security.The method is designed in view of the computing architecture of a GPU, and contains a flip-flop, a finite state machine and a load circuit.The flip-flop identifies the typical characteristics of deep learning training by monitoring the arithmetic instruction intensity and the Warp concurrent activity of the GPU runtime; when the characteristics meet a preset threshold, the finite state machine is triggered, so that the hardware Trojan enters an activated state.The load circuit has two types of designs: the first type is a gradient flipping circuit which interferes with the gradient update direction by modifying the sign bit output by a floating point calculation unit, so that the model cannot converge; the second type is a redundant calculation circuit which consumes computing resources by inserting invalid floating point operations, thereby prolonging the training time.The application designs and triggers the hardware Trojan by utilizing the architecture characteristics of the GPU, has high concealment, and can effectively destroy the accuracy and efficiency of a deep learning training task.

The invention belongs to the field of multiplying units, and particularly discloses a multiplying unit operation method, a multiplying unit, a field-programmable gate array and a digital circuit, a multiplier is coded through Booth coding, and coding is carried out according to sign bit information of the multiplier for a sign integer multiplier; carrying out multiplication operation on the generated codes by utilizing a cross multiplication principle of the bark multiplication; and adding the multiplication operation result to obtain a final multiplication operation result. According to the invention, Booth coding and Vedic multiplication (bark multiplication) are combined, the operation speed is improved, area reduction and resource optimization are realized, and the performance of the multiplier is improved.

The invention provides a data processing method and system and related equipment, and can be applied to the technical field of computers. The method includes acquiring a first group of data including first data and second data, and outputting a second group of data including third data and fourth data. Wherein the first data and the second data occupy a first number of bits, the third data and the fourth data are data obtained by compressing the first data and the second data respectively, the third data occupy a second number of bits, the fourth data occupy a fourth number of bits, and the sum of the second number and the third number is smaller than or equal to the first number. The sum of the fourth number and the third number is smaller than or equal to the first number, and the third number is the number of bits occupied by sign bits and index bits of the floating point type data. Therefore, according to the method, the number of bits occupied by the compressed data can be far smaller than the number of bits occupied by the data before compression, the compression ratio of the data is reduced, and therefore the data storage cost of the database is reduced.

The invention discloses a preprocessing method and a receiver adapted to intensity changes of pseudo satellite pulse signals, and the method comprises the steps: converting a high-bit-width digital intermediate frequency signal outputted by a high-bit-width analog-to-digital conversion chip into a low-bit-width digital intermediate frequency signal adaptive to a capture circuit and a tracking circuit; through a preprocessing circuit, the amplitude of an input signal of a high-bit-width analog-to-digital conversion chip is controlled, and when no pseudo-satellite pulse signal is input, the output power of an amplifier is controlled, so that the amplitude bit of a high-bit-width digital intermediate frequency signal is low 3 bits, and the rest are sign bits; the control parameter is the same as that when no pseudo-satellite pulse signal is input; under the conditions of not changing the data bit width in the existing capture circuit and tracking circuit and not obviously increasing the logic resources of the circuit, the receiver can adapt to satellite navigation signals and pseudo satellite pulse signals with variable strength, and the application range of the navigation receiver is expanded.