268 results about "Sign bit" patented technology

The present invention may be embodied in a magnetic disk, of a disk drive, having eight-bit fields storing wedge repeatable runout (WRRO) compensation values and redundancy information. The WRRO compensation value of each field includes a six-bit binary value of which five bits represent a compensation magnitude and one bit represents a sign bit indicating a compensation direction. The redundancy information of each field has a first bit based on the sign bit.

A rounding circuit is provided that includes an input for receiving a 2's complement number to be rounded. The 2's complement number has a format SXY, where S represents a sign bit, X represents one or more bits to round and keep, and Y represents one or more bits to be discarded. The rounding circuit also includes first logic for adding a rounding bias to the 2's complement number, and second logic for at least one of subtracting the sign bit S from the 2's complement number, or adding the inverted sign bit !S to the 2's complement number. Moreover, the rounding circuit includes third logic for truncating Y bits from a result produced by the first and second logic to produce a rounded 2's complement number having a format SX.

The method includes following steps: scanning DCT coefficient blocks according to sequence so as to obtain last one nonzero coefficient (NC) and the coefficient in front of the last one NC in coefficient block, and number value of NC; based on the number value of NC to calculate difference value between number value of NC in this block and number value of NC in adjacent block, and constructing context model for number value of NC; calculating flag bit of NC for last one NC and coefficients before the last one NC; selecting context model to encode flag bit of NC; subtracting 1 from absolute value of NC according to scanning sequence or scanning inverted sequence; and selecting context model to encode number value of NC, and its position in the scan etc; encoding sign bit. The invention also discloses corresponding decoding method.

A method for performing a power of two estimation on a floating-point number within a data processing system is disclosed. The floating-point number includes a sign bit, multiple exponent bits, and a mantissa having an implied one and multiple fraction bits. In order to estimate the power of two of the floating-point number, the mantissa is partitioned into an integer part and a fraction part, based on the value of the exponent bits. A floating-point result is formed by assigning the integer part of the floating-point number as an unbiased exponent of the floating-point result, and by converting the fraction part of the floating-point number via a table lookup to become a fraction part of the floating-point result.

The invention discloses an intelligence quotient (IQ) data compression method and a device. The method comprises the following steps of: dividing m continuous IQ data into one group, and obtaining data with the maximum numerical value in each group of data; intercepting continuous n-bit seniority effective data and sign bits of the data with the maximum numerical value in the group of data, and deleting the rest low-bit data in the data with the maximum numerical value; intercepting the continuous n bit seniority effective data and sign bits of the other m-1 data in the group of data, and deleting the rest low-bit data in the other m-1 data; and determining compression factors of the group according to the bit number of the deleted low-bit data, and sending the compression factors and the compressed IQ data. When the technical scheme of the invention is adopted, the requirement of eNodeB wireless equipment on optical modules and optical fiber can be effectively reduced, and the cost of base station equipment is reduced.

An exponent preprocessing unit preprocesses an n-bit exponent k and exponentiates a base A by the preprocessed exponent k. A bit string storing unit stores a bit string including a sign bit and the exponent k. A reading unit reads a bit pattern composed of the sign bit and a bit sequence made up of a predetermined number of bits. A bit pattern generating unit generates a new bit pattern from the read bit pattern. An operation pattern specifying unit specifies an operation pattern based on the read bit pattern. An operating unit performs an operation according to the specified operation pattern and writes the new bit pattern over the previous bit pattern. The reading unit reads a next bit sequence starting from a different bit in the bit string storing unit. A repeat controlling unit repeats these procedures n+1 times.

A thermometer code to sign and magnitude converter that is particularly useful in a flash ADC is provided. This comprises two conversion units. The first is a thermometer code to Gray code converter and the second a Gray code to sign and magnitude converter. Preferably, the Gray code is of a kind that has a sign bit and has the other bits symmetrically disposed about zero. This form is easily converted to a sign and magnitude code, which is advantageous as it reduces the latency of the converter, which is particularly useful at high data rates.

A scalable audio codec processes, quantizes and encodes audio signals into an embedded audio bitstream of bit-planes each having a data unit. The data unit has a beginning refinement bits partition, a second significance bits partition, a third sign boundary mark bits partition, and a fourth sign bits partition. The second and fourth partitions form a boundary for the third partition. The quantizing uses a variable length coding algorithm. The third partition is an invalid codeword for a predetermined encoding method being used to encode. The codec uses a decoder to decode the embedded audio bitstream of bit-planes using Reversible exponential Golomb (Exp-Golomb) codes in a Reversible Variable Length Code (RVLC) algorithm to produce quantized data of weighted subbands. An inverse quantizer dequantizes the quantized data into audio signals.

Removing adverse effects in case error detection using error detection codes cannot be performed correctly, and improving the data transmission efficiency. The turbo decoder 6 compares data which is decoded this time with data which is decoded previous time, both of which are decoded in repetitive decoding processing, to obtain discord number information indicative of the number of discordant sign bits, and sends the information to a terminal I/F unit 7 and a packet flow retransmission controlling unit 10. Even though it is determined that error detection result from a CRC recalculating unit 9 shows that there exists no bit error, in case the number of discordant sign bits is larger than a predetermined threshold value, it is determined that there is generated error. And, a packet flow retransmission controlling unit 10 sends a signal requesting retransmission of data. Furthermore, data amount to be retransmitted is varied in accordance with the number of discordant sign bits to improve the data transmission efficiency.

An iterative decoder includes at respective variable nodes, that is, at nodes that correspond to the bits of the code word, bit error detectors that after convergence determine if the respective hard decision bit values have changed from the bit values provided by the channel. The change in value for a given bit indicates that a bit error has been corrected. The bit error detector, for message-passing decoders that perform calculations by addition rather than multiplication, can be readily implemented as an XOR gate. Thus, a bit error is detected at the variable node by XOR'ing the sign bits of the input symbol and the variable node sum. After convergence, the output values produced by the bit error detectors at the respective variable nodes are added together using an adder tree that accumulates the detected bit errors for an entire date block, or ECC code word. Alternatively, the system may group the bits into respective code word symbols and combine the bit error values into symbols-with-errors values using, for example, XOR sub-trees that produce, for each symbol, a single error value. The error value for a given symbol indicates that the symbol is either error-free or includes one or more bit errors, and a total count of the symbols with errors is produced by adding the error values together.

A source encoder encodes audio signals into increasing quality layers defined in bit planes. Each bit plane has a data unit that includes a beginning partition having one or more contiguous refinement bits, a second partition having one or more contiguous coded significance bits, a third partition having one or more contiguous sign boundary mark bits, and a fourth partition having one or more contiguous coded sign bits. A channel encoder encodes the bit planes into respective columns containing multiple rows. Unequal error protection coding is provided according to the quality of each layer such that each row has row and column channel protection codes for the respective row and column that correspond to the respective quality layer. For the corresponding row and column, each row contains the row channel protection codes and either the compressed audio data from the respective layer or the column channel protection codes. A server machine can use a network feedback transmission to allocate bits to the source encoder and the channel encoder.

The invention discloses a carrier frequency synchronous circuit and method of an OFDM (Orthogonal Frequency Division Multiplexing) system. The carrier frequency synchronous circuit comprises a decimal fraction frequency offset estimation circuit, a decimal fraction frequency offset compensation circuit, an integer frequency offset estimation circuit, an integer frequency offset compensation circuit and other circuits; correspondingly, the method comprises the following steps of decimal fraction frequency offset estimation, decimal fraction frequency offset compensation, integer frequency offset estimation and integer frequency offset compensation; a cross-correlation value of two adjacent synchronous sequences to be sampled of a frequency domain is subjected to normalization treatment to obtain a decimal fraction frequency offset estimation value, and decimal fraction frequency offset compensation correction is carried out by utilizing the estimation value; then, the high energy carrier sign bit of each OFDM sign subjected to fast Fourier transform (FFT) treatment is subjected to self-correlation computation, the self-correlation of a plurality of OFDM signs is subjected to summation computation to obtain an integer frequency offset estimation value, and then integer frequency offset compensation is carried out according to the integer frequency offset estimation value. By adopting the synchronous circuit and method, the computational burden can be reduced, the influence of noise to frequency offset estimation can be lowered, and low-power equipment is favorably designed and realized.

The invention provides a high-speed divider comprising a coded conversion module, a sign bit decision module, a nonzero bit search module, a reciprocal value lookup module, a correction adjusting module and a multiplication processing module. The coded conversion module is sequentially connected with the sign bit decision module, the nonzero bit search module, the reciprocal value lookup module, the correction adjusting module and the multiplication processing module; the coded conversion module, the sign bit decision module are respectively connected with the multiplication processing module; and the output end of the multiplication processing module outputs the results of division operation. The high-speed divider has controllable operation accuracy, not only can freely set the corresponding operation accuracy according to the actual application requirements, but also can be used for high-speed mathematical operation processing with short operation time and small processed delay, and has simple structure and good feasibility.

The invention discloses a divider and a divider operation method, and belongs to the technical field of the digital signal processing circuit. The divider adopts a cardinal number N algorithm, wherein N is 2i, i is a positive integer greater than or equal to 3, and the quotient of an initial dividend and an initial divisor is greater than or equal to -N or less than or equal to N. The divider comprises a sign bit determining unit (1), a divisor multiple calculation unit (2) and an iterative computation unit (3), wherein the sign bit determining unit (1) is used for judging the sign bit of a quotient result of the initial dividend and the initial divisor; the divisor multiple calculation unit (2) is used for calculating the P times of a numerical value bit of a non-zero initial divisor to obtain a Pth numerical value multiple value, wherein P takes an integral value successively in an interval 1-N so as to obtain N divisor multiple values; and the iterative computation unit (3) is used for carrying out K-time iterative computation on the numerical value bit of the initial dividend and N divisor multiple values to obtain an initial quotient value result. During the iterative computation of the divider, the bit of the quotient generated each time can be flexibly selected, and excessive hardware areas are not occupied while a quick operation is carried out.

The invention relates to a floating point addition device based on complement rounding, which supports the floating point addition operation and the floating point subtraction operation. The floatingpoint addition device comprises an exponent adder, a mantissa shifter, a mantissa operand preparation logic unit, a mantissa adder, a rounding judgment logic unit and a rounding adder, wherein the mantissa operand preparation logic unit is used for processing the mantissa operand according to sign bits and the exponent difference of the first floating point operand and the second floating point operand, the rounding judgment logic unit is used for executing the uniform rounding judgment on a mantissa addition result, judging the positive and the negative of the mantissa sum according to the highest bit output by the mantissa adder, determining a constant bit for the rounding judgment according to the highest four bits output by the mantissa adder, and unifying original code rounding plus 1judgment logic and complement rounding plus 0 judgment logic; and the rounding adder is used for rounding the mantissa addition result of the floating point and finishing the code extraction and complement operation to the mantissa sum. The invention has the uniform mechanism, avoids the special complex mantissa operand preparation and rounding judgment logic of the floating point addition, and reduces the logic complexity.

The invention discloses an encryption domain H.264/AVC video reversible data hiding method. Under the premise that the encryption domain H.264/AVC video reversible data hiding method is compatible with an H.264/AVC video compressed encoding standard, code words of prediction modes, Exp-Golomb code words of motion vector difference and sign bits of residual error coefficients are selected to be encrypted, computation complexity is low, the application demands of real-time videos are met, and encryption safety is high. Meanwhile, influences of encryption on the code rate of code streams of H.264/AVC videos are quite small, and the problem of data expansion in the video encryption process is solved. A data hiding person can embed private information in the H.264/AVC videos of an encryption domain directly, and thus the problems of video content safety and privacy disclosure can be solved effectively. The hidden data can be extracted effectively from the encryption domain and can also be extracted effectively from a decryption domain, namely, data extraction and data decryption are separated completely, and practicality is high. In addition, the encryption domain H.264/AVC video reversible data hiding method is completely revisable, and original videos can be restored without damage after the hidden information is decrypted and extracted.

A method for performing fast multiplication in a microprocessor is disclosed. The method comprises detecting multiplication operations that have a floating point operand and an integer operand, wherein the integer operand is an integer power of two. Once detected, a multiplication operation meeting these criteria may be executed by using an integer adder to sum the integer power and the floating point operand's exponent to from a product exponent. The bias of the integer operand's exponent may also be subtracted. A product mantissa is simply copied from the floating point operand's mantissa. The floating point operand's sign bit may be inverted to form the product's sign bit if the integer operand is negative. Advantageously, the product is generated using integer addition which is faster than floating point multiplication. The method may be implemented in hardware or software.

In accordance with some embodiments, a floating point number datapath circuitry, e.g., within an integrated circuit programmable logic device is provided. The datapath circuitry may be used for computing a rounded absolute value of a mantissa of a floating point number. The floating point datapath circuitry may have only a single adder stage for computing a rounded absolute value of a mantissa of the floating point number based on one or more bits of an unrounded mantissa of the floating point number. The unrounded and rounded mantissas may include a sign bit, a sticky bit, a round bit, and/or a least significant bit, and/or other bits. The unrounded mantissa may be in a format that includes negative numbers (e.g., 2's complement) and the rounded mantissa may be in a format that may include a portion of the floating point number represented as a positive number, (e.g., signed magnitude).

A comparator (231) for determining a peak number, representing a maximum or minimum of a set of numbers, includes a multi-element comparator (232) for comparing different pages of the set of numbers in a page comparison mode to output a candidate set of winning numbers, and for automatically switching to a leaf/tree search of the candidate set of winning numbers in an element comparison mode. Operating in parallel with the multi-element comparator (232), an index generation unit (233) processes flag/sign bits from the multi-element comparator in conjunction with state machine control logic (230) to keep track of the index/indices for the peak value. Upon completion of final stage, the index generation unit returns the absolute index (235) of the peak value.

Methods of encoding and decoding for video data are described for encoding or decoding coefficients for a transform unit. In particular, the sign bits for the non-zero coefficients are encoded using sign bit hiding. Two or more sets of coefficients are defined for the transform unit and a sign bit may be hidden for each set, subject to satisfaction of a threshold test. The sets may correspond to coefficient groups that are otherwise used in multi-level significance map encoding and decoding.

A computation unit comprises a floating point input having X bits including a sign bit, an E bit exponent and an M bit mantissa. A first circuit is operatively coupled to receive X-N bits of the input, including e1 bits of the exponent and ml bits of the mantissa, where e1≤E, and m1≤M, to output values over a first domain of the input. A second circuit is operatively coupled to receive X-K bits of the input, including e2 bits of the exponent, e2<e1, and m2 bits of the mantissa, m2>m1, to output values, over a second domain of the input. A range detector is operatively coupled to the input, to indicate a range in response to a value of the input. A selector can select the output of the first circuit or of the second circuit in response to the range detector.

The invention relates to the technical field of application security, and specifically discloses a data encryption based safety use method of configuration file. The method comprises the steps of reading plaintexts of the configuration file; respectively determining whether the read plaintexts include identifiers; if so, reading the property value of the configuration file; encrypting the property value through an asymmetric key, a symmetric key or a certificate; backfilling the encrypted data in the property value to the plaintexts of the original configuration file to cover; adding the predefined sign bit as a marker of the encrypted configuration file; performing the following steps; if not so and that the property value of the read configuration file includes the predefined sign bit during use, identifying the configuration file into ciphertexts, and decrypting the property value for use; if the predefined sign bit cannot be read during use, directly using the configuration file, and repeatedly encrypting the property value. According to the method, the encrypting mode is set to protect the sensitive information in the configuration file, and the configuration file can be conveniently modified.

The invention relates to a wave recording data processing method and a system. The method comprises a data zipping step which includes the following aspects in details: calculating data difference; extracting from the data difference value the sign bits and combining them into symbol characters for storage; dividing the absolute value of the data difference value into fragments in an equal length; gathering how many times the fragments appear and taking their appearing times as weights to generate a fragment Huffman coding tree; gathering how many times measuring ranges appear and taking their appearing times as weights for to generate a measuring range Huffman coding tree; and according to the Huffman coding trees, coding and storing the data difference fragments and the measuring ranges; In the invention, a wave shape data zipping file storing structure comprises a recording head and a recording medium. The recording head comprises recording basic information, coding tree information and coding zone information. The recording medium comprises a coding tree zone, a symbol coding zone, a measuring range coding zone and a data difference coding zone. The system consists of a CPU processor, a sampling system, an external storing device and a wave recording triggering system. The sampling system, the external storing device and the wave recording triggering system are all connected to the CPU processor respectively. According to the invention, the compression ratio is influenced by waveform distortion to a small extent. The method and system are suitable for mixed zipping of state quantity and analog quantity. As they consume less processing memory and time, so they are cost-effective in implementation.