Floating point addition device based on complement rounding

Abstract

The invention relates to a floating point addition device based on complement rounding, which supports the floating point addition operation and the floating point subtraction operation. The floatingpoint addition device comprises an exponent adder, a mantissa shifter, a mantissa operand preparation logic unit, a mantissa adder, a rounding judgment logic unit and a rounding adder, wherein the mantissa operand preparation logic unit is used for processing the mantissa operand according to sign bits and the exponent difference of the first floating point operand and the second floating point operand, the rounding judgment logic unit is used for executing the uniform rounding judgment on a mantissa addition result, judging the positive and the negative of the mantissa sum according to the highest bit output by the mantissa adder, determining a constant bit for the rounding judgment according to the highest four bits output by the mantissa adder, and unifying original code rounding plus 1judgment logic and complement rounding plus 0 judgment logic; and the rounding adder is used for rounding the mantissa addition result of the floating point and finishing the code extraction and complement operation to the mantissa sum. The invention has the uniform mechanism, avoids the special complex mantissa operand preparation and rounding judgment logic of the floating point addition, and reduces the logic complexity.

Description

technical field [0001] The invention relates to a microprocessor architecture design, in particular to a floating point operation unit. Background technique [0002] Floating-point operations are ubiquitous in real life, and scientific operations, signal processing, media applications, and information communications all require a large number of floating-point operations. Before the 1980s, various computer manufacturers had different rules for supporting floating-point operations, which brought great changes to the transplantation of floating-point applications on different computer platforms. For this reason, IEEE proposed a set of floating-point arithmetic standards "IEEE-754 for Binary Float-point Arithmetic" in 1985, which has now become an international general standard. In this standard, four floating-point representation formats are proposed: single-precision, double-precision, extended single-precision, and extended double-precision, and specifically define floating...

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Problems solved by technology

[0015] In order to overcome the inconsistency and high logic complexity of existing floating-point addition components, the present invention provides a unified mechanism, which avoids complex mantissa operand preparation and rounding judgment logic unique to floating-point addition, and reduces logic complexity. Degree of floating-point addition device based on two's-complement rounding

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