54results about How to "Simplify Logic Design" patented technology

A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.

The invention provides a step counting method based on autocorrecting computing which comprises the following steps: collecting N three-axis acceleration data in a current time window by a three-axis acceleration sensor of a pedometer, calculating the module values of the N three-axis acceleration data and storing the calculated module values; collecting and calculating the module values of N three-axis acceleration data in a next time window, and taking the first L module values to be put behind the N module values to obtain N+L merged data, denoting the N+L merged data as sample data x (n); performing filtering and autocorrecting computing on the sample data x (n) to detect the number of wave crests of the sample data x (n); taking the number of wave crests as the step number detected in the current time window, and adding the step number and the current total step number together to obtain new current total step number; taking the next time window of the current time window as a new current time window and repeating the steps until the movement course is finished. According to the step counting method based on autocorrecting computing provided by the invention, through autocorrecting computing, the periodic features of periodic signals are highlighted in signals containing a great deal of noise, and the effective step number is detected according to the counted number of crest values of autocorrelation function, and the step counting accuracy is effectively improved.

The invention discloses an error correction method for dynamic refreshing of a ROM (read only memory) mapping zone and a configuration zone in SRAM (static random access memory) type FRGA (field programmable gate array). The method includes: firstly, reading configuration information in configuration files and shielding information in mask word files, determining dynamic refresh prohibited portions and dynamic refresh permitted portions in the configuration information, and classifying the corresponding configuration information of the ROM mapping zone in the configuration zone into dynamic refresh permitted portions; secondly, recording the configuration information into a new configuration file, and identifying whether the configuration information allows to be dynamically refreshed or not in the FPGA embedded logic operating state in the new configuration file; thirdly, using a logic control circuit to read in the configuration information and identification from the new configuration file during dynamic refreshing, and only reading the dynamic refresh permitted configuration information in the configuration zone of the FRGA. Using the method can permit dynamic data refreshing of the ROM mapping zone during repeated data refreshing of the configuration zone, so that accuracy of the data stored in the ROM can be guaranteed.

System and method of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.